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dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICU
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software interrupts and aggregate error interrupts. It has 16 software triggered interrupts (INTCPUn), 16 external pin interrupts (IRQn), a System error interrupt (SEI), two Cortex-A55 error interrupts (CA55_ERRn), two Cortex-R52 error interrupts for each of the two cores (CR52x_ERRn), two Peripheral error interrupts (PERI_ERRn), two DSMIF error interrupts (DSMIF_ERRn), and two ENCIF error interrupts (ENCIF_ERRn). The IRQn and SEI interrupts are exposed externally, while the others are software triggered. INTCPU0 to INTCPU13, IRQ 0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Document them, and use RZ/T2H as a fallback for RZ/N2H as the ICU is entirely compatible. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251201112933.488801-2-cosmin-gabriel.tanislav.xa@renesas.com
This commit is contained in:
Cosmin Tanislav
Thomas Gleixner
parent
8d4c354bef
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-icu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{T2H,N2H} Interrupt Controller
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maintainers:
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- Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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description:
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The Interrupt Controller (ICU) handles software-triggered interrupts
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(INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC
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requests.
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properties:
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compatible:
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oneOf:
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- const: renesas,r9a09g077-icu # RZ/T2H
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- items:
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- enum:
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- renesas,r9a09g087-icu # RZ/N2H
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- const: renesas,r9a09g077-icu
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reg:
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items:
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- description: Non-safety registers (INTCPU0-13, IRQ0-13)
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- description: Safety registers (INTCPU14-15, IRQ14-15, SEI)
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'#interrupt-cells':
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description: The first cell is the SPI number of the interrupt, as per user
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manual. The second cell is used to specify the flag.
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const: 2
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'#address-cells':
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const: 0
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interrupt-controller: true
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interrupts:
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items:
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- description: Software interrupt 0
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- description: Software interrupt 1
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- description: Software interrupt 2
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- description: Software interrupt 3
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- description: Software interrupt 4
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- description: Software interrupt 5
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- description: Software interrupt 6
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- description: Software interrupt 7
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- description: Software interrupt 8
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- description: Software interrupt 9
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- description: Software interrupt 10
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- description: Software interrupt 11
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- description: Software interrupt 12
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- description: Software interrupt 13
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- description: Software interrupt 14
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- description: Software interrupt 15
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- description: External pin interrupt 0
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- description: External pin interrupt 1
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- description: External pin interrupt 2
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- description: External pin interrupt 3
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- description: External pin interrupt 4
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- description: External pin interrupt 5
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- description: External pin interrupt 6
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- description: External pin interrupt 7
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- description: External pin interrupt 8
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- description: External pin interrupt 9
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- description: External pin interrupt 10
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- description: External pin interrupt 11
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- description: External pin interrupt 12
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- description: External pin interrupt 13
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- description: External pin interrupt 14
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- description: External pin interrupt 15
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- description: System error interrupt
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- description: Cortex-A55 error event 0
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- description: Cortex-A55 error event 1
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- description: Cortex-R52 CPU 0 error event 0
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- description: Cortex-R52 CPU 0 error event 1
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- description: Cortex-R52 CPU 1 error event 0
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- description: Cortex-R52 CPU 1 error event 1
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- description: Peripherals error event 0
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- description: Peripherals error event 1
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- description: DSMIF error event 0
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- description: DSMIF error event 1
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- description: ENCIF error event 0
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- description: ENCIF error event 1
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interrupt-names:
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items:
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- const: intcpu0
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- const: intcpu1
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- const: intcpu2
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- const: intcpu3
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- const: intcpu4
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- const: intcpu5
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- const: intcpu6
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- const: intcpu7
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- const: intcpu8
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- const: intcpu9
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- const: intcpu10
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- const: intcpu11
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- const: intcpu12
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- const: intcpu13
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- const: intcpu14
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- const: intcpu15
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- const: irq0
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- const: irq1
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- const: irq2
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- const: irq3
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- const: irq4
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- const: irq5
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- const: irq6
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- const: irq7
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- const: irq8
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- const: irq9
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- const: irq10
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- const: irq11
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- const: irq12
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- const: irq13
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- const: irq14
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- const: irq15
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- const: sei
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- const: ca55-err0
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- const: ca55-err1
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- const: cr520-err0
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- const: cr520-err1
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- const: cr521-err0
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- const: cr521-err1
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- const: peri-err0
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- const: peri-err1
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- const: dsmif-err0
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- const: dsmif-err1
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- const: encif-err0
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- const: encif-err1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- interrupts
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- interrupt-names
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- clocks
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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icu: interrupt-controller@802a0000 {
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compatible = "renesas,r9a09g077-icu";
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reg = <0x802a0000 0x10000>,
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<0x812a0000 0x50>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "intcpu0", "intcpu1", "intcpu2",
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"intcpu3", "intcpu4", "intcpu5",
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"intcpu6", "intcpu7", "intcpu8",
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"intcpu9", "intcpu10", "intcpu11",
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"intcpu12", "intcpu13", "intcpu14",
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"intcpu15",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"irq8", "irq9", "irq10", "irq11",
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"irq12", "irq13", "irq14", "irq15",
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"sei",
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"ca55-err0", "ca55-err1",
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"cr520-err0", "cr520-err1",
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"cr521-err0", "cr521-err1",
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"peri-err0", "peri-err1",
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"dsmif-err0", "dsmif-err1",
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"encif-err0", "encif-err1";
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clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
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power-domains = <&cpg>;
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};
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