- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
- Support for NCO blocks on Apple SoCs
* clk-range:
clk: Drop the rate range on clk_put()
clk: test: Test clk_set_rate_range on orphan mux
clk: Initialize orphan req_rate
clk: bcm: rpi: Run some clocks at the minimum rate allowed
clk: bcm: rpi: Set a default minimum rate
clk: bcm: rpi: Add variant structure
clk: Add clk_drop_range
clk: Always set the rate on clk_set_range_rate
clk: Use clamp instead of open-coding our own
clk: Always clamp the rounded rate
clk: Enforce that disjoints limits are invalid
clk: Introduce Kunit Tests for the framework
clk: Fix clk_hw_get_clk() when dev is NULL
* clk-uniphier:
clk: uniphier: Fix fixed-rate initialization
* clk-apple:
clk: clk-apple-nco: Allow and fix module building
MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE
clk: clk-apple-nco: Add driver for Apple NCO
dt-bindings: clock: Add Apple NCO
* clk-qcom: (61 commits)
clk: qcom: gcc-msm8994: Fix gpll4 width
dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
clk: qcom: Add display clock controller driver for SM6125
dt-bindings: clock: add QCOM SM6125 display clock bindings
clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig
clk: qcom: gcc: Add emac GDSC support for SM8150
clk: qcom: gcc: sm8150: Fix some identation issues
clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150
clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
clk: qcom: clk-rcg2: Update the frac table for pixel clock
clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
clk: qcom: smd: Add missing MSM8998 RPM clocks
clk: qcom: smd: Add missing RPM clocks for msm8992/4
dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks
clk: qcom: gcc-ipq806x: add CryptoEngine resets
dt-bindings: reset: add ipq8064 ce5 resets
clk: qcom: gcc-ipq806x: add CryptoEngine clocks
dt-bindings: clock: add ipq8064 ce5 clk define
clk: qcom: gcc-ipq806x: add additional freq for sdc table
clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
...
Here are the big set of tty and serial driver changes for 5.18-rc1.
Nothing major, some more good cleanups from Jiri and 2 new serial
drivers. Highlights include:
- termbits cleanups
- export symbol cleanups and other core cleanups from Jiri Slaby
- new sunplus and mvebu uart drivers (amazing that people are
still creating new uarts...)
- samsung serial driver cleanups
- ldisc 29 is now "reserved" for experimental/development line
disciplines
- lots of other tiny fixes and cleanups to serial drivers and
bindings
All of these have been in linux-next for a while with no reported
issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'tty-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver updates from Greg KH:
"Here are the big set of tty and serial driver changes for 5.18-rc1.
Nothing major, some more good cleanups from Jiri and 2 new serial
drivers. Highlights include:
- termbits cleanups
- export symbol cleanups and other core cleanups from Jiri Slaby
- new sunplus and mvebu uart drivers (amazing that people are still
creating new uarts...)
- samsung serial driver cleanups
- ldisc 29 is now "reserved" for experimental/development line
disciplines
- lots of other tiny fixes and cleanups to serial drivers and
bindings
All of these have been in linux-next for a while with no reported
issues"
* tag 'tty-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (104 commits)
vt_ioctl: fix potential spectre v1 in VT_DISALLOCATE
serial: 8250: fix XOFF/XON sending when DMA is used
tty: serial: samsung: Add ARTPEC-8 support
dt-bindings: serial: samsung: Add ARTPEC-8 UART
serial: sc16is7xx: Clear RS485 bits in the shutdown
tty: serial: samsung: simplify getting OF match data
tty: serial: samsung: constify variables and pointers
tty: serial: samsung: constify s3c24xx_serial_drv_data members
tty: serial: samsung: constify UART name
tty: serial: samsung: constify s3c24xx_serial_drv_data
tty: serial: samsung: reduce number of casts
tty: serial: samsung: embed s3c2410_uartcfg in parent structure
tty: serial: samsung: embed s3c24xx_uart_info in parent structure
serial: 8250_tegra: mark acpi_device_id as unused with !ACPI
tty: serial: bcm63xx: use more precise Kconfig symbol
serial: SERIAL_SUNPLUS should depend on ARCH_SUNPLUS
tty: serial: jsm: fix two assignments in if conditions
tty: serial: jsm: remove redundant assignments to variable linestatus
serial: 8250_mtk: make two read-only arrays static const
serial: samsung_tty: do not unlock port->lock for uart_write_wakeup()
...
Here is the big set of staging driver updates for 5.18-rc1.
Loads of tiny cleanups for almost all staging drivers in here, nothing
major at all. Highlights include:
- remove the ashmem Android driver. It is long-dead and if
there are any legacy userspace applications still using it,
the Android kernel images will maintain it, the community
shouldn't care about it anymore
- wfx wifi driver major cleanups. Should be ready to merge out
of staging soon, and will coordinate with the wifi maintainers
after -rc1 is out
- major cleanups and unwinding of the layers of the r8188eu
driver. It's amazing just how many unneeded layers of
abstraction is in there, just when we think it's done, another
is found...
- lots of tiny coding style cleanups in many other staging
drivers.
There will be merge conflict with a fbtft change and the spi driver
changes in your tree, but it's pretty obvious what to do (the function
shouldn't return anything.)
All have been in linux-next for a while with no reported problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging driver updates from Greg KH:
"Here is the big set of staging driver updates for 5.18-rc1.
Loads of tiny cleanups for almost all staging drivers in here, nothing
major at all. Highlights include:
- remove the ashmem Android driver. It is long-dead and if there are
any legacy userspace applications still using it, the Android
kernel images will maintain it, the community shouldn't care about
it anymore
- wfx wifi driver major cleanups. Should be ready to merge out of
staging soon, and will coordinate with the wifi maintainers after
-rc1 is out
- major cleanups and unwinding of the layers of the r8188eu driver.
It's amazing just how many unneeded layers of abstraction is in
there, just when we think it's done, another is found...
- lots of tiny coding style cleanups in many other staging drivers.
All have been in linux-next for a while with no reported problems"
* tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (455 commits)
staging: r8188eu: remove unnecessary memset in r8188eu
staging: greybus: introduce pwm_ops::apply
staging: rts5208: Resolve checkpatch.pl issues.
staging: sm750fb: fix naming style
staging: fbtft: Consider type of init sequence values in fbtft_init_display()
staging: fbtft: Constify buf parameter in fbtft_dbg_hex()
staging: mmal-vchiq: clear redundant item named bulk_scratch
mips: dts: ralink: add MT7621 SoC
staging: r8188eu: remove some unused local ieee80211 macros
staging: r8188eu: make rtl8188e_process_phy_info static
staging: r8188eu: remove unused function prototype
staging: r8188eu: remove three unused receive defines
staging: r8188eu: remove unnecessary initializations
staging: rtl8192e: Fix spelling mistake "RESQUEST" -> "REQUEST"
MAINTAINERS: remove the obsolete file entry for staging in ANDROID DRIVERS
staging: r8188eu: proper error handling in rtw_init_drv_sw
staging: r8188eu: call _cancel_timer_ex from _rtw_free_recv_priv
staging: vt6656: Removed unused variable vt3342_vnt_threshold
staging: vt6656: Removed unused variable bb_vga_0
staging: remove ashmem
...
- Add Krzysztof Kozlowski as co-maintainer for DT bindings providing
much needed help.
- DT schema validation now takes DTB files as input rather than
intermediate YAML files. This decouples the validation from the source
level syntax information. There's a bunch of schema fixes as a result
of switching to DTB based validation which exposed some errors
and incomplete schemas and examples.
- Kbuild improvements to explicitly warn users running 'make
dt_binding_check' on missing yamllint
- Expand DT_SCHEMA_FILES kbuild variable to take just a partial filename
or path instead of the full path to 1 file.
- Convert various bindings to schema format: mscc,vsc7514-switch,
multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS
bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel
SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display
subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma,
msm/mdp4, rda,8810pl-uart
- New schemas for u-boot environment variable partition, TI clksel
- New compatible strings for Renesas RZ/V2L SoC
- Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated HiSilicon
- Add/fix schemas for QEMU Arm 'virt' machine
- Drop unused of_alias_get_alias_list() function
- Add a script to check DT unittest EXPECT message output. Pass messages
also now print by default at PR_INFO level to help test automation.
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Merge tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Add Krzysztof Kozlowski as co-maintainer for DT bindings providing
much needed help.
- DT schema validation now takes DTB files as input rather than
intermediate YAML files. This decouples the validation from the
source level syntax information. There's a bunch of schema fixes as a
result of switching to DTB based validation which exposed some errors
and incomplete schemas and examples.
- Kbuild improvements to explicitly warn users running 'make
dt_binding_check' on missing yamllint
- Expand DT_SCHEMA_FILES kbuild variable to take just a partial
filename or path instead of the full path to 1 file.
- Convert various bindings to schema format: mscc,vsc7514-switch,
multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS
bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel
SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display
subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma,
msm/mdp4, rda,8810pl-uart
- New schemas for u-boot environment variable partition, TI clksel
- New compatible strings for Renesas RZ/V2L SoC
- Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated
HiSilicon
- Add/fix schemas for QEMU Arm 'virt' machine
- Drop unused of_alias_get_alias_list() function
- Add a script to check DT unittest EXPECT message output. Pass
messages also now print by default at PR_INFO level to help test
automation.
* tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (96 commits)
dt-bindings: kbuild: Make DT_SCHEMA_LINT a recursive variable
dt-bindings: nvmem: add U-Boot environment variables binding
dt-bindings: ufs: qcom: Add SM6350 compatible string
dt-bindings: dmaengine: sifive,fu540-c000: include generic schema
dt-bindings: gpio: pca95xx: drop useless consumer example
Revert "of: base: Introduce of_alias_get_alias_list() to check alias IDs"
dt-bindings: virtio,mmio: Allow setting devices 'dma-coherent'
dt-bindings: gnss: Add two more chips
dt-bindings: gnss: Rewrite sirfstar binding in YAML
dt-bindings: gnss: Modify u-blox to use common bindings
dt-bindings: gnss: Rewrite common bindings in YAML
dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible
dt-bindings: ata: ahci-platform: Add power-domains property
dt-bindings: ata: ahci-platform: Convert DT bindings to yaml
dt-bindings: kbuild: Use DTB files for validation
dt-bindings: kbuild: Pass DT_SCHEMA_FILES to dt-validate
dt-bindings: Add QEMU virt machine compatible
dt-bindings: arm: Convert QEMU fw-cfg to DT schema
dt-bindings: i2c: at91: Add SAMA7G5 compatible strings list
dt-bindings: i2c: convert i2c-at91 to json-schema
...
* Support for Sv57-based virtual memory.
* Various improvements for the MicroChip PolarFire SOC and the
associated Icicle dev board, which should allow upstream kernels to
boot without any additional modifications.
* An improved memmove() implementation.
* Support for the new Ssconfpmf and SBI PMU extensions, which allows for
a much more useful perf implementation on RISC-V systems.
* Support for restartable sequences.
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Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for Sv57-based virtual memory.
- Various improvements for the MicroChip PolarFire SOC and the
associated Icicle dev board, which should allow upstream kernels to
boot without any additional modifications.
- An improved memmove() implementation.
- Support for the new Ssconfpmf and SBI PMU extensions, which allows
for a much more useful perf implementation on RISC-V systems.
- Support for restartable sequences.
* tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits)
rseq/selftests: Add support for RISC-V
RISC-V: Add support for restartable sequence
MAINTAINERS: Add entry for RISC-V PMU drivers
Documentation: riscv: Remove the old documentation
RISC-V: Add sscofpmf extension support
RISC-V: Add perf platform driver based on SBI PMU extension
RISC-V: Add RISC-V SBI PMU extension definitions
RISC-V: Add a simple platform driver for RISC-V legacy perf
RISC-V: Add a perf core library for pmu drivers
RISC-V: Add CSR encodings for all HPMCOUNTERS
RISC-V: Remove the current perf implementation
RISC-V: Improve /proc/cpuinfo output for ISA extensions
RISC-V: Do no continue isa string parsing without correct XLEN
RISC-V: Implement multi-letter ISA extension probing framework
RISC-V: Extract multi-letter extension names from "riscv, isa"
RISC-V: Minimal parser for "riscv, isa" strings
RISC-V: Correctly print supported extensions
riscv: Fixed misaligned memory access. Fixed pointer comparison.
MAINTAINERS: update riscv/microchip entry
riscv: dts: microchip: add new peripherals to icicle kit device tree
...
Consumer examples in the bindings of resource providers are trivial,
useless and duplication of code. Remove the example code for consumer
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'clocks' in the example is not parsable with the 0 phandle value
because the number of #clock-cells is unknown in the previous entry.
Solve this by adding the clock provider node. Only 'cpg_clocks' is
needed as the examples are built with fixups which can be used to
identify phandles.
This is in preparation to support schema validation on .dtb files.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220301190400.1644150-1-robh@kernel.org
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
qcom,gcc-other Documentation lacks a '|' for the description. This cause
dt_binding_check to incorrectly parse "See also:" as a new value.
Add the missing '|' to correctly parse the description.
Fixes: a03965ed13 ("dt-bindings: clock: split qcom,gcc.yaml to common and specific schema")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20220323194248.26970-1-ansuelsmth@gmail.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
After a somewhat quiet 5.17 release, the size of the DT changes
is a bit larger again. There are nine new SoC that get added,
all of them related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the
LG Nexus 5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs,
along with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC losely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added all
over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner,
i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)
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Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"After a somewhat quiet 5.17 release, the size of the DT changes is a
bit larger again. There are nine new SoC that get added, all of them
related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added
all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic:
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno:
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar:
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)"
* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
arm64: dts: n5x: drop invalid property and fix edac node name
arm64: dts: fsd: Add the MCT support
arm64: dts: stingray: Fix spi clock name
arm64: dts: ns2: Fix spi clock name
ARM: dts: rockchip: Update regulator name for PX3
ARM: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
ARM: dts: at91: sama7g5: Add NAND support
ARM: dts: at91: sama7g5: add eic node
ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
arm64: dts: lg: align pl330 node name with dtschema
arm64: dts: lg: add dma-cells to pl330 node
arm64: dts: juno: align pl330 node name with dtschema
arm64: dts: broadcom: Fix sata nodename
arm64: dts: n5x: add sdr edac support
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
dt-bindings: usb: dwc2: add disable-over-current
...
There are a few separately maintained driver subsystems that we merge through
the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs,
and clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport based
on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ
and older NVIDIA Tegra chips
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Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are a few separately maintained driver subsystems that we merge
through the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs, and
clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport
based on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
NVIDIA Tegra chips"
* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
ARM: spear: fix typos in comments
soc/microchip: fix invalid free in mpfs_sys_controller_delete
soc: s4: Add support for power domains controller
dt-bindings: power: add Amlogic s4 power domains bindings
ARM: at91: add support in soc driver for new SAMA5D29
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
memory: emif: check the pointer temp in get_device_details()
memory: emif: Add check for setup_interrupts
dt-bindings: arm: mediatek: mmsys: add support for MT8186
dt-bindings: mediatek: add compatible for MT8186 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
soc: mediatek: mmsys: add mmsys reset control for MT8186
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
soc: ti: k3-socinfo: Add AM62x JTAG ID
soc: mediatek: add MTK mutex support for MT8186
soc: mediatek: mmsys: add mt8186 mmsys routing table
soc: mediatek: pm-domains: Add support for mt8186
dt-bindings: power: Add MT8186 power domains
soc: mediatek: pm-domains: Add support for mt8195
...
Add binding for Renesas 9-series PCIe clock generators. This binding
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators, currently the only tested and supported chip
is 9FGV0241.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-1-marex@denx.de
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The NCO block found on Apple SoCs is a programmable clock generator
performing fractional division of a high frequency input clock.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20220208183411.61090-2-povik+lin@cutebit.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-5-kernel@esmil.dk
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
clocks. The gcc node is also used by the tsens driver, already documented,
to get the calib nvmem cells and the base reg from gcc. Use
qcom,gcc.yaml as a template and remove the compatible from
generic qcom,gcc-other.yaml
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-4-ansuelsmth@gmail.com
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
template and remove the compatible from qcom,gcc.yaml
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-3-ansuelsmth@gmail.com
Split qcom,gcc.yaml to common and specific schema to use it as a
template for schema that needs to use the gcc bindings and require
to add additional bindings.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-2-ansuelsmth@gmail.com
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM6350 SoCs.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220222011534.3502-3-konrad.dybcio@somainline.org
Add the clock dt-binding file for i.MX93.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* 'mstar-dt-next' of https://github.com/linux-chenxing/linux:
ARM: mstar: Extend opp_table for infinity2m
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for infinity
ARM: mstar: Link cpupll to second core
ARM: mstar: Link cpupll to cpu
ARM: mstar: Add cpupll to base dtsi
dt-bindings: clk: mstar msc313 cpupll binding description
ARM: dts: mstar: Add board for 100ask DongShanPiOne
dt-bindings: arm: mstar: Add compatible for 100ask DongShanPiOne
dt-bindings: vendor-prefixes: Add prefix for 100ask
ARM: dts: mstar: Add a dts for Miyoo Mini
dt-bindings: arm: mstar: Add compatible for Miyoo Mini
dt-bindings: vendor-prefixes: Add prefix for Miyoo
ARM: dts: mstar: Add the Wireless Tag IDO-SBC2D06-V1B-22W
dt-bindings: add vendor prefix for Wireless Tag
ARM: dts: mstar: Set gpio compatible for ssd20xd
Link: https://lore.kernel.org/r/20220216193131.59794-1-romain.perier@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Qualcomm SC8280XP has a RPMh clock controller, so add a compatible
for this to the binding.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220223044516.3776637-1-bjorn.andersson@linaro.org
The driver can parse bi-tcxo clock from the clocks passed in the device
tree. Specify it in schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220215201539.3970459-3-dmitry.baryshkov@linaro.org
The compatible string is already in use, fix the binding to include it.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Add a binding description for the MStar/SigmaStar CPU PLL block.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Make system controller a reset provider for all the peripherals in the
MT7621 SoC adding '#reset-cells' property.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In order to prepare for fixing lots of devicetree unique_unit_address
warnings for the TI clock nodes, let's add a binding for the TI clksel
clocks. This allows us to move the overlapping reg properties for the
component clocks to be children of the related clksel nodes. And with
that we need the reg property only for the parent clksel node making
the reg property unique like it should be.
We want to set #clock-cells = <2> in case we ever start parsing ranges
of clkcsel instances directly using a clksel driver rather than using the
existing component clock drivers and child nodes.
And before the devicetree files can be updated, we need to update the
TI clock drivers to get the IO address from the parent clksel node.
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220203073929.59296-1-tony@atomide.com
Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This new flag exists to enable the dynamic mode of the hardware.
When not given, the static mode is used.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220125093336.226787-5-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This mode allows the PLL to maintain lock even when CLK_IN has
missing pulses for up to 20 ms.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220125093336.226787-4-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This new optional property can be used to control the function of the
auxiliary output pin. Introduce a new dt-bindings include file that
contains the numerical values.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220125093336.226787-3-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support. Per usual (or maybe just recent trends), Qualcomm gains a
handful of SoC drivers additions and has the largest diffstat. After
that there are quite a few updates to the Allwinner (sunxi) drivers to
support modular drivers and Renesas is heavily updated to add more
support for various clks. Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock
drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a couple patches in the framework core this time around but
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support.
Per usual (or maybe just recent trends), Qualcomm gains a handful of
SoC drivers additions and has the largest diffstat. After that there
are quite a few updates to the Allwinner (sunxi) drivers to support
modular drivers and Renesas is heavily updated to add more support for
various clks.
Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in
drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2
clock drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits)
clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
clk: mediatek: add mt7986 clock support
clk: mediatek: add mt7986 clock IDs
dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
clk: x86: Fix clk_gate_flags for RV_CLK_GATE
clk: x86: Use dynamic con_id string during clk registration
ACPI: APD: Add a fmw property clk-name
drivers: acpi: acpi_apd: Remove unused device property "is-rv"
x86: clk: clk-fch: Add support for newer family of AMD's SOC
clk: ingenic: Add MDMA and BDMA clocks
dt-bindings: clk/ingenic: Add MDMA and BDMA clocks
clk: bm1880: remove kfrees on static allocations
clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
clk: st: clkgen-mux: search reg within node or parent
clk: st: clkgen-fsyn: search reg within node or parent
clk: Enable/Disable runtime PM for clk_summary
MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
clk: visconti: Add support common clock driver and reset driver
...
Bindings:
- DT schema conversions for Samsung clocks, RNG bindings, Qcom Command
DB and rmtfs, gpio-restart, i2c-mux-gpio, i2c-mux-pinctl, Tegra I2C
and BPMP, pwm-vibrator, Arm DSU, and Cadence macb
- DT schema conversions for Broadcom platforms: interrupt controllers,
STB GPIO, STB waketimer, STB reset, iProc MDIO mux, iProc PCIe,
Cygnus PCIe PHY, PWM, USB BDC, BCM6328 LEDs, TMON, SYSTEMPORT, AMAC,
Northstar 2 PCIe PHY, GENET, moca PHY, GISB arbiter, and SATA
- Add binding schemas for Tegra210 EMC table, TI DC-DC converters,
- Clean-ups of MDIO bus schemas to fix 'unevaluatedProperties' issues
- More fixes due to 'unevaluatedProperties' enabling
- Data type fixes and clean-ups of binding examples found in preparation
to move to validating DTB files directly (instead of intermediate YAML
representation.
- Vendor prefixes for T-Head Semiconductor, OnePlus, and Sunplus
- Add various new compatible strings
DT core:
- Silence a warning for overlapping reserved memory regions
- Reimplement unittest overlay tracking
- Fix stack frame size warning in unittest
- Clean-ups of early FDT scanning functions
- Fix handling of "linux,usable-memory-range" on EFI booted systems
- Add support for 'fail' status on CPU nodes
- Improve error message in of_phandle_iterator_next()
- kbuild: Disable duplicate unit-address warnings for disabled nodes
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Merge tag 'devicetree-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"Bindings:
- DT schema conversions for Samsung clocks, RNG bindings, Qcom
Command DB and rmtfs, gpio-restart, i2c-mux-gpio, i2c-mux-pinctl,
Tegra I2C and BPMP, pwm-vibrator, Arm DSU, and Cadence macb
- DT schema conversions for Broadcom platforms: interrupt
controllers, STB GPIO, STB waketimer, STB reset, iProc MDIO mux,
iProc PCIe, Cygnus PCIe PHY, PWM, USB BDC, BCM6328 LEDs, TMON,
SYSTEMPORT, AMAC, Northstar 2 PCIe PHY, GENET, moca PHY, GISB
arbiter, and SATA
- Add binding schemas for Tegra210 EMC table, TI DC-DC converters,
- Clean-ups of MDIO bus schemas to fix 'unevaluatedProperties' issues
- More fixes due to 'unevaluatedProperties' enabling
- Data type fixes and clean-ups of binding examples found in
preparation to move to validating DTB files directly (instead of
intermediate YAML representation.
- Vendor prefixes for T-Head Semiconductor, OnePlus, and Sunplus
- Add various new compatible strings
DT core:
- Silence a warning for overlapping reserved memory regions
- Reimplement unittest overlay tracking
- Fix stack frame size warning in unittest
- Clean-ups of early FDT scanning functions
- Fix handling of "linux,usable-memory-range" on EFI booted systems
- Add support for 'fail' status on CPU nodes
- Improve error message in of_phandle_iterator_next()
- kbuild: Disable duplicate unit-address warnings for disabled nodes"
* tag 'devicetree-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (114 commits)
dt-bindings: net: mdio: Drop resets/reset-names child properties
dt-bindings: clock: samsung: convert S5Pv210 to dtschema
dt-bindings: clock: samsung: convert Exynos5410 to dtschema
dt-bindings: clock: samsung: convert Exynos5260 to dtschema
dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
dt-bindings: clock: samsung: convert Exynos7 to dtschema
dt-bindings: clock: samsung: convert Exynos5433 to dtschema
dt-bindings: i2c: maxim,max96712: Add bindings for Maxim Integrated MAX96712
dt-bindings: iio: adi,ltc2983: Fix 64-bit property sizes
dt-bindings: power: maxim,max17040: Fix incorrect type for 'maxim,rcomp'
dt-bindings: interrupt-controller: arm,gic-v3: Fix 'interrupts' cell size in example
dt-bindings: iio/magnetometer: yamaha,yas530: Fix invalid 'interrupts' in example
dt-bindings: clock: imx5: Drop clock consumer node from example
dt-bindings: Drop required 'interrupt-parent'
dt-bindings: net: ti,dp83869: Drop value on boolean 'ti,max-output-impedance'
dt-bindings: net: wireless: mt76: Fix 8-bit property sizes
dt-bindings: PCI: snps,dw-pcie-ep: Drop conflicting 'max-functions' schema
dt-bindings: i2c: st,stm32-i2c: Make each example a separate entry
dt-bindings: net: stm32-dwmac: Make each example a separate entry
dt-bindings: net: Cleanup MDIO node schemas
...
- Clock and reset driver for Toshiba Visconti SoCs
* clk-socfpga:
clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource()
clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource()
clk: socfpga: remove redundant assignment after a mask operation
clk: socfpga: remove redundant assignment on division
* clk-toshiba:
clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
clk: visconti: Add support common clock driver and reset driver
dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC
dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC
* clk-st:
clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
clk: st: clkgen-mux: search reg within node or parent
clk: st: clkgen-fsyn: search reg within node or parent
* clk-bitmain:
clk: bm1880: remove kfrees on static allocations
* clk-x86:
clk: x86: Fix clk_gate_flags for RV_CLK_GATE
clk: x86: Use dynamic con_id string during clk registration
ACPI: APD: Add a fmw property clk-name
drivers: acpi: acpi_apd: Remove unused device property "is-rv"
x86: clk: clk-fch: Add support for newer family of AMD's SOC
clk: Introduce clk-tps68470 driver
platform/x86: int3472: Deal with probe ordering issues
platform/x86: int3472: Pass tps68470_regulator_platform_data to the tps68470-regulator MFD-cell
platform/x86: int3472: Pass tps68470_clk_platform_data to the tps68470-regulator MFD-cell
platform/x86: int3472: Add get_sensor_adev_and_name() helper
platform/x86: int3472: Split into 2 drivers
platform_data: Add linux/platform_data/tps68470.h file
i2c: acpi: Add i2c_acpi_new_device_by_fwnode() function
i2c: acpi: Use acpi_dev_ready_for_enumeration() helper
ACPI: delay enumeration of devices with a _DEP pointing to an INT3472 device
* clk-stm:
clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell
* clk-amlogic:
clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
* clk-allwinner:
clk: sunxi-ng: Add support for the D1 SoC clocks
clk: sunxi-ng: gate: Add macros for gates with fixed dividers
clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw
clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw
clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw
dt-bindings: clk: Add compatibles for D1 CCUs
clk: sunxi-ng: Allow the CCU core to be built as a module
clk: sunxi-ng: Convert early providers to platform drivers
clk: sunxi-ng: Allow drivers to be built as modules
clk: sunxi-ng: Export symbols used by CCU drivers
The UFS for Exynos7 SoC clock controller requires additional input
clocks for the FSYS1 clock controller. Update the bindings to reflect
this, at least in theory. In practice, these input clocks are ignored,
so it is rather adjusting of bindings to existing DTS, without affecting
any real users. I understand that is not how it should be done,
though...
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220102115356.75796-5-krzysztof.kozlowski@canonical.com
The example nodes have different sized interrupt cells which is not valid
given no interrupt-parent is specified. As provider examples don't need to
show the consumer side in the first place, just drop the consumer node.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220106182518.1435497-1-robh@kernel.org
This adds support for the StarFive JH7100, including the necessary
device drivers and DT files for the BeagleV Starlight prototype
board, with additional boards to be added later. This SoC promises
to be the first usable low-cost platform for RISC-V.
I've taken this through the SoC tree in the anticipation of adding
a few other Arm based SoCs as well, but those did not pass the
review in time, so it's only this one.
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Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull RISC-V SoC updates from Arnd Bergmann:
"Add support for StarFive JH7100 RISC-V SoC
This adds support for the StarFive JH7100, including the necessary
device drivers and DT files for the BeagleV Starlight prototype board,
with additional boards to be added later. This SoC promises to be the
first usable low-cost platform for RISC-V.
I've taken this through the SoC tree in the anticipation of adding a
few other Arm based SoCs as well, but those did not pass the review in
time, so it's only this one"
* tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
reset: starfive-jh7100: Fix 32bit compilation
RISC-V: Add BeagleV Starlight Beta device tree
RISC-V: Add initial StarFive JH7100 device tree
serial: 8250_dw: Add StarFive JH7100 quirk
dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
pinctrl: starfive: Add pinctrl driver for StarFive SoCs
dt-bindings: pinctrl: Add StarFive JH7100 bindings
dt-bindings: pinctrl: Add StarFive pinctrl definitions
reset: starfive-jh7100: Add StarFive JH7100 reset driver
dt-bindings: reset: Add Starfive JH7100 reset bindings
dt-bindings: reset: Add StarFive JH7100 reset definitions
clk: starfive: Add JH7100 clock generator driver
dt-bindings: clock: starfive: Add JH7100 bindings
dt-bindings: clock: starfive: Add JH7100 clock definitions
dt-bindings: interrupt-controller: Add StarFive JH7100 plic
dt-bindings: timer: Add StarFive JH7100 clint
RISC-V: Add StarFive SoC Kconfig option
This introduces initial support for the brand new Snapdragon 8 Gen 1,
aka SM8450 platform, with SMP, CPUfreq, cluster idling, low speed buses,
TLMM pinctrl, SMMU, regulators, clocks, power-domains, UFS storage and
USB currently supported.
SDM845 adds new support for Sony Xperia XZ2, XZ2C and XZ3. The Lenovo
Yoga C630 gains a few audio related fixes. The PMIC's VADC channels are
described as thermal zones. OnePlus devices gains msm-id and board-id,
to facilitate a single firmware image for the multiple devices.
On SM8350 the Sony Xperia 1 III and 5 III, as well as initial
description of Microsoft's Surface Duo 2 are introduced. On the
platform side, LLCC, QUP nodes, redistributor stride and all the
low-speed QUPs are added
MSM8996 gained various regulator fixes, and adsp firmware name to
faciliate pushing firmware to linux-firmware. Xiaomi Mi Note 2 gained
touchkey controller definition.
On SDM660 the Xiaomi Redmi Note 7 gained power and volume keys, RPM and
regulator definitions, USB, eMMC and SD-card and a simple-framebuffer
description.
MSM8916 has the mmc aliases corrected, to stop the storage devices to
move around and the RPM sleep stats memory is described. Support for the
Samsung J5 2015 smartphone is introduced.
SM6350 validation errors are fixed and and description of the audio,
compute and modem remoteprocs are added.
A couple new revisions of the SC7180 based Google devices are added.
The SC7280 platform gains venus and a few fixes. The CRD development
device is introduced, with the EC, touchscreen and touchpad.
On SM8250 CPU opp-tables, for scaling L3 cache and DDR frequency based
on CPU frequency, are added. As is TX, RX macros and SoundWire blocks
and used to enable audio on the SM8350 MTP.
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Merge tag 'qcom-arm64-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DeviceTree updates for v5.17
This introduces initial support for the brand new Snapdragon 8 Gen 1,
aka SM8450 platform, with SMP, CPUfreq, cluster idling, low speed buses,
TLMM pinctrl, SMMU, regulators, clocks, power-domains, UFS storage and
USB currently supported.
SDM845 adds new support for Sony Xperia XZ2, XZ2C and XZ3. The Lenovo
Yoga C630 gains a few audio related fixes. The PMIC's VADC channels are
described as thermal zones. OnePlus devices gains msm-id and board-id,
to facilitate a single firmware image for the multiple devices.
On SM8350 the Sony Xperia 1 III and 5 III, as well as initial
description of Microsoft's Surface Duo 2 are introduced. On the
platform side, LLCC, QUP nodes, redistributor stride and all the
low-speed QUPs are added
MSM8996 gained various regulator fixes, and adsp firmware name to
faciliate pushing firmware to linux-firmware. Xiaomi Mi Note 2 gained
touchkey controller definition.
On SDM660 the Xiaomi Redmi Note 7 gained power and volume keys, RPM and
regulator definitions, USB, eMMC and SD-card and a simple-framebuffer
description.
MSM8916 has the mmc aliases corrected, to stop the storage devices to
move around and the RPM sleep stats memory is described. Support for the
Samsung J5 2015 smartphone is introduced.
SM6350 validation errors are fixed and and description of the audio,
compute and modem remoteprocs are added.
A couple new revisions of the SC7180 based Google devices are added.
The SC7280 platform gains venus and a few fixes. The CRD development
device is introduced, with the EC, touchscreen and touchpad.
On SM8250 CPU opp-tables, for scaling L3 cache and DDR frequency based
on CPU frequency, are added. As is TX, RX macros and SoundWire blocks
and used to enable audio on the SM8350 MTP.
* tag 'qcom-arm64-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (92 commits)
arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX
arm64: dts: qcom: sm8450-qrd: Enable USB nodes
arm64: dts: qcom: sm8450: Add usb nodes
arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes
arm64: dts: qcom: sm8450: add cpufreq support
arm64: dts: qcom: sm8450: Add rpmhpd node
arm64: dts: qcom: sm8450-qrd: enable ufs nodes
arm64: dts: qcom: sm8450: add ufs nodes
arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes
arm64: dts: qcom: Add base SM8450 QRD DTS
arm64: dts: qcom: sm8450: add smmu nodes
arm64: dts: qcom: sm8450: Add reserved memory nodes
arm64: dts: qcom: sm8450: Add tlmm nodes
arm64: dts: qcom: Add base SM8450 DTSI
arm64: dts: qcom: ipq6018: Fix gpio-ranges property
arm64: dts: qcom: sdm845: add QFPROM chipset specific compatible
arm64: dts: qcom: sdm845: mtp: Add vadc channels and thermal zones
arm64: dts: qcom: pm8998: Add ADC Thermal Monitor node
arm64: qcom: dts: drop legacy property #stream-id-cells
Revert "arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer"
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
To SDX55 this introduces the description of the IPA, PCIe PHY and PCIe
endpoint controller, as well as enables these for the FN960 device.
The SDX65 5G platform is introduced, currently with definitions
necessary to boot to a shell.
The undocumented property "input-name" is dropped throughout the dts
files, dwc3 nodes throughout gains more specific compatibles and lastly
building of the Dragonboard 410c DTB on ARM32 is enabled, in addition to
its normal operation in 64-bit mode.
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Merge tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm DeviceTree updates for v5.17
To SDX55 this introduces the description of the IPA, PCIe PHY and PCIe
endpoint controller, as well as enables these for the FN960 device.
The SDX65 5G platform is introduced, currently with definitions
necessary to boot to a shell.
The undocumented property "input-name" is dropped throughout the dts
files, dwc3 nodes throughout gains more specific compatibles and lastly
building of the Dragonboard 410c DTB on ARM32 is enabled, in addition to
its normal operation in 64-bit mode.
* tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: Drop input-name property
ARM: dts: qcom: sdx65: Add pincontrol node
ARM: dts: qcom: Add SDX65 platform and MTP board support
dt-bindings: arm: qcom: Document SDX65 platform and boards
dt-bindings: clock: Add SDX65 GCC clock bindings
ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32
ARM: dts: qcom: sdx55-t55: Enable IPA
ARM: dts: qcom: sdx55-fn980: Enable IPA
ARM: dts: qcom: sdx55-fn980: Enable PCIe EP
ARM: dts: qcom: sdx55: Add support for PCIe EP
ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY
ARM: dts: qcom: sdx55: Add support for PCIe PHY
ARM: dts: qcom: update USB nodes with new platform specific compatible
Link: https://lore.kernel.org/r/20211221042154.3621955-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Provide dt-schema documentation for Exynos7885 SoC clock controller.
Description is modified from Exynos850 clock controller documentation as
I couldn't describe it any better, that was written by Sam Protsenko.
Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211206153124.427102-3-virag.david003@gmail.com
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to them, clock controller is in charge of managing power for them.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Document the required properties and firmware clocks for gcc-msm8976 to
operate nominally, and add header definitions for referencing the clocks
from firmware.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211208091036.132334-2-marijn.suijten@somainline.org
v5.16-rc1 + 20211207114003.100693-2-vkoul@kernel.org
The immutable branch contains the DT binding and clock defines as need
for the Qualcomm SM8450 global clock controller driver.
Add bindings for the clock generator on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Add device tree bindings for global clock controller on SM8450 SoCs.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211207114003.100693-2-vkoul@kernel.org
Allow to add an optional resource to be able to access the clock gate
registers.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-3-horatiu.vultur@microchip.com
This adds the DT bindings documentation for lan966x SoC
generic clock controller.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-3-kavyasree.kotagiri@microchip.com
The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with
3 and 4 clock inputs, respectively. Add the compatibles and bindings.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org
CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
clocks are needed for HSI2C_3 and HSI2C_4 instances.
Add clock indices and bindings documentation for CMU_CMGP domain.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-4-semen.protsenko@linaro.org
CMU_APM generates clocks for APM IP-core (Active Power Management). In
particular it generates RTC clocks, which are needed to enable rtc-s3c
driver on Exynos850 SoC.
Add clock indices and binding documentation for CMU_APM.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-2-semen.protsenko@linaro.org
- 2 fixes due to DT node name changes on Arm, Ltd. boards
- Treewide rename of Ingenic CGU headers
- Update ST email addresses
- Remove Netlogic DT bindings
- Dropping few more cases of redundant 'maxItems' in schemas
- Convert toshiba,tc358767 bridge binding to schema
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Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:
- Two fixes due to DT node name changes on Arm, Ltd. boards
- Treewide rename of Ingenic CGU headers
- Update ST email addresses
- Remove Netlogic DT bindings
- Dropping few more cases of redundant 'maxItems' in schemas
- Convert toshiba,tc358767 bridge binding to schema
* tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dt-bindings: watchdog: sunxi: fix error in schema
bindings: media: venus: Drop redundant maxItems for power-domain-names
dt-bindings: Remove Netlogic bindings
clk: versatile: clk-icst: Ensure clock names are unique
of: Support using 'mask' in making device bus id
dt-bindings: treewide: Update @st.com email address to @foss.st.com
dt-bindings: media: Update maintainers for st,stm32-hwspinlock.yaml
dt-bindings: media: Update maintainers for st,stm32-cec.yaml
dt-bindings: mfd: timers: Update maintainers for st,stm32-timers
dt-bindings: timer: Update maintainers for st,stm32-timer
dt-bindings: i2c: imx: hardware do not restrict clock-frequency to only 100 and 400 kHz
dt-bindings: display: bridge: Convert toshiba,tc358767.txt to yaml
dt-bindings: Rename Ingenic CGU headers to ingenic,*.h
a little more time to soak in linux-next.
- Use modern i2c probe in vc5
- Cleanup some includes
- Update links to datasheets
- Add UniPhier NX1 SoC clk support
- Fix DT bindings for SiFive FU740
- Revert the module platform driver support for Rockchip out
because it wasn't actually tested
- Fix the composite clk code again as the previous fix had a
one line bug that broke rate changes for clks that want to use
the same parent still
- Use the right table for a divider in ast2600 driver
- Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
its critical but unused
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"This is the second batch of clk driver updates that needed a little
more time to soak in linux-next.
- Use modern i2c probe in vc5
- Cleanup some includes
- Update links to datasheets
- Add UniPhier NX1 SoC clk support
- Fix DT bindings for SiFive FU740
- Revert the module platform driver support for Rockchip because it
wasn't actually tested
- Fix the composite clk code again as the previous fix had a one line
bug that broke rate changes for clks that want to use the same
parent still
- Use the right table for a divider in ast2600 driver
- Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
its critical but unused"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk
clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
clk/ast2600: Fix soc revision for AHB
clk: composite: Fix 'switching' to same clock
clk: rockchip: drop module parts from rk3399 and rk3568 drivers
Revert "clk: rockchip: use module_platform_driver_probe"
clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c
dt-bindings: clock: fu740-prci: add reset-cells
clk: uniphier: Add SoC-glue clock source selector support for Pro4
dt-bindings: clock: uniphier: Add clock binding for SoC-glue
clk: uniphier: Add NX1 clock support
dt-bindings: clock: uniphier: Add NX1 clock binding
clk: uniphier: Add audio system and video input clock control for PXs3
clk: si5351: Update datasheet references
clk: vc5: Use i2c .probe_new
clk/actions/owl-factor.c: remove superfluous headers
clk: ingenic: Fix bugs with divided dividers
Not all @st.com email address are concerned, only people who have
a specific @foss.st.com email will see their entry updated.
For some people, who left the company, remove their email.
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Cc: Fabien Dessenne <fabien.dessenne@foss.st.com>
Cc: Christophe Roullier <christophe.roullier@foss.st.com>
Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: Lionel Debieve <lionel.debieve@foss.st.com>
Cc: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Cc: Ludovic Barre <ludovic.barre@foss.st.com>
Cc: Christophe Kerello <christophe.kerello@foss.st.com>
Cc: pascal Paillet <p.paillet@foss.st.com>
Cc: Erwan Le Ray <erwan.leray@foss.st.com>
Cc: Philippe CORNU <philippe.cornu@foss.st.com>
Cc: Yannick Fertre <yannick.fertre@foss.st.com>
Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Cc: Olivier Moysan <olivier.moysan@foss.st.com>
Cc: Hugues Fruchet <hugues.fruchet@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-By: Vinod Koul <vkoul@kernel.org>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20211110150144.18272-6-patrice.chotard@foss.st.com
Signed-off-by: Rob Herring <robh@kernel.org>
Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files
related to Ingenic SoCs with 'ingenic,'.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
- Remove support for TI TPS80031/TPS80032 PMICs
- New Device Support
- Add support for Magnetic Reader to TI AM335x
- Add support for DA9063_EA to Dialog DA9063
- Add support for SC2730 PMIC to Spreadtrum SC27xx
- Add support for MacBookPro16,2 ICL-N UART Intel LPSS PCI
- Add support for lots of new PMICS in QCom SPMI PMIC
- Add support for ADC to Diolan DLN2
- New Functionality
- Add support for Power Off to Rockchip RK817
- Fix-ups
- Simplify Regmap passing to child devices; hi6421-spmi-pmic
- SPDX licensing updates; ti_am335x_tscadc
- Improve error handling; ti_am335x_tscadc
- Expedite clock search; ti_am335x_tscadc
- Generic simplifications; ti_am335x_tscadc
- Use generic macros/defines; ti_am335x_tscadc
- Remove unused code; ti_am335x_tscadc, cros_ec_dev
- Convert to GPIOD; wcd934x
- Add namespacing; ti_am335x_tscadc
- Restrict compilation to relevant arches; intel_pmt
- Provide better description/documentation; exynos_lpass
- Add SPI device ID table; altera-a10sr, motorola-cpcap, sprd-sc27xx-spi
- Change IRQ handling; qcom-pm8xxx
- Split out I2C and SPI code; arizona
- Explicitly include used headers; altera-a10sr
- Convert sysfs show() function to; sysfs_emit
- Standardise *_exit() and *_remove() return values; mc13xxx, stmpe, tps65912
- Trivial (style/spelling/whitespace) fixups; ti_am335x_tscadc, qcom-spmi-pmic,
max77686-private
- Device Tree fix-ups; ti,am3359-tscadc, samsung,s2mps11, samsung,s2mpa01,
samsung,s5m8767, brcm,misc, brcm,cru, syscon, qcom,tcsr,
xylon,logicvc, max77686, x-powers,ac100, x-powers,axp152,
x-powers,axp209-gpio, syscon, qcom,spmi-pmic
- Bug Fixes
- Balance refcounting (get/put); ti_am335x_tscadc, mfd-core
- Fix IRQ trigger type; sec-irq, max77693, max14577
- Repair off-by-one; altera-sysmgr
- Add explicit 'select MFD_CORE' to MFD_SIMPLE_MFD_I2C
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Merge tag 'mfd-next-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Removed Drivers:
- Remove support for TI TPS80031/TPS80032 PMICs
New Device Support:
- Add support for Magnetic Reader to TI AM335x
- Add support for DA9063_EA to Dialog DA9063
- Add support for SC2730 PMIC to Spreadtrum SC27xx
- Add support for MacBookPro16,2 ICL-N UART Intel LPSS PCI
- Add support for lots of new PMICS in QCom SPMI PMIC
- Add support for ADC to Diolan DLN2
New Functionality:
- Add support for Power Off to Rockchip RK817
Fix-ups:
- Simplify Regmap passing to child devices in hi6421-spmi-pmic
- SPDX licensing updates in ti_am335x_tscadc
- Improve error handling in ti_am335x_tscadc
- Expedite clock search in ti_am335x_tscadc
- Generic simplifications in ti_am335x_tscadc
- Use generic macros/defines in ti_am335x_tscadc
- Remove unused code in ti_am335x_tscadc, cros_ec_dev
- Convert to GPIOD in wcd934x
- Add namespacing in ti_am335x_tscadc
- Restrict compilation to relevant arches in intel_pmt
- Provide better description/documentation in exynos_lpass
- Add SPI device ID table in altera-a10sr, motorola-cpcap,
sprd-sc27xx-spi
- Change IRQ handling in qcom-pm8xxx
- Split out I2C and SPI code in arizona
- Explicitly include used headers in altera-a10sr
- Convert sysfs show() function to in sysfs_emit
- Standardise *_exit() and *_remove() return values in mc13xxx,
stmpe, tps65912
- Trivial (style/spelling/whitespace) fixups in ti_am335x_tscadc,
qcom-spmi-pmic, max77686-private
- Device Tree fix-ups in ti,am3359-tscadc, samsung,s2mps11,
samsung,s2mpa01, samsung,s5m8767, brcm,misc, brcm,cru, syscon,
qcom,tcsr, xylon,logicvc, max77686, x-powers,ac100,
x-powers,axp152, x-powers,axp209-gpio, syscon, qcom,spmi-pmic
Bug Fixes:
- Balance refcounting (get/put) in ti_am335x_tscadc, mfd-core
- Fix IRQ trigger type in sec-irq, max77693, max14577
- Repair off-by-one in altera-sysmgr
- Add explicit 'select MFD_CORE' to MFD_SIMPLE_MFD_I2C"
* tag 'mfd-next-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (95 commits)
mfd: simple-mfd-i2c: Select MFD_CORE to fix build error
mfd: tps80031: Remove driver
mfd: max77686: Correct tab-based alignment of register addresses
mfd: wcd934x: Replace legacy gpio interface for gpiod
dt-bindings: mfd: qcom: pm8xxx: Add pm8018 compatible
mfd: dln2: Add cell for initializing DLN2 ADC
mfd: qcom-spmi-pmic: Add missing PMICs supported by socinfo
mfd: qcom-spmi-pmic: Document ten more PMICs in the binding
mfd: qcom-spmi-pmic: Sort compatibles in the driver
mfd: qcom-spmi-pmic: Sort the compatibles in the binding
mfd: janz-cmoio: Replace snprintf in show functions with sysfs_emit
mfd: altera-a10sr: Include linux/module.h
mfd: tps65912: Make tps65912_device_exit() return void
mfd: stmpe: Make stmpe_remove() return void
mfd: mc13xxx: Make mc13xxx_common_exit() return void
dt-bindings: mfd: syscon: Add samsung,exynosautov9-sysreg compatible
mfd: altera-sysmgr: Fix a mistake caused by resource_size conversion
dt-bindings: gpio: Convert X-Powers AXP209 GPIO binding to a schema
dt-bindings: mfd: syscon: Add rk3368 QoS register compatible
mfd: arizona: Split of_match table into I2C and SPI versions
...
Interrupt line can be configured on different hardware in different way,
even inverted. Therefore driver should not enforce specific trigger
type - edge falling - but instead rely on Devicetree to configure it.
The Maxim 77686 datasheet describes the interrupt line as active low
with a requirement of acknowledge from the CPU therefore the edge
falling is not correct.
The interrupt line is shared between PMIC and RTC driver, so using level
sensitive interrupt is here especially important to avoid races. With
an edge configuration in case if first PMIC signals interrupt followed
shortly after by the RTC, the interrupt might not be yet cleared/acked
thus the second one would not be noticed.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210602110445.33536-2-krzysztof.kozlowski@canonical.com
terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to use
cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung Exynos5433
CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The usual collection of clk driver updates and new driver additions.
In terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to
use cpufreq-dt driver and avoid overclocking of CPU and MCK0
domains while changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung
Exynos5433 CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
clk: use clk_core_get_rate_recalc() in clk_rate_get()
clk: at91: sama7g5: set low limit for mck0 at 32KHz
clk: at91: sama7g5: remove prescaler part of master clock
clk: at91: clk-master: add notifier for divider
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
clk: at91: clk-master: fix prescaler logic
clk: at91: clk-master: mask mckr against layout->mask
clk: at91: clk-master: check if div or pres is zero
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
clk: at91: pmc: add sama7g5 to the list of available pmcs
clk: at91: clk-master: improve readability by using local variables
clk: at91: clk-master: add register definition for sama7g5's master clock
clk: at91: sama7g5: add securam's peripheral clock
clk: at91: pmc: execute suspend/resume only for backup mode
clk: at91: re-factor clocks suspend/resume
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
...
The SiFive FU740 Power Reset Clock Interrupt Controller is a reset line
provider so add respective reset-cells property to fix:
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dt.yaml: clock-controller@10000000:
'#reset-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920144944.162431-1-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Silicon Labs is now part of Skyworks Inc. so update the URLs to the
datasheet and application note.
Signed-off-by: Jens Renner <renner@efe-gmbh.de>
Link: https://lore.kernel.org/r/20210913074823.115212-1-renner@efe-gmbh.de
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk-composite-determine-fix:
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: composite: Also consider .determine_rate for rate + mux composites
* clk-allwinner:
clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-ar100: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0-gates: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: sun6i-apb0: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function devm_platform_ioremap_resource()
clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_resource()
dt-bindings: clocks: Fix typo in the H6 compatible
clk: sunxi-ng: Use a separate lock for each CCU instance
clk: sunxi-ng: Prevent unbinding CCUs via sysfs
clk: sunxi-ng: Unregister clocks/resets when unbinding
clk: sunxi-ng: Add machine dependency to A83T CCU
clk: sunxi-ng: mux: Remove unused 'reg' field
* clk-amlogic:
clk: meson: meson8b: Make the video clock trees mutable
clk: meson: meson8b: Initialize the HDMI PLL registers
clk: meson: meson8b: Add the HDMI PLL M/N parameters
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel
clk: meson: meson8b: Export the video clocks
* clk-samsung:
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
clk: samsung: add support for CPU clocks
clk: samsung: Introduce Exynos850 clock driver
dt-bindings: clock: Document Exynos850 CMU bindings
dt-bindings: clock: Add bindings definitions for Exynos850 CMU
clk: samsung: clk-pll: Implement pll0831x PLL type
clk: samsung: clk-pll: Implement pll0822x PLL type
clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()
clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
* clk-imx: (21 commits)
clk: imx: Make CLK_IMX8ULP select MXC_CLK
clk: imx: imx6ul: Fix csi clk gate register
clk: imx: imx6ul: Move csi_sel mux to correct base register
clk: imx: Fix the build break when clk-imx8ulp build as module
clk: imx: Add the pcc reset controller support on imx8ulp
clk: imx: Add clock driver for imx8ulp
clk: imx: Update the pfdv2 for 8ulp specific support
clk: imx: disable the pfd when set pfdv2 clock rate
clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp
clk: imx: disable i.mx7ulp composite clock during initialization
clk: imx: Update the compsite driver to support imx8ulp
clk: imx: Update the pllv4 to support imx8ulp
dt-bindings: clock: Add imx8ulp clock support
clk: imx: Rework imx_clk_hw_pll14xx wrapper
clk: imx: Rework all imx_clk_hw_composite wrappers
clk: imx: Rework all clk_hw_register_divider wrappers
clk: imx: Rework all clk_hw_register_mux wrappers
clk: imx: Rework all clk_hw_register_gate2 wrappers
clk: imx: Rework all clk_hw_register_gate wrappers
clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones
...
* clk-ux500:
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
* clk-debugfs:
clk: use clk_core_get_rate_recalc() in clk_rate_get()
This rewrites the ux500/u8500 clock bindings in YAML schema and extends them
with the PRCC reset controller.
The bindings are a bit idiomatic but it just reflects their age, the ux500
platform was used as guinea pig for early device tree conversion of platforms
in 2015. The new subnode for the reset controller follows the pattern of the
old bindings and adds a node with reset-cells for this.
Cc: devicetree@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tagged to allow further bindings to rely on these.
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Merge tag 'tags/s2m_s5m_dtschema' into tb-mfd-from-regulator-5.16
regulator/clock: Convert the s2m and s5m DT bindings to schema
Tagged to allow further bindings to rely on these.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
On sm8250 videocc requires MMCX power domain to be powered up before
clock controller's registers become available. For now sm8250 was using
external regulator driven by the power domain to describe this
relationship. Switch into specifying power-domain and required opp-state
directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210829154757.784699-3-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
On sm8250 dispcc requires MMCX power domain to be powered up before
clock controller's registers become available. For now sm8250 was using
external regulator driven by the power domain to describe this
relationship. Switch into specifying power-domain and required opp-state
directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210829154757.784699-2-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The camera clock controller clock provider have a bunch of generic
properties that are needed in a device tree. Add the CAMCC clock IDs for
camera client to request for the clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633567425-11953-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Add the LPASS clock IDs for
LPASS PIL client to request for the clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633484416-27852-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add documentation for the MSM8994 GCC driver. While at it, retire its
compatible from the old, everyone-get-in-here file.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-1-konrad.dybcio@somainline.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add compatible for the RPM Clock Controller on the QCM2290 SoC.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210917030434.19859-3-shawn.guo@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It adds device tree bindings for QCM2290 Global Clock Controller.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210919023308.24498-2-shawn.guo@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Hi All,
Changes since v2
================
1. Add Stephen's and Rob's tags.
2. Correct inb-supply description in patch 10/10.
Changes since v2
================
1. Add Rob's tags.
2. Remove "regulator-name" from properties (all regulator dtschema).
3. Move "unevaluatedProperties" higher to make code easier to read (all regulator dtschema).
4. Add ref-type to op-mode property (patch 6: s5m8767 regulators).
Changes since v1
================
1. Drop DTS patches - applied.
2. Fully remove bindings/regulator/samsung,s5m8767.txt .
3. Minor subject reformatting and few typos in text.
Intro
=====
This patchset converts all devicetree bindings of Samsung S2M and S5M
PMIC devices from txt to dtschema.
It includes also two fixes because later conversion depends on it
(contextually).
Merging/dependencies
====================
1. Regulator related binding changes depend on first two commits (the
fixes), because of context.
2. The mfd bindings depend on clock and regulator bindings.
The fixes and bindings changes (patches 1-10) should go via the same
tree. For example regulator or mfd tree.
Another alternative is that regulator patches (1-2, 4-6) go via Mark who
later gives MFD a stable branch/tag to pull. Then the clock and MFD
bindings would go on top via MFD tree. Or any other setup you would like
to have.
Overview of devices
===================
Essentially all Samsung S2M and S5M PMICs are very similar devices. They
provide the same functionality: regulators, RTC, 2 or 3 clocks and main
power management (e.g. power cut to SoC).
The differences are mostly in registers layout and number of regulators.
The drivers are built around one common part, mfd/sec-core.c, and share
some drivers between devices:
1. MFD sec-core for all devices,
1. one clock driver for most of devices,
2. one RTC driver for all devices,
3. three regulator drivers.
The regulator drivers were implementing slightly different features,
therefore one regulator binding for all devices does not make much
sense. However the clock device binding can be shared.
The final dtschema bindings try to implement this - share only the clock
bindings.
Best regards,
Krzysztof
Krzysztof Kozlowski (10):
regulator: s5m8767: do not use reset value as DVS voltage if GPIO DVS
is disabled
regulator: dt-bindings: samsung,s5m8767: correct
s5m8767,pmic-buck-default-dvs-idx property
dt-bindings: clock: samsung,s2mps11: convert to dtschema
regulator: dt-bindings: samsung,s2m: convert to dtschema
regulator: dt-bindings: samsung,s2mpa01: convert to dtschema
regulator: dt-bindings: samsung,s5m8767: convert to dtschema
dt-bindings: mfd: samsung,s2mps11: convert to dtschema
dt-bindings: mfd: samsung,s2mpa01: convert to dtschema
dt-bindings: mfd: samsung,s5m8767: convert to dtschema
dt-bindings: mfd: samsung,s5m8767: document buck and LDO supplies
.../bindings/clock/samsung,s2mps11.txt | 49 ---
.../bindings/clock/samsung,s2mps11.yaml | 45 +++
.../bindings/mfd/samsung,s2mpa01.yaml | 91 ++++++
.../bindings/mfd/samsung,s2mps11.yaml | 267 +++++++++++++++
.../bindings/mfd/samsung,s5m8767.yaml | 307 ++++++++++++++++++
.../bindings/mfd/samsung,sec-core.txt | 86 -----
.../bindings/regulator/samsung,s2mpa01.txt | 79 -----
.../bindings/regulator/samsung,s2mpa01.yaml | 62 ++++
.../bindings/regulator/samsung,s2mps11.txt | 102 ------
.../bindings/regulator/samsung,s2mps11.yaml | 44 +++
.../bindings/regulator/samsung,s2mps13.yaml | 44 +++
.../bindings/regulator/samsung,s2mps14.yaml | 44 +++
.../bindings/regulator/samsung,s2mps15.yaml | 44 +++
.../bindings/regulator/samsung,s2mpu02.yaml | 44 +++
.../bindings/regulator/samsung,s5m8767.txt | 145 ---------
.../bindings/regulator/samsung,s5m8767.yaml | 74 +++++
MAINTAINERS | 9 +-
drivers/regulator/s5m8767.c | 21 +-
18 files changed, 1080 insertions(+), 477 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s2mps11.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/samsung,s2mpa01.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/samsung,s5m8767.yaml
delete mode 100644 Documentation/devicetree/bindings/mfd/samsung,sec-core.txt
delete mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mpa01.txt
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mpa01.yaml
delete mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mps11.txt
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mps11.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mps13.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mps15.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s2mpu02.yaml
delete mode 100644 Documentation/devicetree/bindings/regulator/samsung,s5m8767.txt
create mode 100644 Documentation/devicetree/bindings/regulator/samsung,s5m8767.yaml
--
2.30.2
Convert the clock provider of Samsung S2MPS11 family of PMICs to DT
schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Message-Id: <20211008113723.134648-4-krzysztof.kozlowski@canonical.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the clock dt-binding file for i.MX8ULP.
For pcc node, it will also be used as a reset controller,
so add the '#reset-cells' property description and add the
pcc reset IDs.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-2-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Convert the binding documentatoin for fixed-mmio-clock to YAML.
Signed-off-by: Marek Behún <kabel@kernel.org>
Link: https://lore.kernel.org/r/20210903152615.31453-1-kabel@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'reg' is the standard property for defining register banks/addresses. Add
it to use for the VCO register address and deprecate 'vco-offset'. This
will also allow for using standard node names with unit-addresses.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210913192816.1225025-5-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some of these clocks are not referenced by the driver at all whereas
aud_ref_clk and core_bi_pll_test_se are but were missing from the
bindings. These clocks are optional (and not currently provided
anywhere) while "xo" and "sleep_clk" are mandatory.
Note that none of these clocks were used beforehand as the driver
referenced them by their global name.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-7-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Even though both the driver and the device trees all use the
allwinner,sun50i-h6-de3-clk, we documented the compatible as
allwinner,sun50i-h6-de2-clk in the binding. Let's fix this.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20210901091852.479202-10-maxime@cerno.tech
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
* clk-nvidia:
clk: tegra: fix old-style declaration
clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
soc/tegra: fuse: Add runtime PM support
soc/tegra: fuse: Clear fuse->clk on driver probe failure
soc/tegra: pmc: Prevent racing with cpuilde driver
soc/tegra: bpmp: Remove unused including <linux/version.h>
* clk-rockchip:
clk: rockchip: make rk3308 ddrphy4x clock critical
clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
clk: rockchip: Add support for hclk_sfc on rk3036
clk: rockchip: rk3036: fix up the sclk_sfc parent error
clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036
* clk-at91:
clk: at91: clk-generated: Limit the requested rate to our range
* clk-vc5:
clk: vc5: Add properties for configuring SD/OE behavior
clk: vc5: Use dev_err_probe
dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
The proper header is exynos4.h:
samsung,exynos4412-isp-clock.example.dts:19:18: fatal error: dt-bindings/clock/exynos4412.h: No such file or directory
Fixes: 7ac6157809 ("dt-bindings: clock: samsung: convert Exynos4 to dtschema")
Reported-by: Stephen Boyd <sboyd@kernel.org>
Reported-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210831130643.83249-1-krzysztof.kozlowski@canonical.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert Samsung S5Pv210 Audio SubSystem clock controller bindings to DT
schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134251.220098-2-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134251.220098-1-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document the bindings for Samsung Exynos external to SoC
(oscclk/XXTI/XusbXTI) clock provided on boards. The bindings are
already implemented in most of the Exynos clock drivers and DTS files.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210825134056.219884-3-krzysztof.kozlowski@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert Samsung Exynos5250 clock controller bindings to DT schema format
using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134056.219884-2-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These properties allow configuring the SD/OE pin as described in the
datasheet.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210809223813.3766204-1-sean.anderson@seco.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
armpll clocks (available on Cygnus and Northstar Plus) are simple clocks
with no cells. Adjust binding props #clock-cells and clock-output-names
to handle them.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20210819052918.6753-1-zajec5@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add bindings and update documentation for clock rpmh driver on SM6350.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203243.230157-2-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for global clock controller on SM6115 and
SM4250 SoCs (pin and software compatible).
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210805161107.1194521-2-iskren.chernev@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The GPU clock controller found in SC8180x is a variant of the same block
found in SM8150, but with one additional clock frequency for the
gmu_clk_src clock.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721225329.3035779-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the dt-binding for the RPM Clock Controller on the SM4250/6115 SoCs.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210627185927.695411-3-iskren.chernev@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the rockchip,rk3399-cru binding to DT schema format.
Tested with
ARCH=arm64 make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210610175613.167601-1-nfraprado@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add device tree bindings for video clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-7-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-5-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for display clock controller subsystem for
Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-3-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Another round of removing redundant minItems/maxItems from new schema in
the recent merge window.
If a property has an 'items' list, then a 'minItems' or 'maxItems' with the
same size as the list is redundant and can be dropped. Note that is DT
schema specific behavior and not standard json-schema behavior. The tooling
will fixup the final schema adding any unspecified minItems/maxItems.
This condition is partially checked with the meta-schema already, but
only if both 'minItems' and 'maxItems' are equal to the 'items' length.
An improved meta-schema is pending.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Will Deacon <will@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Kamal Dasu <kdasu.kdev@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-clk@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-rtc@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210713193453.690290-1-robh@kernel.org
Like always, the DT branch is sizable. There are numerous additions and
fixes to existing platforms, but also a handful of new ones introduced.
Less than some other releases, but there's been significant work on
cleanups, refactorings and device enabling on existing platforms.
A non-exhaustive list of new material:
- Refactoring of BCM2711 dtsi structure to add support for the Raspberry Pi 400
- Rockchip: RK3568 SoC and EVB, video codecs for rk3036/3066/3188/322x
- Qualcomm: SA8155p Automotive platform (SM8150 derivative),
SM8150/8250 enhancements and support for Sony Xperia 1/1II and 5/5II
- TI K3: PCI/USB3 support on AM64-sk boards, R5 remoteproc definitions
- TI OMAP: Various cleanups
- Tegra: Audio support for Jetson Xavier NX, SMMU support on Tegra194
- Qualcomm: lots of additions for peripherals across several SoCs, and
new support for Microsoft Surface Duo (SM8150-based), Huawei Ascend G7.
- i.MX: Numerous additions of features across SoCs and boards.
- Allwinner: More device bindings for V3s, Forlinx OKA40i-C and NanoPi
R1S H5 boards
- MediaTek: More device bindings for mt8167, new Chromebook system
variants for mt8183
- Renesas: RZ/G2L SoC and EVK added
- Amlogic: BananaPi BPI-M5 board added
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Merge tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Olof Johansson:
"Like always, the DT branch is sizable. There are numerous additions
and fixes to existing platforms, but also a handful of new ones
introduced. Less than some other releases, but there's been
significant work on cleanups, refactorings and device enabling on
existing platforms.
A non-exhaustive list of new material:
- Refactoring of BCM2711 dtsi structure to add support for the
Raspberry Pi 400
- Rockchip: RK3568 SoC and EVB, video codecs for
rk3036/3066/3188/322x
- Qualcomm: SA8155p Automotive platform (SM8150 derivative),
SM8150/8250 enhancements and support for Sony Xperia 1/1II and
5/5II
- TI K3: PCI/USB3 support on AM64-sk boards, R5 remoteproc
definitions
- TI OMAP: Various cleanups
- Tegra: Audio support for Jetson Xavier NX, SMMU support on Tegra194
- Qualcomm: lots of additions for peripherals across several SoCs,
and new support for Microsoft Surface Duo (SM8150-based), Huawei
Ascend G7.
- i.MX: Numerous additions of features across SoCs and boards.
- Allwinner: More device bindings for V3s, Forlinx OKA40i-C and
NanoPi R1S H5 boards
- MediaTek: More device bindings for mt8167, new Chromebook system
variants for mt8183
- Renesas: RZ/G2L SoC and EVK added
- Amlogic: BananaPi BPI-M5 board added"
* tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (511 commits)
arm64: dts: rockchip: add basic dts for RK3568 EVB
arm64: dts: rockchip: add core dtsi for RK3568 SoC
arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs
ARM: dts: rockchip: add vpu and vdec node for RK322x
ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188
ARM: dts: rockchip: add vpu node for RK3036
arm64: dts: ipq8074: Add QUP6 I2C node
arm64: dts: rockchip: Re-add regulator-always-on for vcc_sdio for rk3399-roc-pc
arm64: dts: rockchip: Re-add regulator-boot-on, regulator-always-on for vdd_gpu on rk3399-roc-pc
arm64: dts: rockchip: add ir-receiver for rk3399-roc-pc
arm64: dts: rockchip: Add USB-C port details for rk3399 Firefly
arm64: dts: rockchip: Sort rk3399 firefly pinmux entries
arm64: dts: rockchip: add infrared receiver node to RK3399 Firefly
arm64: dts: rockchip: add SPDIF node for rk3399-firefly
arm64: dts: rockchip: Add Rotation Property for OGA Panel
arm64: dts: qcom: sc7180: bus votes for eMMC and SD card
arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen
arm64: dts: qcom: sm8250-edo: Enable GPI DMA
arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI
arm64: dts: qcom: sm8250-edo: Enable PCIe
...
- Refine reserved memory nomap handling
- Merge some PCI and non-PCI address handling implementations
- Simplify of_address.h header ifdefs
- Improve printk handling of some 64-bit types
- Convert Arm ccree, Zynq FPGA, ZynqMP RTC, Arm VIC, adi,adv7511, TI
AM56 PCI, Aspeed I2C, arm,sbsa-gwdt, MTD physmap, virtio-mmio, Arm
SCMI, Arm/Amlogic SCPI, TI OMAP mailbox, NXP pcf8563/pcf85263/pcf85363,
Mediatek RNG, Arm SCU, Arm TWD timer, Broadcom iProc PWM, Renesas TPU,
Tegra20 EMC, MDIO GPIO, renesas,r9a06g032-sysctrl, renesas,emev2-smu,
sysc-rmobile, linaro,optee-tz, and TI SCI bindings to DT schema
- Convert mux and mux controller bindings to schema. This includes MDIO
IIO, and I2C muxes.
- Add Arm PL031 RTC binding schema
- Add vendor prefixes for StarFive Technology Co. Ltd. and Insignal Ltd
- Fix some stale doc references
- Remove stale property-units.txt. Superseded by schema in dt-schema
repo.
- Fixes for 'unevaluatedProperties' handling (enabled with experimental
json-schema support)
- Drop redundant usage of minItems and maxItems across the tree
- Update some examples to use bindings with a schema
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Merge tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Refine reserved memory nomap handling
- Merge some PCI and non-PCI address handling implementations
- Simplify of_address.h header ifdefs
- Improve printk handling of some 64-bit types
- Convert adi,adv7511, Arm ccree, Arm SCMI, Arm SCU, Arm TWD timer, Arm
VIC, arm,sbsa-gwdt, Arm/Amlogic SCPI, Aspeed I2C, Broadcom iProc PWM,
linaro,optee-tz, MDIO GPIO, Mediatek RNG, MTD physmap, NXP
pcf8563/pcf85263/pcf85363, Renesas TPU, renesas,emev2-smu,
renesas,r9a06g032-sysctrl, sysc-rmobile, Tegra20 EMC, TI AM56 PCI, TI
OMAP mailbox, TI SCI bindings, virtio-mmio, Zynq FPGA, and ZynqMP RTC
to DT schema
- Convert mux and mux controller bindings to schema. This includes MDIO
IIO, and I2C muxes.
- Add Arm PL031 RTC binding schema
- Add vendor prefixes for StarFive Technology Co. Ltd. and Insignal Ltd
- Fix some stale doc references
- Remove stale property-units.txt. Superseded by schema in dt-schema
repo.
- Fixes for 'unevaluatedProperties' handling (enabled with experimental
json-schema support)
- Drop redundant usage of minItems and maxItems across the tree
- Update some examples to use bindings with a schema
* tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (83 commits)
dt-bindings: Fix 'unevaluatedProperties' errors in DT graph users
dt-bindings: display: renesas,du: Fix 'ports' reference
dt-bindings: media: adv7180: Add missing video-interfaces.yaml reference
dt-bindings: crypto: ccree: Convert to json-schema
dt-bindings: fpga: zynq: convert bindings to YAML
dt-bindings: rtc: zynqmp: convert bindings to YAML
dt-bindings: interrupt-controller: Convert ARM VIC to json-schema
of: of_reserved_mem: mark nomap memory instead of removing
of: of_reserved_mem: only call memblock_free for normal reserved memory
dt-bindings: Drop redundant minItems/maxItems
dt-bindings: spmi: Correct 'reg' schema
of: reserved-memory: Add stub for RESERVEDMEM_OF_DECLARE()
dt-bindings: clk: vc5: Fix example
dt-bindings: timer: renesas,tmu: add r8a779a0 TMU support
dt-bindings: drm: bridge: adi,adv7511.txt: convert to yaml
dt-bindings: PCI: ti,am65: Convert PCIe host/endpoint mode dt-bindings to YAML
of: Remove superfluous casts when printing u64 values
of: Fix truncation of memory sizes on 32-bit platforms
dt-bindings: rtc: nxp,pcf8563: Absorb pcf85263/pcf85363 bindings
dt-bindings: pwm: Use examples with documented/matching schema
...
- Ingenic fixes/improvments
- other fixes and cleanups
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Merge tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- add support for OpeneEmbed SOM9331 board
- Ingenic fixes/improvments
- other fixes and cleanups
* tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (39 commits)
MIPS: Fix PKMAP with 32-bit MIPS huge page support
MIPS: CI20: Add second percpu timer for SMP.
MIPS: CI20: Reduce clocksource to 750 kHz.
MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
dt-bindings: clock: Add documentation for MAC PHY control bindings.
MIPS: X1830: Respect cell count of common properties.
MIPS: set mips32r5 for virt extensions
MIPS: loongsoon64: Reserve memory below starting pfn to prevent Oops
MIPS: MT extensions are not available on MIPS32r1
mips/kvm: Use BUG_ON instead of if condition followed by BUG
MIPS: OCTEON: octeon-usb: Use devm_platform_get_and_ioremap_resource()
MIPS: add PMD table accounting into MIPS'pmd_alloc_one
MIPS: Loongson64: fix spelling of SPDX tag
MIPS: ingenic: rs90: Add dedicated VRAM memory region
MIPS: ingenic: gcw0: Set codec to cap-less mode for FM radio
MIPS: ingenic: jz4780: Fix I2C nodes to match DT doc
MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
MIPS: Kconfig: ingenic: Ensure MACH_INGENIC_GENERIC selects all SoCs
MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B)
MIPS: boot: Support specifying UART port on Ingenic SoCs
...
that's just a bunch of data so the diffstat reflects that. Looking beyond that
there's just a bunch of updates all around in various clk drivers. Renesas and
NXP (for i.MX) are two SoC vendors that have a lot of patches in here. Overall
the driver changes look to be mostly enabling more clks and non-critical fixes
that we could hold until the next merge window.
I'm especially excited about the series from Arnd that graduates clkdev to be
the only implementation of clk_get() and clk_put(). That's a good step in the
right direction to migreate eveerything over to the common clk framework. Now
we don't have to worry about clkdev specific details, they're just part of the
clk API now.
Core:
- clkdev is now the only option, i.e. clk_get()/clk_put() is implemented in
only one place in the kernel instead of in drivers/clk/clkdev.c and in
architectures that want their own implementation
New Drivers:
- Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
Jitter Cleaner With Dual Loop PLLs
- Qualcomm MDM9607 GCC
- Qualcomm SC8180X display clks
- Qualcomm SM6125 GCC
- Qualcomm SM8250 CAMCC (camera)
- Renesas RZ/G2L SoC
- Hisilicon hi3559A SoC
Updates:
- Stop using clock-output-names in ST clk drivers (yay!)
- Support secure mode of STM32MP1 SoCs
- Improve clock support for Actions S500 SoC
- duty cycle setting support on qcom clks
- Add TI am33xx spread spectrum clock support
- Use determine_rate() for the Amlogic pll ops instead of round_rate()
- Restrict Amlogic gp0/1 and audio plls range on g12a/sm1
- Improve Amlogic axg-audio controller error on deferral
- Add NNA clocks on Amlogic g12a
- Reduce memory footprint of Rockchip PLL rate tables
- A fix for the newly added Rockchip rk3568 clk driver
- Exported clock for the newly added Rockchip video decoder
- Remove audio ipg clock from i.MX8MP
- Remove deprecated legacy clock binding for i.MX SCU clock driver
- Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
- Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio,
parallel interface)
- Add dedicated clock ops for i.MX paralel interface
- Different fixes for clocks controlled by ATF on i.MX SoCs
- Add A53/A72 frequency scaling support i.MX clk-scu driver
- Add special case for DCSS clock on suspend for i.MX clk-scu driver
- Add parent save/restore on suspend/resume to i.MX clk-scu driver
- Skip runtime PM enablement for CPU clocks in i.MX clk-scu driver
- Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
bindings
- Tegra clk driver no longer deasserts resets on clk_enable as it
gets in the way of certain power-up sequences
- Fix compile testing for Tegra clk driver
- One patch to fix a divider on the Allwinner v3s Audio PLL
- Add support for CPU core clock boost modes on Renesas R-Car Gen3
- Add ISPCS (Image Signal Processor) clocks on Renesas R-Car V3U
- Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate()
and improve support for multiple parents
- Switch Renesas RZ/N1 divider clocks to .determine_rate()
- Add ZA2 (Audio Clock Generator) clock on Renesas R-Car D3
- Convert ar7 to common clk framework
- Convert ralink to common clk framework
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round has a diffstat dominated by Qualcomm clk drivers. Honestly
though that's just a bunch of data so the diffstat reflects that.
Looking beyond that there's just a bunch of updates all around in
various clk drivers. Renesas and NXP (for i.MX) are two SoC vendors
that have a lot of patches in here.
Overall the driver changes look to be mostly enabling more clks and
non-critical fixes that we could hold until the next merge window.
I'm especially excited about the series from Arnd that graduates
clkdev to be the only implementation of clk_get() and clk_put().
That's a good step in the right direction to migreate eveerything over
to the common clk framework. Now we don't have to worry about clkdev
specific details, they're just part of the clk API now.
Core:
- clkdev is now the only option, i.e. clk_get()/clk_put() is
implemented in only one place in the kernel instead of in
drivers/clk/clkdev.c and in architectures that want their own
implementation
New Drivers:
- Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner With Dual Loop PLLs
- Qualcomm MDM9607 GCC
- Qualcomm SC8180X display clks
- Qualcomm SM6125 GCC
- Qualcomm SM8250 CAMCC (camera)
- Renesas RZ/G2L SoC
- Hisilicon hi3559A SoC
Updates:
- Stop using clock-output-names in ST clk drivers (yay!)
- Support secure mode of STM32MP1 SoCs
- Improve clock support for Actions S500 SoC
- duty cycle setting support on qcom clks
- Add TI am33xx spread spectrum clock support
- Use determine_rate() for the Amlogic pll ops instead of
round_rate()
- Restrict Amlogic gp0/1 and audio plls range on g12a/sm1
- Improve Amlogic axg-audio controller error on deferral
- Add NNA clocks on Amlogic g12a
- Reduce memory footprint of Rockchip PLL rate tables
- A fix for the newly added Rockchip rk3568 clk driver
- Exported clock for the newly added Rockchip video decoder
- Remove audio ipg clock from i.MX8MP
- Remove deprecated legacy clock binding for i.MX SCU clock driver
- Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
- Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif,
audio, parallel interface)
- Add dedicated clock ops for i.MX paralel interface
- Different fixes for clocks controlled by ATF on i.MX SoCs
- Add A53/A72 frequency scaling support i.MX clk-scu driver
- Add special case for DCSS clock on suspend for i.MX clk-scu driver
- Add parent save/restore on suspend/resume to i.MX clk-scu driver
- Skip runtime PM enablement for CPU clocks in i.MX clk-scu driver
- Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
bindings
- Tegra clk driver no longer deasserts resets on clk_enable as it
gets in the way of certain power-up sequences
- Fix compile testing for Tegra clk driver
- One patch to fix a divider on the Allwinner v3s Audio PLL
- Add support for CPU core clock boost modes on Renesas R-Car Gen3
- Add ISPCS (Image Signal Processor) clocks on Renesas R-Car V3U
- Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate() and
improve support for multiple parents
- Switch Renesas RZ/N1 divider clocks to .determine_rate()
- Add ZA2 (Audio Clock Generator) clock on Renesas R-Car D3
- Convert ar7 to common clk framework
- Convert ralink to common clk framework"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (161 commits)
clk: zynqmp: Handle divider specific read only flag
clk: zynqmp: Use firmware specific mux clock flags
clk: zynqmp: Use firmware specific divider clock flags
clk: zynqmp: Use firmware specific common clock flags
clk: lmk04832: Use of match table
clk: lmk04832: Depend on SPI
clk: stm32mp1: new compatible for secure RCC support
dt-bindings: clock: stm32mp1 new compatible for secure rcc
dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
reset: stm32mp1: remove stm32mp1 reset
clk: hisilicon: Add clock driver for hi3559A SoC
dt-bindings: Document the hi3559a clock bindings
clk: si5341: Add sysfs properties to allow checking/resetting device faults
clk: si5341: Add silabs,iovdd-33 property
clk: si5341: Add silabs,xaxb-ext-clk property
clk: si5341: Allow different output VDD_SEL values
clk: si5341: Update initialization magic
clk: si5341: Check for input clock presence and PLL lock on startup
...
Update the CGU binding documentation, add mac-phy-ctrl as a
pattern property.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
- Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
Jitter Cleaner With Dual Loop PLLs
- Support secure mode of STM32MP1 SoCs
- Improve clock support for Actions S500 SoC
* clk-lmk04832:
clk: lmk04832: Use of match table
clk: lmk04832: Depend on SPI
clk: lmk04832: add support for digital delay
clk: add support for the lmk04832
dt-bindings: clock: add ti,lmk04832 bindings
* clk-stm:
clk: stm32mp1: new compatible for secure RCC support
dt-bindings: clock: stm32mp1 new compatible for secure rcc
dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
reset: stm32mp1: remove stm32mp1 reset
clk: stm32mp1: move RCC reset controller into RCC clock driver
clk: stm32mp1: convert to module driver
clk: stm32mp1: remove intermediate pll clocks
clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
* clk-rohm:
clk: bd718xx: Drop BD70528 support
* clk-actions:
clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
clk: actions: Fix SD clocks factor table on Owl S500 SoC
clk: actions: Fix UART clock dividers on Owl S500 SoC
* clk-ingenic:
clk: ingenic: Add support for the JZ4760
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
clk: ingenic: Remove pll_info.no_bypass_bit
clk: ingenic: Read bypass register only when there is one
clk: Support bypassing dividers
dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles
Introduce new compatible string "st,stm32mp1-rcc-secure" for
stm32mp1 clock driver when the device is configured with RCC
security support hardened.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210617051814.12018-11-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add new silabs,xaxb-ext-clk and silabs,iovdd-33 properties.
Changed vdd-supply on top-level node to optional since it is not actually
used by the driver.
Removed vdd-supply from output sub-nodes, as it was not supported by the
driver and it is not easily possible to support this in that location with
the kernel regulator infrastructure. Changed to have vddoX-supply
attributes for each output on the top-level device node.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Link: https://lore.kernel.org/r/20210325192643.2190069-2-robert.hancock@calian.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
New compatible are added, supporting various kind of clkgen-fsyn
used for STiH407, STiH410 and STiH418
Signed-off-by: Alain Volmat <avolmat@me.com>
Link: https://lore.kernel.org/r/20210331201632.24530-8-avolmat@me.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
New compatible are added, supporting various kind of clkgen-pll
used for STiH407, STiH410 and STiH418
Signed-off-by: Alain Volmat <avolmat@me.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210331201632.24530-6-avolmat@me.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
New compatible are added, supporting various kind of flexgen in
STiH407, STiH410 and STiH418
Signed-off-by: Alain Volmat <avolmat@me.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210331201632.24530-4-avolmat@me.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add ingenic,jz4760-cgu and ingenic,jz4760b-cgu compatible strings for
the JZ4760 and JZ4760B SoCs respectively.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210530164923.18134-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document devicetree bindings for Texas Instruments' LMK04832.
The LMK04208 is a high performance clock conditioner with superior clock
jitter cleaning, generation, and distribution with JEDEC JESD204B
support.
Signed-off-by: Liam Beguin <lvb@xiphos.com>
Link: https://lore.kernel.org/r/20210423004057.283926-4-liambeguin@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SM8250 SoC.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210609022051.2171-3-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add compatible device strings and the include files for the MSM8226 GCC.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210418122909.71434-2-bartosz.dudziak@snejp.pl
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
If a property has an 'items' list, then a 'minItems' or 'maxItems' with the
same size as the list is redundant and can be dropped. Note that is DT
schema specific behavior and not standard json-schema behavior. The tooling
will fixup the final schema adding any unspecified minItems/maxItems.
This condition is partially checked with the meta-schema already, but
only if both 'minItems' and 'maxItems' are equal to the 'items' length.
An improved meta-schema is pending.
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Kamal Dasu <kdasu.kdev@gmail.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Vivien Didelot <vivien.didelot@gmail.com>
Cc: Vladimir Oltean <olteanv@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # for MMC
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-By: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20210615191543.1043414-1-robh@kernel.org
The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.
Fixes: 45c940184b ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com
Signed-off-by: Rob Herring <robh@kernel.org>
This contains a conversion of the Tegra clock and reset controller
device tree bindings to the new json-schema format and adds the core
power domain to the PMC device tree bindings.
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Merge tag 'tegra-for-5.14-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.14-rc1
This contains a conversion of the Tegra clock and reset controller
device tree bindings to the new json-schema format and adds the core
power domain to the PMC device tree bindings.
* tag 'tegra-for-5.14-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: soc: tegra-pmc: Document core power domain
dt-bindings: clock: tegra: Convert to schema
Link: https://lore.kernel.org/r/20210611164437.3568059-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
for 5.14, please pull the following:
- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
files to resolve a number of DT binding check warnings pertaining to
NAND, pinmux, clocks, SPI
- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
causing regressions on the Raspberry Pi 4B
- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
off that variant properly
- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
re-organization work and finally adding the DTS file proper
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Merge tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.14, please pull the following:
- Rafal updates the BCM5301x, HR2, BCM63xx, BCM5301x, NSP and Cygnus DTS
files to resolve a number of DT binding check warnings pertaining to
NAND, pinmux, clocks, SPI
- Stefan provides a fix for an increase in the DWC2 controller's RX FIFO
causing regressions on the Raspberry Pi 4B
- Mateusz adds a BCM2711 specific VEC compatible string to allow keying
off that variant properly
- Stefan adds support for the Raspberry Pi 400 by doing some DTS/DTSI
re-organization work and finally adding the DTS file proper
* tag 'arm-soc/for-5.14/devicetree' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Add reference to RPi 400
ARM: dts: Add Raspberry Pi 400 support
ARM: dts: bcm283x: Fix up GPIO LED node names
dt-bindings: arm: bcm2835: Add Raspberry Pi 400 to DT schema
ARM: dts: Move BCM2711 RPi specific into separate dtsi
ARM: dts: bcm283x: Fix up MMC node names
ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible
Revert "ARM: dts: bcm283x: increase dwc2's RX FIFO size"
ARM: dts: BCM5301X: Fixup SPI binding
dt-bindings: clock: brcm, iproc-clocks: convert to the json-schema
ARM: dts: BCM5301X: Fix pinmux subnodes names
ARM: dts: Hurricane 2: Fix NAND nodes names
ARM: dts: BCM63xx: Fix NAND nodes names
ARM: NSP: dts: fix NAND nodes names
ARM: Cygnus: dts: fix NAND nodes names
ARM: brcmstb: dts: fix NAND nodes names
ARM: dts: BCM5301X: Fix NAND nodes names
Link: https://lore.kernel.org/r/20210610194836.309869-1-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210609153230.6967-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
DT bindings for enabling and adjusting spread spectrum clocking have
been added.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210606202253.31649-3-dariobin@libero.it
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the dt-binding for the RPM Clock Controller on the MSM8226 SoC.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210502122027.9351-4-bartosz.dudziak@snejp.pl
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The display clock controller in SC8180x is reused from SM8150, so add
the necessary compatible and wire up the driver to enable this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Users of common properties shouldn't have a type definition as the
common schemas already have one. A few new ones slipped in and
*-names was missed in the last clean-up pass. Drop all the unnecessary
type references in the tree.
A meta-schema update to catch these is pending.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Olivier Moysan <olivier.moysan@foss.st.com>
Cc: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Baolin Wang <baolin.wang7@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Fabrice Gasnier <fabrice.gasnier@st.com>
Cc: Odelu Kukatla <okukatla@codeaurora.org>
Cc: Alex Elder <elder@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: linux-clk@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Cc: linux-iio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-input@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: netdev@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20210510204524.617390-1-robh@kernel.org
Convert the Renesas EMMA Mobile EV2 System Management Unit (SMU) Device
Tree binding documentation to json-schema.
Drop the separate provider examples, as they mostly duplicate the global
example. Drop the consumer example, as it doesn't belong here.
Update the global example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/526e1a412145a0fcc5a43dcf6de5c580301017cb.1620119350.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the ti,sci-clk to json schema for better checks and documentation.
Differences being:
- Drop consumer example as they are documented in the corresponding
bindings themselves.
- Standardize the node name as clock-controller rather than clocks as
it is more appropriate.
- Drop phandle description for clock-cells as it is redundant.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210426155457.21221-3-nm@ti.com
Signed-off-by: Rob Herring <robh@kernel.org>
usual suspects are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and
Rockchip, but it feels pretty light on commits. There's only one real commit to
the framework core and that's to consolidate code. Otherwise the diffstat is
dominated by many Qualcomm clk driver patches that modernize the driver for the
proper way of speciying clk parents. That's shifting data around, which could
subtly break things so I'll be on the lookout for fixes.
New Drivers:
- Proper clk driver for Mediatek MT7621 SoCs
- Support for the clock controller on the new Rockchip rk3568
Updates:
- Simplify Zynq Kconfig dependencies
- Use clk_hw pointers in socfpga driver
- Cleanup parent data in qcom clk drivers
- Some cleanups for rk3399 modularization
- Fix reparenting of i.MX UART clocks by initializing only the ones
associated to stdout
- Correct the PCIE clocks for i.MX8MP and i.MX8MQ
- Make i.MX LPCG and SCU clocks return on registering failure
- Kernel doc fixes
- Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N
- Add timer (TMU) clocks on Renesas R-Car H3 ES1.0
- Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on Renesas R-Car V3U
- Sigma-delta modulation on Allwinner V3s audio PLL
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Here's a collection of largely clk driver updates. The usual suspects
are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and Rockchip,
but it feels pretty light on commits.
There's only one real commit to the framework core and that's to
consolidate code. Otherwise the diffstat is dominated by many Qualcomm
clk driver patches that modernize the driver for the proper way of
speciying clk parents. That's shifting data around, which could subtly
break things so I'll be on the lookout for fixes.
New Drivers:
- Proper clk driver for Mediatek MT7621 SoCs
- Support for the clock controller on the new Rockchip rk3568
Updates:
- Simplify Zynq Kconfig dependencies
- Use clk_hw pointers in socfpga driver
- Cleanup parent data in qcom clk drivers
- Some cleanups for rk3399 modularization
- Fix reparenting of i.MX UART clocks by initializing only the ones
associated to stdout
- Correct the PCIE clocks for i.MX8MP and i.MX8MQ
- Make i.MX LPCG and SCU clocks return on registering failure
- Kernel doc fixes
- Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N
- Add timer (TMU) clocks on Renesas R-Car H3 ES1.0
- Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on
Renesas R-Car V3U
- Sigma-delta modulation on Allwinner V3s audio PLL"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (82 commits)
MAINTAINERS: add MT7621 CLOCK maintainer
staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
staging: mt7621-dts: make use of new 'mt7621-clk'
clk: ralink: add clock driver for mt7621 SoC
clk: uniphier: Fix potential infinite loop
clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
clk: qcom: gcc-sdm845: get rid of the test clock
clk: qcom: convert SDM845 Global Clock Controller to parent_data
dt-bindings: clock: separate SDM845 GCC clock bindings
clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
dt: bindings: add mt7621-sysc device tree binding documentation
dt-bindings: clock: add dt binding header for mt7621 clocks
clk: samsung: Remove redundant dev_err calls
clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
clk: zynqmp: Drop dependency on ARCH_ZYNQMP
clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
...
- Refactoring powerpc and arm64 kexec DT handling to common code. This
enables IMA on arm64.
- Add kbuild support for applying DT overlays at build time. The first
user are the DT unittests.
- Fix kerneldoc formatting and W=1 warnings in drivers/of/
- Fix handling 64-bit flag on PCI resources
- Bump dtschema version required to v2021.2.1
- Enable undocumented compatible checks for dtbs_check. This allows
tracking of missing binding schemas.
- DT docs improvements. Regroup the DT docs and add the example schema
and DT kernel ABI docs to the doc build.
- Convert Broadcom Bluetooth and video-mux bindings to schema
- Add QCom sm8250 Venus video codec binding schema
- Add vendor prefixes for AESOP, YIC System Co., Ltd, and Siliconfile
Technologies Inc.
- Cleanup of DT schema type references on common properties and
standard unit properties
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Merge tag 'devicetree-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Refactor powerpc and arm64 kexec DT handling to common code. This
enables IMA on arm64.
- Add kbuild support for applying DT overlays at build time. The first
user are the DT unittests.
- Fix kerneldoc formatting and W=1 warnings in drivers/of/
- Fix handling 64-bit flag on PCI resources
- Bump dtschema version required to v2021.2.1
- Enable undocumented compatible checks for dtbs_check. This allows
tracking of missing binding schemas.
- DT docs improvements. Regroup the DT docs and add the example schema
and DT kernel ABI docs to the doc build.
- Convert Broadcom Bluetooth and video-mux bindings to schema
- Add QCom sm8250 Venus video codec binding schema
- Add vendor prefixes for AESOP, YIC System Co., Ltd, and Siliconfile
Technologies Inc.
- Cleanup of DT schema type references on common properties and
standard unit properties
* tag 'devicetree-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits)
powerpc: If kexec_build_elf_info() fails return immediately from elf64_load()
powerpc: Free fdt on error in elf64_load()
of: overlay: Fix kerneldoc warning in of_overlay_remove()
of: linux/of.h: fix kernel-doc warnings
of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses
dt-bindings: bcm4329-fmac: add optional brcm,ccode-map
docs: dt: update writing-schema.rst references
dt-bindings: media: venus: Add sm8250 dt schema
of: base: Fix spelling issue with function param 'prop'
docs: dt: Add DT API documentation
of: Add missing 'Return' section in kerneldoc comments
of: Fix kerneldoc output formatting
docs: dt: Group DT docs into relevant sub-sections
docs: dt: Make 'Devicetree' wording more consistent
docs: dt: writing-schema: Include the example schema in the doc build
docs: dt: writing-schema: Remove spurious indentation
dt-bindings: Fix reference in submitting-patches.rst to the DT ABI doc
dt-bindings: ddr: Add optional manufacturer and revision ID to LPDDR3
dt-bindings: media: video-interfaces: Drop the example
devicetree: bindings: clock: Minor typo fix in the file armada3700-tbg-clock.txt
...
- Simplify Zynq Kconfig dependencies
* clk-imx:
clk: imx: Reference preceded by free
clk: imx8mq: Correct the pcie1 sels
clk: imx8mp: Remove the none exist pcie clocks
clk: imx: Fix reparenting of UARTs not associated with stdout
* clk-samsung:
clk: samsung: Remove redundant dev_err calls
clk: exynos7: Mark aclk_fsys1_200 as critical
* clk-zynq:
clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
clk: zynqmp: Drop dependency on ARCH_ZYNQMP
clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
* clk-rockchip:
clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller
clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends
clk: rockchip: add clock controller for rk3568
clk: rockchip: support more core div setting
dt-binding: clock: Document rockchip, rk3568-cru bindings
clk: rockchip: add dt-binding header for rk3568
* clk-uniphier:
clk: uniphier: Fix potential infinite loop
Separate qcom,gcc-sdm845 clock bindings from the clock-less
qcom,gcc.yaml, so that we can add required clocks and clock-names
properties.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210409183004.1617777-2-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Adding checks for undocumented compatible strings reveals a bunch of
warnings in the DT binding examples. Fix the cases which are typos, just
a mismatch between the schema and the example, or aren't documented at all.
In a couple of cases, fixing the compatible revealed some schema errors
which are fixed.
There's a bunch of others remaining after this which have bindings, but
those aren't converted to schema yet.
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: linux-clk@vger.kernel.org
Cc: dmaengine@vger.kernel.org
Cc: linux-i3c@lists.infradead.org
Cc: linux-iio@vger.kernel.org
Cc: linux-leds@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Alain Volmat <alain.volmat@foss.st.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20210316194918.3528417-1-robh@kernel.org
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210315085608.16010-2-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Align with all other i.MX using the mmc controller, align
the clock-names.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- Sync dtc to upstream version v1.6.0-51-g183df9e9c2b9 and build
host fdtoverlay
- Add kbuild support to build DT overlays (%.dtbo)
- Drop NULLifying match table in of_match_device(). In preparation for
this, there are several driver cleanups to use
(of_)?device_get_match_data().
- Drop pointless wrappers from DT struct device API
- Convert USB binding schemas to use graph schema and remove old plain
text graph binding doc
- Convert spi-nor and v3d GPU bindings to DT schema
- Tree wide schema fixes for if/then schemas, array size constraints,
and undocumented compatible strings in examples
- Handle 'no-map' correctly for already reserved memblock regions
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Merge tag 'devicetree-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Sync dtc to upstream version v1.6.0-51-g183df9e9c2b9 and build host
fdtoverlay
- Add kbuild support to build DT overlays (%.dtbo)
- Drop NULLifying match table in of_match_device().
In preparation for this, there are several driver cleanups to use
(of_)?device_get_match_data().
- Drop pointless wrappers from DT struct device API
- Convert USB binding schemas to use graph schema and remove old plain
text graph binding doc
- Convert spi-nor and v3d GPU bindings to DT schema
- Tree wide schema fixes for if/then schemas, array size constraints,
and undocumented compatible strings in examples
- Handle 'no-map' correctly for already reserved memblock regions
* tag 'devicetree-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (35 commits)
driver core: platform: Drop of_device_node_put() wrapper
of: Remove of_dev_{get,put}()
dt-bindings: usb: Change descibe to describe in usbmisc-imx.txt
dt-bindings: can: rcar_canfd: Group tuples in pin control properties
dt-bindings: power: renesas,apmu: Group tuples in cpus properties
dt-bindings: mtd: spi-nor: Convert to DT schema format
dt-bindings: Use portable sort for version cmp
dt-bindings: ethernet-controller: fix fixed-link specification
dt-bindings: irqchip: Add node name to PRUSS INTC
dt-bindings: interconnect: Fix the expected number of cells
dt-bindings: Fix errors in 'if' schemas
dt-bindings: iommu: renesas,ipmmu-vmsa: Make 'power-domains' conditionally required
dt-bindings: Fix undocumented compatible strings in examples
kbuild: Add support to build overlays (%.dtbo)
scripts: dtc: Remove the unused fdtdump.c file
scripts: dtc: Build fdtoverlay tool
scripts/dtc: Update to upstream version v1.6.0-51-g183df9e9c2b9
scripts: dtc: Fetch fdtoverlay.c from external DTC project
dt-bindings: thermal: sun8i: Fix misplaced schema keyword in compatible strings
dt-bindings: iio: dac: Fix AD5686 references
...
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot
* clk-vc5:
clk: vc5: Add support for optional load capacitance
dt-bindings: clk: versaclock5: Add optional load capacitance property
* clk-silabs:
clk: si570: Skip NVM to RAM recall operation if an optional property is set
dt-bindings: clock: si570: Add 'silabs,skip-recall' property
* clk-aspeed:
clk: aspeed: Fix APLL calculate formula from ast2600-A2
* clk-qoriq:
clk: qoriq: use macros to generate pll_mask
* clk-rohm:
clk: BD718x7: Do not depend on parent driver data
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM630 and SDM660 SoCs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-10-angelogioacchino.delregno@somainline.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the eASIC
N5X platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210212143059.478554-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add an optional property so the driver can skip calling the NVM->RAM
recall operation during probe().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Link: https://lore.kernel.org/r/1612496104-3437-2-git-send-email-saeed.nowshadi@xilinx.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There are two registers which can set the load capacitance for
XTAL1 and XTAL2. These are optional registers when using an
external crystal. Since XTAL1 and XTAL2 will set to the same value,
update the binding to support a single property called
xtal-load-femtofarads.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20210207185140.3653350-1-aford173@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-5-arnd@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.
Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The zte zx platform is getting removed, so this driver is no
longer needed.
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The tango platform is getting removed, so the driver is no
longer needed.
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-2-arnd@kernel.org
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
driver needs to use different PFD & VCO limits.
For ZynqMP, these needs to be selected by using the
'adi,zynqmp-axi-clkgen-2.00.a' string.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-4-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for global clock controller on SM8350 SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Running 'dt-validate -m' will flag any compatible strings missing a schema.
Fix all the errors found in DT binding examples. Most of these are just
typos.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Tomer Maimon <tmaimon77@gmail.com>
Cc: Tali Perry <tali.perry1@gmail.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Will Deacon <will@kernel.org>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Vincent Cheng <vincent.cheng.xh@renesas.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: linux-watchdog@vger.kernel.org
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Daniel Palmer <daniel@thingy.jp>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210202205544.24812-1-robh@kernel.org
The datasheet for the RZ/G2 Series show the bit for choosing between a crystal
oscillator and an external oscillator is present. Add the bindings for
r8a774a1 (RZ/G2M), r8a774b1 (RZ/G2N), and r8a774e1 (RZ/G2H)
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201228202221.2327468-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
DT properties which can have multiple entries need to specify what the
entries are and define how many entries there can be. In the case of
only a single entry, just 'maxItems: 1' is sufficient.
Add the missing entry constraints. These were found with a modified
meta-schema. Unfortunately, there are a few cases where the size
constraints are not defined such as common bindings, so the meta-schema
can't be part of the normal checks.
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210104230253.2805217-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
ability to get struct clk pointers from a struct clk_hw so that clk providers
can consume the clks they provide, if they need to do something like that. This
has been a long missing part of the clk provider API that will help us move
away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are
added for the clk_set_rate() "range" functions, similar to the tracepoints we
already have for clk_set_rate() and we added a column to debugfs to help
developers understand the hardware enable state of clks in case firmware or
bootloader state is different than what is expected. Overall the core changes
are mostly improving the clk driver writing experience.
At the driver level, we have the usual collection of driver updates and new
drivers for new SoCs. This time around the Qualcomm folks introduced a good
handful of clk drivers for various parts of three or four SoCs. The SiFive
folks added a new clk driver for their FU740 SoCs, coming in second on the
diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that
for various new features. One last thing to note in the driver area is that the
i.MX driver has gained a new binding to support SCU clks after being on the
list for many months. It uses a two cell binding which is sort of rare in clk
DT bindings. Beyond that we have the usual set of driver fixes and tweaks that
come from more testing and finding out that some configuration was wrong or
that a driver could support being built as a module.
Core:
- Add some trace points for clk_set_rate() "range" functions
- Add hardware enable information to clk_summary debugfs
- Replace clk-provider.h with of_clk.h when possible
- Add devm variant of clk_notifier_register()
- Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw
New Drivers:
- Bindings for Canaan K210 SoC clks
- Support for SiFive FU740 PRCI
- Camera clks on Qualcomm SC7180 SoCs
- GCC and RPMh clks on Qualcomm SDX55 SoCs
- RPMh clks on Qualcomm SM8350 SoCs
- LPASS clks on Qualcomm SM8250 SoCs
Updates:
- DVFS support for AT91 clk driver
- Update git repo branch for Renesas clock drivers
- Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
- Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
- Stop using __raw_*() I/O accessors in Renesas clk drivers
- One more conversion of DT bindings to json-schema
- Make i.MX clk-gate2 driver more flexible
- New two cell binding for i.MX SCU clks
- Drop of_match_ptr() in i.MX8 clk drivers
- Add arch dependencies for Rockchip clk drivers
- Fix i2s on Rockchip rk3066
- Add MIPI DSI clks on Amlogic axg and g12 SoCs
- Support modular builds of Amlogic clk drivers
- Fix an Amlogic Video PLL clock dependency
- Samsung Kconfig dependencies updates for better compile test coverage
- Refactoring of the Samsung PLL clocks driver
- Small Tegra driver cleanups
- Minor fixes to Ingenic and VC5 clk drivers
- Cleanup patches to remove unused variables and plug memory leaks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The core framework got some nice improvements this time around. We
gained the ability to get struct clk pointers from a struct clk_hw so
that clk providers can consume the clks they provide, if they need to
do something like that. This has been a long missing part of the clk
provider API that will help us move away from exposing a struct clk
pointer in the struct clk_hw. Tracepoints are added for the
clk_set_rate() "range" functions, similar to the tracepoints we
already have for clk_set_rate() and we added a column to debugfs to
help developers understand the hardware enable state of clks in case
firmware or bootloader state is different than what is expected.
Overall the core changes are mostly improving the clk driver writing
experience.
At the driver level, we have the usual collection of driver updates
and new drivers for new SoCs. This time around the Qualcomm folks
introduced a good handful of clk drivers for various parts of three or
four SoCs. The SiFive folks added a new clk driver for their FU740
SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic
SoCs had lots of work done after that for various new features. One
last thing to note in the driver area is that the i.MX driver has
gained a new binding to support SCU clks after being on the list for
many months. It uses a two cell binding which is sort of rare in clk
DT bindings. Beyond that we have the usual set of driver fixes and
tweaks that come from more testing and finding out that some
configuration was wrong or that a driver could support being built as
a module.
Summary:
Core:
- Add some trace points for clk_set_rate() "range" functions
- Add hardware enable information to clk_summary debugfs
- Replace clk-provider.h with of_clk.h when possible
- Add devm variant of clk_notifier_register()
- Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw
New Drivers:
- Bindings for Canaan K210 SoC clks
- Support for SiFive FU740 PRCI
- Camera clks on Qualcomm SC7180 SoCs
- GCC and RPMh clks on Qualcomm SDX55 SoCs
- RPMh clks on Qualcomm SM8350 SoCs
- LPASS clks on Qualcomm SM8250 SoCs
Updates:
- DVFS support for AT91 clk driver
- Update git repo branch for Renesas clock drivers
- Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
- Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
- Stop using __raw_*() I/O accessors in Renesas clk drivers
- One more conversion of DT bindings to json-schema
- Make i.MX clk-gate2 driver more flexible
- New two cell binding for i.MX SCU clks
- Drop of_match_ptr() in i.MX8 clk drivers
- Add arch dependencies for Rockchip clk drivers
- Fix i2s on Rockchip rk3066
- Add MIPI DSI clks on Amlogic axg and g12 SoCs
- Support modular builds of Amlogic clk drivers
- Fix an Amlogic Video PLL clock dependency
- Samsung Kconfig dependencies updates for better compile test coverage
- Refactoring of the Samsung PLL clocks driver
- Small Tegra driver cleanups
- Minor fixes to Ingenic and VC5 clk drivers
- Cleanup patches to remove unused variables and plug memory leaks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
dt-binding: clock: Document canaan,k210-clk bindings
dt-bindings: Add Canaan vendor prefix
clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
clk: ingenic: Fix divider calculation with div tables
clk: sunxi-ng: Make sure divider tables have sentinel
clk: s2mps11: Fix a resource leak in error handling paths in the probe function
clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
clk: si5351: Wait for bit clear after PLL reset
clk: at91: sam9x60: remove atmel,osc-bypass support
clk: at91: sama7g5: register cpu clock
clk: at91: clk-master: re-factor master clock
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
clk: at91: sama7g5: decrease lower limit for MCK0 rate
clk: at91: sama7g5: remove mck0 from parent list of other clocks
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
clk: at91: clk-master: add 5th divisor for mck master
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
dt-bindings: clock: at91: add sama7g5 pll defines
clk: at91: sama7g5: fix compilation error
...
- Bindings for Canaan K210 SoC clks
* clk-ingenic:
clk: ingenic: Fix divider calculation with div tables
* clk-vc5:
clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
* clk-cleanup:
clk: sunxi-ng: Make sure divider tables have sentinel
clk: s2mps11: Fix a resource leak in error handling paths in the probe function
clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
clk: bcm: dvp: drop a variable that is assigned to only
* clk-canaan:
dt-binding: clock: Document canaan,k210-clk bindings
dt-bindings: Add Canaan vendor prefix
* clk-marvell:
clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
- Add some trace points for clk_set_rate() "range" functions
- DVFS support for AT91 clk driver
* clk-ti:
clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
clk: ti: Fix memleak in ti_fapll_synth_setup
* clk-analog:
clk: axi-clkgen: move the OF table at the bottom of the file
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format
* clk-trace:
clk: Trace clk_set_rate() "range" functions
* clk-at91:
clk: at91: sam9x60: remove atmel,osc-bypass support
clk: at91: sama7g5: register cpu clock
clk: at91: clk-master: re-factor master clock
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
clk: at91: sama7g5: decrease lower limit for MCK0 rate
clk: at91: sama7g5: remove mck0 from parent list of other clocks
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
clk: at91: clk-master: add 5th divisor for mck master
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
dt-bindings: clock: at91: add sama7g5 pll defines
clk: at91: sama7g5: fix compilation error
* clk-silabs:
clk: si5351: Wait for bit clear after PLL reset
- Support for SiFive FU740 PRCI
- Add hardware enable information to clk_summary debugfs
* clk-tegra:
clk: tegra: Fix duplicated SE clock entry
clk: tegra: bpmp: Clamp clock rates on requests
clk: tegra: Do not return 0 on failure
* clk-imx: (24 commits)
clk: imx: scu: remove the calling of device_is_bound
clk: imx: scu: Make pd_np with static keyword
clk: imx8mq: drop of_match_ptr from of_device_id table
clk: imx8mp: drop of_match_ptr from of_device_id table
clk: imx8mn: drop of_match_ptr from of_device_id table
clk: imx8mm: drop of_match_ptr from of_device_id table
clk: imx: gate2: Remove unused variable ret
clk: imx: gate2: Add locking in is_enabled op
clk: imx: gate2: Add cgr_mask for more flexible number of control bits
clk: imx: gate2: Check if clock is enabled against cgr_val
clk: imx: gate2: Keep the register writing in on place
clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
clk: imx: scu: fix build break when compiled as modules
clk: imx: remove redundant assignment to pointer np
clk: imx: remove unneeded semicolon
clk: imx: lpcg: add suspend/resume support
clk: imx: clk-imx8qxp-lpcg: add runtime pm support
clk: imx: lpcg: allow lpcg clk to take device pointer
clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
clk: imx: scu: add suspend/resume support
...
* clk-sifive:
clk: sifive: Add clock enable and disable ops
clk: sifive: Fix the wrong bit field shift
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Use common name for prci configuration
clk: sifive: Extract prci core to common base
dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI
* clk-mediatek:
clk: mediatek: Make mtk_clk_register_mux() a static function
* clk-summary:
clk: Add hardware-enable column to clk summary
Document the device tree bindings of the Canaan Kendryte K210 SoC clock
driver in Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.
The header file include/dt-bindings/clock/k210-clk.h is modified to
include the complete list of IDs for all clocks of the SoC.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201220085725.19545-3-damien.lemoal@wdc.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Eliminate the following yamllint warnings:
./Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
:32:13:[warning] wrong indentation: expected 14 but found 12 (indentation)
:35:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201207045527.1607-2-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
This change converts the old binding for the AXI clkgen driver to a yaml
format.
As maintainers, added:
- Lars-Peter Clausen <lars@metafoo.de> - as original author of driver &
binding
- Michael Hennerich <michael.hennerich@analog.com> - as supporter of
Analog Devices drivers
Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201013143421.84188-1-alexandru.ardelean@analog.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Across all platforms, there is a continued move towards DT schema for
validating the dts files. As a result there are bug fixes for mistakes
that are found using these schema, in addition to warnings from the
dtc compiler.
As usual, many changes are for adding support for additional on-chip
and on-board components in the machines we already support.
The newly supported SoCs for this release are:
- MStar Infinity2M, a low-end IP camera chip based on a dual-core
Cortex-A7, otherwise similar to the Infinity chip we already support.
This is also known as the SigmaStar SSD202D, and we add support for
the Honestar ssd201htv2 development kit.
- Nuvoton NPCM730, a Cortex-A9 based Baseboard Management Controller
(BMC), in the same family as the NPCM750. This gets used in the Ampere
Altra based "Fii Kudo" server and the Quanta GSJ, both of which are
added as well.
- Broadcom BCM4908, a 64-bit home router chip based on Broadcom's own
Brahma-B53 CPU. Support is also added for the Asus ROG Rapture
GT-AC5300 high-end WiFi router based on this chip.
- Mediatek MT8192 is a new SoC based on eight Cortex-A76/A55 cores,
meant for faster Chromebooks and tablets. It gets added along with
its reference design.
- Mediatek MT6779 (Helio P90) is a high-end phone chip from last year's
generation, also added along with its reference board. This one is
still based on Cortex-A75/A55.
- Mediatek MT8167 is a version of the already supported MT8516 chip,
both based on Cortex-A35. It gets added along with the "Pumpkin"
single board computer, but is likely to also make its way into low-end
tablets in the future.
For the already supported chips, there are a number of new boards.
Interestingly there are more 32-bit machines added this time than
64-bit. Here is a brief list of the new boards:
- Three new Mikrotik router variants based on Marvell Prestera
98DX3236, a close relative of the more common Armada XP
- A reference board for the Marvell Armada 382
- Three new servers using ASpeed baseboard management controllers,
the actual machines being from Bytedance, Facebook and IBM,
and one machine using the Nuvoton NPCM750 BMC.
- The Galaxy Note 10.1 (P4) tablet, using an Exynos 4412.
- The usual set of 32-bit i.MX industrial/embedded hardware:
* Protonic WD3 (tractor e-cockpit)
* Kamstrup OMNIA Flex Concentrator (smart grid platform)
* Van der Laan LANMCU (food storage)
* Altesco I6P (vehicle inspection stations)
* PHYTEC phyBOARD-Segin/phyCORE-i.MX6UL baseboard
- DH electronics STM32MP157C DHCOM, a PicoITX carrier board
for the aleady supported DHCOM module
- Three new Allwinner SoC based single-board computers:
* NanoPi R1 (H3 based)
* FriendlyArm ZeroPi (H3 based)
* Elimo Initium SBC (S3 based)
- Ouya Game Console based on Nvidia Tegra 3
- Version 5 of the already supported Zynq Z-Turn MYIR Board
- LX2162AQDS, a reference platform for NXP Layerscape
LX2162A, which is a repackaged 16-core LX2160A
- A series of Kontron i.MX8M Mini baseboard/SoM versions
- Espressobin Ultra, a new variant of the popular Armada 3700 based board,
- IEI Puzzle-M801, a rackmount network appliance based on
Marvell Armada 8040
- Microsoft Lumia 950 XL, a phone
- HDK855 and HDK865 Hardware development kits for Qualcomm
sm8250 and sm8150, respectively
- Three new board variants of the "Trogdor" Chromebook
(sc7180)
- New board variants of the Renesas based "Kingfisher" and
"HiHope" reference boards
- Kobol Helios64, an open source NAS appliance based on Rockchips
RK3399
- Engicam PX30.Core, a SoM based on Rockchip PX30, along with
a few carrier boards.
There is one conflict in mt6577_auxadc.txt, which got replaced in
another tree and modified here, the modification is already part of
the new file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-dt-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM device tree updates from Arnd Bergmann:
"Across all platforms, there is a continued move towards DT schema for
validating the dts files. As a result there are bug fixes for mistakes
that are found using these schema, in addition to warnings from the
dtc compiler.
As usual, many changes are for adding support for additional on-chip
and on-board components in the machines we already support.
The newly supported SoCs for this release are:
- MStar Infinity2M, a low-end IP camera chip based on a dual-core
Cortex-A7, otherwise similar to the Infinity chip we already
support. This is also known as the SigmaStar SSD202D, and we add
support for the Honestar ssd201htv2 development kit.
- Nuvoton NPCM730, a Cortex-A9 based Baseboard Management Controller
(BMC), in the same family as the NPCM750. This gets used in the
Ampere Altra based "Fii Kudo" server and the Quanta GSJ, both of
which are added as well.
- Broadcom BCM4908, a 64-bit home router chip based on Broadcom's own
Brahma-B53 CPU. Support is also added for the Asus ROG Rapture
GT-AC5300 high-end WiFi router based on this chip.
- Mediatek MT8192 is a new SoC based on eight Cortex-A76/A55 cores,
meant for faster Chromebooks and tablets. It gets added along with
its reference design.
- Mediatek MT6779 (Helio P90) is a high-end phone chip from last
year's generation, also added along with its reference board. This
one is still based on Cortex-A75/A55.
- Mediatek MT8167 is a version of the already supported MT8516 chip,
both based on Cortex-A35. It gets added along with the "Pumpkin"
single board computer, but is likely to also make its way into
low-end tablets in the future.
For the already supported chips, there are a number of new boards.
Interestingly there are more 32-bit machines added this time than
64-bit. Here is a brief list of the new boards:
- Three new Mikrotik router variants based on Marvell Prestera
98DX3236, a close relative of the more common Armada XP
- A reference board for the Marvell Armada 382
- Three new servers using ASpeed baseboard management controllers,
the actual machines being from Bytedance, Facebook and IBM, and one
machine using the Nuvoton NPCM750 BMC.
- The Galaxy Note 10.1 (P4) tablet, using an Exynos 4412.
- The usual set of 32-bit i.MX industrial/embedded hardware:
* Protonic WD3 (tractor e-cockpit)
* Kamstrup OMNIA Flex Concentrator (smart grid platform)
* Van der Laan LANMCU (food storage)
* Altesco I6P (vehicle inspection stations)
* PHYTEC phyBOARD-Segin/phyCORE-i.MX6UL baseboard
- DH electronics STM32MP157C DHCOM, a PicoITX carrier board for the
aleady supported DHCOM module
- Three new Allwinner SoC based single-board computers:
* NanoPi R1 (H3 based)
* FriendlyArm ZeroPi (H3 based)
* Elimo Initium SBC (S3 based)
- Ouya Game Console based on Nvidia Tegra 3
- Version 5 of the already supported Zynq Z-Turn MYIR Board
- LX2162AQDS, a reference platform for NXP Layerscape LX2162A, which
is a repackaged 16-core LX2160A
- A series of Kontron i.MX8M Mini baseboard/SoM versions
- Espressobin Ultra, a new variant of the popular Armada 3700 based
board,
- IEI Puzzle-M801, a rackmount network appliance based on Marvell
Armada 8040
- Microsoft Lumia 950 XL, a phone
- HDK855 and HDK865 Hardware development kits for Qualcomm sm8250 and
sm8150, respectively
- Three new board variants of the "Trogdor" Chromebook (sc7180)
- New board variants of the Renesas based "Kingfisher" and "HiHope"
reference boards
- Kobol Helios64, an open source NAS appliance based on Rockchips
RK3399
- Engicam PX30.Core, a SoM based on Rockchip PX30, along with a few
carrier boards"
* tag 'arm-soc-dt-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (679 commits)
arm64: dts: sparx5: Add SGPIO devices
arm64: dts: sparx5: Add reset support
dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver
ARM: mstar: SMP support
ARM: mstar: Wire up smpctrl for SSD201/SSD202D
ARM: mstar: Add smp ctrl registers to infinity2m dtsi
ARM: mstar: Add dts for Honestar ssd201htv2
ARM: mstar: Add chip level dtsi for SSD202D
ARM: mstar: Add common dtsi for SSD201/SSD202D
ARM: mstar: Add infinity2m support
dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards
dt-bindings: vendor-prefixes: Add honestar vendor prefix
dt-bindings: mstar: Add binding details for mstar,smpctrl
ARM: mstar: Fill in GPIO controller properties for infinity
ARM: mstar: Add gpio controller to MStar base dtsi
ARM: zynq: Fix incorrect reference to XM013 instead of XM011
ARM: zynq: Convert at25 binding to new description on zc770-xm013
ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
ARM: zynq: Fix leds subnode name for zc702/zybo-z7
ARM: zynq: Rename bus to be align with simple-bus yaml
...
- New phy drivers:
- Mediatek MT7621 PCIe PHY (promoted from staging)
- Ingenic USB phy driver supporting JZ4775 and X2000
- Intel Keem Bay USB PHY driver
- Marvell USB HSIC PHY driver supporting MMP3 SoC
- AXG MIPI D-PHY driver
- Updates:
- Conversion to YAML binding for:
- Broadcom SATA PHY
- Cadence Sierra PHY bindings
- STM32 USBC Phy
- Support for Exynos5433 PCIe PHY
- Support for Qualcomm SM8250 PCIe QMP PHY
- Support for Exynos5420 USB2 phy
- devm_platform_ioremap_resource conversion for bunch of drivers
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Merge tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:
phy-for-5.11
- New phy drivers:
- Mediatek MT7621 PCIe PHY (promoted from staging)
- Ingenic USB phy driver supporting JZ4775 and X2000
- Intel Keem Bay USB PHY driver
- Marvell USB HSIC PHY driver supporting MMP3 SoC
- AXG MIPI D-PHY driver
- Updates:
- Conversion to YAML binding for:
- Broadcom SATA PHY
- Cadence Sierra PHY bindings
- STM32 USBC Phy
- Support for Exynos5433 PCIe PHY
- Support for Qualcomm SM8250 PCIe QMP PHY
- Support for Exynos5420 USB2 phy
- devm_platform_ioremap_resource conversion for bunch of drivers
* tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
drm/mediatek: avoid dereferencing a null hdmi_phy on an error message
phy: ingenic: depend on HAS_IOMEM
phy: mediatek: statify mtk_hdmi_phy_driver
dt-bindings: phy: Convert Broadcom SATA PHY to YAML
devicetree: phy: rockchip-emmc add output-tapdelay-select
phy: rockchip-emmc: output tap delay dt property
PHY: Ingenic: Add USB PHY driver using generic PHY framework.
dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000.
USB: PHY: JZ4770: Remove unnecessary function calls.
devicetree: phy: rockchip-emmc: pulldown property
phy: rockchip: set pulldown for strobe line in dts
phy: renesas: rcar-gen3-usb2: disable runtime pm in case of failure
phy: mediatek: allow compile-testing the hdmi phy
phy/rockchip: Make PHY_ROCKCHIP_INNO_HDMI depend on HAS_IOMEM to fix build error
phy: samsung: Merge Kconfig for Exynos5420 and Exynos5250
phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro
phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig
phy: mediatek: Make PHY_MTK_{XSPHY, TPHY} depend on HAS_IOMEM and OF_ADDRESS to fix build errors
phy: tegra: xusb: Fix usb_phy device driver field
phy: amlogic: replace devm_reset_control_array_get()
...
- Quite some patches that update vendor-prefixes.yaml and fsl.yaml to
document missing board compatibles and add new board compatibles.
- A couple of patches from Dong Aisheng to update imx-scu firmware and
imx-lpcg clock bindings for new SCU two cells clock support.
- A couple of net bindings update from Ioana Ciornei to complete the
MAC/PCS/PHY representation on DPAA2 devices.
- Document watchdog compatibles for all i.MX and Layerscape devices.
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Merge tag 'imx-bindings-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT bindings update for 5.11:
- Quite some patches that update vendor-prefixes.yaml and fsl.yaml to
document missing board compatibles and add new board compatibles.
- A couple of patches from Dong Aisheng to update imx-scu firmware and
imx-lpcg clock bindings for new SCU two cells clock support.
- A couple of net bindings update from Ioana Ciornei to complete the
MAC/PCS/PHY representation on DPAA2 devices.
- Document watchdog compatibles for all i.MX and Layerscape devices.
* tag 'imx-bindings-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (35 commits)
dt-bindings: arm: fsl: add Protonic WD3 board
dt-bindings: vendor-prefixes: add "virtual" prefix
dt-bindings: fsl: add kamstrup flex concentrator to schema
dt-bindings: arm: fsl: document i.MX7S boards
dt-bindings: arm: fsl: document SolidRun LX2160A boards
dt-bindings: arm: fsl: document LS1012A FRWY board
dt-bindings: arm: fsl: add Van der Laan LANMCU board
dt-bindings: arm: fsl: add Altesco I6P board
dt-bindings: vendor-prefixes: Add an entry for Altus-Escon-Company
dt-bindings: net: add the 10gbase-r connection type
dt-bindings: net: add the DPAA2 MAC DTS definition
dt-bindings: fsl: add compatible for LX2162A QDS Board
dt-bindings: vendor-prefixes: Add an entry for Van der Laan b.v.
dt-bindings: arm: fsl: document i.MX7D boards
dt-bindings: arm: fsl: document i.MX6ULL boards
dt-bindings: arm: fsl: document i.MX6UL boards
dt-bindings: arm: fsl: document i.MX6SX boards
dt-bindings: arm: fsl: document i.MX6SL boards
dt-bindings: arm: fsl: document i.MX6QP boards
dt-bindings: arm: fsl: document i.MX6Q boards
...
Link: https://lore.kernel.org/r/20201202142717.9262-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device tree bindings for global clock controller on SDX55 SoCs.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201126072844.35370-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Move Ingenic USB PHY bindings from Documentation/devicetree/bindings/usb
to Documentation/devicetree/bindings/phy, and add bindings for JZ4775 SoC
and X2000 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201116141906.11758-3-zhouyanjie@wanyeetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Since commit:
0e030a373d ("can: flexcan: fix endianess detection")
the fsl,imx53-flexcan isn't compatible with the fsl,p1010-flexcan any more. As
the former accesses the IP core in Little Endian mode and the latter uses Big
Endian mode.
With the conversion of the flexcan DT bindings to yaml, the dt_binding_check
this throws the following error:
Documentation/devicetree/bindings/clock/imx5-clock.example.dt.yaml: can@53fc8000: compatible: 'oneOf' conditional failed, one must be fixed:
['fsl,imx53-flexcan', 'fsl,p1010-flexcan'] is too long
Additional items are not allowed ('fsl,p1010-flexcan' was unexpected)
'fsl,imx53-flexcan' is not one of ['fsl,imx7d-flexcan', 'fsl,imx6ul-flexcan', 'fsl,imx6sx-flexcan']
'fsl,imx53-flexcan' is not one of ['fsl,ls1028ar1-flexcan']
'fsl,imx6q-flexcan' was expected
'fsl,lx2160ar1-flexcan' was expected
From schema: /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
The error is fixed by replacing the "fsl,p1010-flexcan" compatible
(which turned out the be incompatible) with "fsl,imx25-flexcan" in the
binding example.
Reported-by: Rob Herring <robh+dt@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20201111213548.1621094-1-mkl@pengutronix.de
[robh: Add "fsl,imx25-flexcan" as fallback]
Signed-off-by: Rob Herring <robh@kernel.org>
Always ON Clock controller is a block inside LPASS which controls
1 Glitch free muxes to LPASS codec Macros.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20201026120221.18984-3-srinivas.kandagatla@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Camera Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for camera clocks which are required to bring the camera
subsystem out of reset.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1602873815-1677-4-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside
in different subsystems across CPUs and also vary a bit on the availability.
Same as SCU clock, we want to move the clock definition into device tree
which can fully decouple the dependency of Clock ID definition from device
tree and make us be able to write a fully generic lpcg clock driver.
And we can also use the existence of clock nodes in device tree to address
the device and clock availability differences across different SoCs.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
of various clk driver updates. The biggest driver updates in terms of lines of
code is the Allwinner driver, closely followed by the Qualcomm and Mediatek
drivers. All of those hit high because we add so many lines of clk data. Coming
in fourth place is i.MX which also adds a bunch of clk data. This accounts for
the new driver additions this time around.
Otherwise the patches are lots of little cleanups and fixes for various clk
drivers that have baked in linux-next for a while. I suppose one highlight or
theme is that more clk drivers are being updated to work as modules, which is
interesting to see such critical SoC infrastructure work as a loadable module.
New Drivers:
- Support qcom SM8150/SM8250 video and display clks
- Support Mediatek MT8167 clks
- Add clock for CRC block found on vf610 SoCs
- Add support for the Renesas R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on Renesas RZ/G1H
- Support Allwinner A100 SoC clks
Removed Drivers:
- Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
Updates:
- Change how qcom's display port clks work
- Small non-critical fixes for TI clk driver
- Remove various unused variables in clk drivers
- Allow Rockchip clk driver to be a module
- Remove most __clk_lookup() calls in Samsung drivers (yay!)
- Support building i.MX ARMv8 platforms clock driver as module
- Some kerneldoc fixes here and there
- A couple of minor i.MX clk data corrections
- Update audio clock inverter and fdiv2 flag on Amlogic g12
- Make amlogic clk drivers configurable in Kconfig
- Fix Renesas VSP clock names to match corrected hardware documentation
- Sigma-delta modulation on Allwinner R40
- Various fixes for at91 clk driver
- Use semicolons instead of commas in some places
- Mark some variables const so they can move to RO memory
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This contains no changes to the core framework. It is a collection of
various clk driver updates.
The biggest driver updates in terms of lines of code is the Allwinner
driver, closely followed by the Qualcomm and Mediatek drivers. All of
those hit high because we add so many lines of clk data. Coming in
fourth place is i.MX which also adds a bunch of clk data. This
accounts for the new driver additions this time around.
Otherwise the patches are lots of little cleanups and fixes for
various clk drivers that have baked in linux-next for a while. I
suppose one highlight or theme is that more clk drivers are being
updated to work as modules, which is interesting to see such critical
SoC infrastructure work as a loadable module.
New Drivers:
- Support qcom SM8150/SM8250 video and display clks
- Support Mediatek MT8167 clks
- Add clock for CRC block found on vf610 SoCs
- Add support for the Renesas R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on Renesas RZ/G1H
- Support Allwinner A100 SoC clks
Removed Drivers:
- Remove i.MX21 clock driver, as i.MX21 platform support is being
dropped
Updates:
- Change how qcom's display port clks work
- Small non-critical fixes for TI clk driver
- Remove various unused variables in clk drivers
- Allow Rockchip clk driver to be a module
- Remove most __clk_lookup() calls in Samsung drivers (yay!)
- Support building i.MX ARMv8 platforms clock driver as module
- Some kerneldoc fixes here and there
- A couple of minor i.MX clk data corrections
- Update audio clock inverter and fdiv2 flag on Amlogic g12
- Make amlogic clk drivers configurable in Kconfig
- Fix Renesas VSP clock names to match corrected hardware
documentation
- Sigma-delta modulation on Allwinner R40
- Various fixes for at91 clk driver
- Use semicolons instead of commas in some places
- Mark some variables const so they can move to RO memory"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
clk: imx8mq: Fix usdhc parents order
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
clk: at91: sam9x60: support only two programmable clocks
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
clk: clk-prima2: fix return value check in prima2_clk_init()
clk: mmp2: Fix the display clock divider base
clk: pxa: Constify static struct clk_ops
clk: baikal-t1: Mark Ethernet PLL as critical
clk: qoriq: modify MAX_PLL_DIV to 32
clk: axi-clkgen: Set power bits for fractional mode
clk: axi-clkgen: Add support for fractional dividers
...
- Support qcom SM8150/SM8250 video and display clks
- Change how qcom's display port clks work
* clk-ingenic:
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
* clk-at91:
clk: at91: sam9x60: support only two programmable clocks
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
* clk-kconfig:
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
* clk-imx:
clk: imx8mq: Fix usdhc parents order
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
* clk-qcom:
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: qcom: Add display clock controller driver for SM8150 and SM8250
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: add video clock controller driver for SM8250
clk: qcom: add video clock controller driver for SM8150
dt-bindings: clock: add SM8250 QCOM video clock bindings
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
clk/qcom: fix spelling typo
clk: qcom: gcc-sdm660: Fix wrong parent_map
clk: qcom: dispcc: Update DP clk ops for phy design
clk: qcom: gcc-msm8939: remove defined but not used variables
clk: qcom: ipq8074: make pcie0_rchng_clk_src static
* clk-prima2:
clk: clk-prima2: fix return value check in prima2_clk_init()
* clk-bcm:
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: bcm: rpi: Add register to control pixel bvb clk
- Update dtc to upstream version v1.6.0-31-gcbca977ea121
- dtx_diff help text reformatting
- Speed-up validation time for binding and dtb checks using json for
intermediate files
- Add support for running yamllint on DT schema files
- Remove old booting-without-of.rst
- Extend the example schema to address common issues
- Cleanup handling of additionalProperties/unevaluatedProperties
- Ensure all DSI controller schemas reference dsi-controller.yaml
- Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex, DFI,
and Cisco Meraki
- Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
schema
- Convert HiSilicon SoC and syscon bindings to DT schema
- Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema
- Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR,
SATA, vf610 GPIO, and UART to DT schema
- Add i.MX 8M compatible strings
- Add LM81 and DS1780 as trivial devices
- Various missing properties added to fix dtb validation warnings
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Merge tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Update dtc to upstream version v1.6.0-31-gcbca977ea121
- dtx_diff help text reformatting
- Speed-up validation time for binding and dtb checks using json for
intermediate files
- Add support for running yamllint on DT schema files
- Remove old booting-without-of.rst
- Extend the example schema to address common issues
- Cleanup handling of additionalProperties/unevaluatedProperties
- Ensure all DSI controller schemas reference dsi-controller.yaml
- Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex,
DFI, and Cisco Meraki
- Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
schema
- Convert HiSilicon SoC and syscon bindings to DT schema
- Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema
- Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR, SATA, vf610
GPIO, and UART to DT schema
- Add i.MX 8M compatible strings
- Add LM81 and DS1780 as trivial devices
- Various missing properties added to fix dtb validation warnings
* tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (111 commits)
dt-bindings: misc: explicitly add #address-cells for slave mode
spi: dt-bindings: spi-controller: explicitly require #address-cells=<0> for slave mode
dt: Remove booting-without-of.rst
dt-bindings: update usb-c-connector example
dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml
dt-bindings: arm: hisilicon: add missing properties into sysctrl.yaml
dt-bindings: pwm: imx: document i.MX compatibles
scripts/dtc: Update to upstream version v1.6.0-31-gcbca977ea121
dt-bindings: Add running yamllint to dt_binding_check
dt-bindings: powerpc: Add a schema for the 'sleep' property
dt-bindings: pinctrl: sirf: Fix typo abitrary
dt-bindings: pinctrl: qcom: Fix typo abitrary
dt-bindings: Explicitly allow additional properties in common schemas
dt-bindings: Use 'additionalProperties' instead of 'unevaluatedProperties'
dt-bindings: Add missing 'unevaluatedProperties'
Docs: Fixing spelling errors in Documentation/devicetree/bindings/
dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema
dt-bindings: riscv: convert pwm bindings to json-schema
dt-bindings: riscv: convert plic bindings to json-schema
dt-bindings: fu540: prci: convert PRCI bindings to json-schema
...
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250)
Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for video clock controller for SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200923160635.28370-4-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for video clock controller for SM8150 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200923160635.28370-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 videocc bindings.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200923160635.28370-2-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In cases where we don't reference another schema, 'additionalProperties'
can be used instead. This is preferred for now as 'unevaluatedProperties'
support isn't implemented yet.
In a few cases, this means adding some missing property definitions of
which most are for SPI bus properties. 'unevaluatedProperties' is not going
to work for the SPI bus properties anyways as they are evaluated from the
parent node, not the SPI child node.
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20201005183830.486085-3-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
The clock controller schemas for i.MX 8M Mini, 8M Nano, 8M Plus and 8M
Quad are basically the same. The only minor difference appears on 8M
Quad which needs one more clock.
There is no point to have four schemas for almost the same binding. Any
fixes or changes would have to be duplicated four times.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
The i.MX 8 DTSes use two compatibles so update the binding to fix
dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000:
compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long
From schema: Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000:
compatible: Additional items are not allowed ('fsl,imx7d-usdhc' was unexpected)
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: mmc@30b40000:
compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200829062505.4642-1-krzk@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Update the i.MX23 clock example to align with MXS AUART binding doc to
avoid below build error:
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: clocks: [[4294967295, 32]] is too short
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: 'dmas' is a required property
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: 'dma-names' is a required property
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1597721685-9280-2-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
Update the i.MX28 clock example to align with MXS AUART binding doc to
avoid below build error:
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: clocks: [[4294967295, 45]] is too short
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: compatible: Additional items are not allowed
('fsl,imx23-auart' was unexpected)
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: compatible: ['fsl,imx28-auart', 'fsl,imx23-auart']
is too long
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: 'dmas' is a required property
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: 'dma-names' is a required property
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1597721685-9280-1-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
happened to tag the tree at an earlier point in the history of clk-next.
I must have fat fingered it and checked out an older version of clk-next
on this second computer I'm using.
This time it actually includes more code for Qualcomm SoCs, the AT91
major updates, and some Rockchip SoC clk driver updates as well. I've
corrected this flow so this shouldn't happen again.
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd:
"Here's some more updates that missed the last pull request because I
happened to tag the tree at an earlier point in the history of
clk-next. I must have fat fingered it and checked out an older version
of clk-next on this second computer I'm using.
This time it actually includes more code for Qualcomm SoCs, the AT91
major updates, and some Rockchip SoC clk driver updates as well. I've
corrected this flow so this shouldn't happen again"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits)
clk: bcm2835: Do not use prediv with bcm2711's PLLs
clk: drop unused function __clk_get_flags
clk: hsdk: Fix bad dependency on IOMEM
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
clk: mmp: avoid missing prototype warning
clk: sparx5: Add Sparx5 SoC DPLL clock driver
dt-bindings: clock: sparx5: Add bindings include file
clk: qoriq: add LS1021A core pll mux options
clk: clk-atlas6: fix return value check in atlas6_clk_init()
clk: tegra: pll: Improve PLLM enable-state detection
clk: X1000: Add support for calculat REFCLK of USB PHY.
clk: JZ4780: Reformat the code to align it.
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
dt-bindings: clock: Add tabs to align code.
dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
clk: davinci: Use fallthrough pseudo-keyword
clk: imx: Use fallthrough pseudo-keyword
clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
clk: qcom: gcc-sdm660: Add missing modem reset
...
framework we just have some minor tweaks and a debugfs feature, so not much to
see there. The driver updates are fairly well split between AT91 and Qualcomm
clk support. Adding those two drivers together equals about 50% of the
diffstat. Otherwise, the big amount of work this time was on supporting
Broadcom's Raspberry Pi firmware clks. See below for some more highlights.
Core:
- Document clk_hw_round_rate() so it gets some more use
- Remove unused __clk_get_flags()
- Add a prepare/enable debugfs feature similar to rate setting
New Drivers:
- Add support for SAMA7G5 SoC clks
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Microchip Sparx5 DPLL clk
- Add support for the new Renesas RZ/G2H (R8A774E1) SoC
Updates:
- Make defines for bcm63xx-gate clks to use in DT
- Support BCM2711 SoC firmware clks
- Add HDMI clks for BCM2711 SoCs
- Add RTC related clks on Ingenic SoCs
- Support USB PHY clks on Ingenic SoCs
- Support gate clks on BCM6318 SoCs
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
- Use poll_timeout functions in Rockchip clk driver
- Support Rockchip rk3288w SoC variant
- Mark mac_lbtest critical on Rockchip rk3188
- Add CAAM clock support for i.MX vf610 driver
- Add MU root clock support for i.MX imx8mp driver
- Amlogic g12: add neural network accelerator clock sources
- Amlogic meson8: remove critical flag for main PLL divider
- Amlogic meson8: add video decoder clock gates
- Convert one more Renesas DT binding to json-schema
- Enhance critical clock handling on Renesas platforms to only consider
clocks that were enabled at boot time
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"It looks like a smaller batch of clk updates this time around.
In the core framework we just have some minor tweaks and a debugfs
feature, so not much to see there. The driver updates are fairly well
split between AT91 and Qualcomm clk support. Adding those two drivers
together equals about 50% of the diffstat.
Otherwise, the big amount of work this time was on supporting
Broadcom's Raspberry Pi firmware clks.
Highlights:
Core:
- Document clk_hw_round_rate() so it gets some more use
- Remove unused __clk_get_flags()
- Add a prepare/enable debugfs feature similar to rate setting
New Drivers:
- Add support for SAMA7G5 SoC clks
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Microchip Sparx5 DPLL clk
- Add support for the new Renesas RZ/G2H (R8A774E1) SoC
Updates:
- Make defines for bcm63xx-gate clks to use in DT
- Support BCM2711 SoC firmware clks
- Add HDMI clks for BCM2711 SoCs
- Add RTC related clks on Ingenic SoCs
- Support USB PHY clks on Ingenic SoCs
- Support gate clks on BCM6318 SoCs
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
- Use poll_timeout functions in Rockchip clk driver
- Support Rockchip rk3288w SoC variant
- Mark mac_lbtest critical on Rockchip rk3188
- Add CAAM clock support for i.MX vf610 driver
- Add MU root clock support for i.MX imx8mp driver
- Amlogic g12: add neural network accelerator clock sources
- Amlogic meson8: remove critical flag for main PLL divider
- Amlogic meson8: add video decoder clock gates
- Convert one more Renesas DT binding to json-schema
- Enhance critical clock handling on Renesas platforms to only
consider clocks that were enabled at boot time"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits)
clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
ipq806x: gcc: add support for child probe
clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
clk: qcom: ipq8074: Add correct index for PCIe clocks
clk: <linux/clk-provider.h>: drop a duplicated word
clk: renesas: cpg-mssr: Add r8a774e1 support
dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
clk: Drop duplicate selection in Kconfig
clk: qcom: smd: Add support for MSM8992/4 rpm clocks
clk: qcom: ipq8074: Add missing clocks for pcie
dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
Replace HTTP links with HTTPS ones: Common CLK framework
clk: qcom: Add CPU clock driver for msm8996
dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
soc: qcom: Separate kryo l2 accessors from PMU driver
clk: meson: meson8b: add the vclk2_en gate clock
clk: meson: meson8b: add the vclk_en gate clock
clk: qcom: Fix return value check in apss_ipq6018_probe()
clk: bcm: dvp: Add missing module informations
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
...
- Improve device links cycle detection and breaking. Add more
bindings for device link dependencies.
- Refactor parsing 'no-map' in __reserved_mem_alloc_size()
- Improve DT unittest 'ranges' and 'dma-ranges' test case to check
differing cell sizes
- Various http to https link conversions
- Add a schema check to prevent 'syscon' from being used by itself
without a more specific compatible
- A bunch more DT binding conversions to schema
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Merge tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- Improve device links cycle detection and breaking. Add more bindings
for device link dependencies.
- Refactor parsing 'no-map' in __reserved_mem_alloc_size()
- Improve DT unittest 'ranges' and 'dma-ranges' test case to check
differing cell sizes
- Various http to https link conversions
- Add a schema check to prevent 'syscon' from being used by itself
without a more specific compatible
- A bunch more DT binding conversions to schema
* tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
of: reserved-memory: remove duplicated call to of_get_flat_dt_prop() for no-map node
of: unittest: Use bigger address cells to catch parser regressions
dt-bindings: memory-controllers: Convert mmdc to json-schema
dt-bindings: mtd: Convert imx nand to json-schema
dt-bindings: mtd: Convert gpmi nand to json-schema
dt-bindings: iio: io-channel-mux: Fix compatible string in example code
of: property: Add device link support for pinctrl-0 through pinctrl-8
of: property: Add device link support for multiple DT bindings
dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema
dt-bindings: mux: mux.h: drop a duplicated word
dt-bindings: misc: Convert olpc,xo1.75-ec to json-schema
dt-bindings: aspeed-lpc: Replace HTTP links with HTTPS ones
dt-bindings: drm/bridge: Replace HTTP links with HTTPS ones
drm/tilcdc: Replace HTTP links with HTTPS ones
dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
dt-bindings: fpga: Replace HTTP links with HTTPS ones
dt-bindings: virtio: Replace HTTP links with HTTPS ones
dt-bindings: media: imx274: Add optional input clock and supplies
dt-bindings: i2c-gpio: Use 'deprecated' keyword on deprecated properties
dt-bindings: interrupt-controller: Fix typos in loongson,liointc.yaml
...
There are three SoC families newly dded to the 32-bit and
64-bit Arm architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012. For
now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new ARM SoC support from Arnd Bergmann:
"There are three SoC families newly dded to the 32-bit and 64-bit Arm
architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012.
For now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores"
* tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
ARM: mstar: Correct the compatible string for pmsleep
dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep
dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep
ARM: mstar: Add reboot support
ARM: mstar: Add "pmsleep" node to base dtsi
ARM: mstar: Add PMU
ARM: mstar: Adjust IMI size for infinity3
ARM: mstar: Adjust IMI size for mercury5
ARM: mstar: Adjust IMI size of infinity
ARM: mstar: Add IMI SRAM region
dt-bindings: arm: mstar: Move existing MStar binding descriptions
dt-bindings: arm: mstar: Add binding details for mstar, pmsleep
ARM: mstar: Fix dts filename for 70mai midrive d08
ARM: mstar: Add dts for 70mai midrive d08
ARM: mstar: Add dts for msc313(e) based BreadBee boards
ARM: mstar: Add mercury5 series dtsis
ARM: mstar: Add infinity/infinity3 family dtsis
ARM: mstar: Add Armv7 base dtsi
ARM: mstar: Add binding details for mstar,l3bridge
ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
...
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Make defines for bcm63xx-gate clks to use in DT
- Support gate clks on BCM6318 SoCs
- Add HDMI clks for BCM2711 SoCs
- Support BCM2711 SoC firmware clks
* clk-socfpga:
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
* clk-doc:
clk: Clean up kernel-doc errors
clk: <linux/clk-provider.h>: drop a duplicated word
clk: add function documentation for clk_hw_round_rate()
* clk-qcom: (38 commits)
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
clk: qcom: gcc-sdm660: Add missing modem reset
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gdsc: Add support to enable retention of GSDCR
clk: qcom: Export gdsc_gx_do_nothing_enable() to modules
clk: qcom: Add graphics clock controller driver for SM8250
clk: qcom: Add graphics clock controller driver for SM8150
clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
clk: qcom: gcc: remove unnecessary vco_table from SM8150
clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
clk: qcom: gcc: fix sm8150 GPU and NPU clocks
dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax
...
* clk-vc5:
clk: vc5: use a dedicated struct to describe the output drivers
dt-bindings: clk: versaclock5: convert to yaml
MAINTAINERS: take over IDT VersaClock 5 clock driver
dt-bindings: clk: versaclock5: fix 'idt' prefix typos
clk: vc5: Add memory check to prevent oops
clk: vc5: fix use of memory after it has been kfree'd
clk: vc5: Enable addition output configurations of the Versaclock
dt: Add additional option bindings for IDT VersaClock
clk: vc5: Allow Versaclock driver to support multiple instances
* clk-bcm: (44 commits)
clk: bcm2835: Do not use prediv with bcm2711's PLLs
dt-bindings: arm: bcm: Add a select to the RPI Firmware binding
clk: bcm: dvp: Add missing module informations
clk: bcm: rpi: Remove the quirks for the CPU clock
clk: bcm2835: Don't cache the PLLB rate
clk: bcm2835: Allow custom CCF flags for the PLLs
Revert "clk: bcm2835: remove pllb"
clk: bcm: rpi: Give firmware clocks a name
clk: bcm: rpi: Discover the firmware clocks
clk: bcm: rpi: Add an enum for the firmware clocks
clk: bcm: rpi: Add DT provider for the clocks
clk: bcm: rpi: Make the PLLB registration function return a clk_hw
clk: bcm: rpi: Split pllb clock hooks
clk: bcm: rpi: Rename is_prepared function
clk: bcm: rpi: Pass the clocks data to the firmware function
clk: bcm: rpi: Add clock id to data
clk: bcm: rpi: Create a data structure for the clocks
clk: bcm: rpi: Use CCF boundaries instead of rolling our own
clk: bcm: rpi: Make sure the clkdev lookup is removed
clk: bcm: rpi: Switch to clk_hw_register_clkdev
...
The YAML schemas that landed forgot one clock: "bi_tcxo". Presumably
the bindings were developed against the v4 version of the driver and
when the ".name" was removed in v5 of the driver things broke.
While touching this, add the needed includes in each example. I
believe both examples are supposed to be independent of each other.
Let's fix the bindings.
Fixes: 381cc6f97c ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200731133006.1.Iee81b115f5be50d6d69500fe1bda11bba6e16143@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1595606878-2664-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-9-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-8-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 gpucc bindings.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-7-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20200723074112.3159-4-luca@lucaceresoli.net
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
'idt' is misspelled 'itd' in a few places, fix it.
Fixes: 34662f6e30 ("dt: Add additional option bindings for IDT VersaClock")
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200723074112.3159-2-luca@lucaceresoli.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This add the DT bindings documentation for the Sparx5 SoC DPLL clock
Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992,
MSM8994 (and APQ variants) for clients to vote on.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com
[sboyd@kernel.org: Fixed up binding numbers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk-renesas:
clk: renesas: rzg2: Mark RWDT clocks as critical
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
dt-bindings: clock: renesas: cpg: Convert to json-schema
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Enable CPU clks on Qualcomm MSM8996 SoCs
* clk-qcom:
clk: qcom: Add CPU clock driver for msm8996
dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
soc: qcom: Separate kryo l2 accessors from PMU driver
clk: qcom: Fix return value check in apss_ipq6018_probe()
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1593766185-16346-4-git-send-email-loic.poulain@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Sync dtc to upstream to pick up fixes for I2C bus checks and quiet
warnings
- Various fixes for DT binding check warnings
- A couple of build fixes/improvements for binding checks
- ReST formatting improvements for writing-schema.rst
- Document reference fixes
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Merge tag 'devicetree-fixes-for-5.8-2' into dt/next
Devicetree fixes for v5.8, take 2:
- Sync dtc to upstream to pick up fixes for I2C bus checks and quiet
warnings
- Various fixes for DT binding check warnings
- A couple of build fixes/improvements for binding checks
- ReST formatting improvements for writing-schema.rst
- Document reference fixes
In i.MX8QXP LPCG binding's example, "fsl,imx7d-usdhc" as fallback
compatible is incorrect, remove it to avoid below build error:
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.example.dt.yaml:
mmc@5b010000: compatible: Additional items are not allowed ('fsl,imx7d-usdhc' was unexpected)
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.example.dt.yaml:
mmc@5b010000: compatible: ['fsl,imx8qxp-usdhc', 'fsl,imx7d-usdhc'] is too long
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1592450578-30140-3-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
Nodename should be "mmc" instead of "esdhc" in i.MX35 clock binding
to avoid below build error:
Documentation/devicetree/bindings/clock/imx35-clock.example.dt.yaml:
esdhc@53fb4000: $nodename:0: 'esdhc@53fb4000' does not match '^mmc(@.*)?$'
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1592450578-30140-2-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
- Make defines for bcm63xx-gate clks to use in DT
- Support gate clks on BCM6318 SoCs
- Add HDMI clks for BCM2711 SoCs
- Support BCM2711 SoC firmware clks
* clk-bcm: (42 commits)
clk: bcm: dvp: Add missing module informations
clk: bcm: rpi: Remove the quirks for the CPU clock
clk: bcm2835: Don't cache the PLLB rate
clk: bcm2835: Allow custom CCF flags for the PLLs
Revert "clk: bcm2835: remove pllb"
clk: bcm: rpi: Give firmware clocks a name
clk: bcm: rpi: Discover the firmware clocks
clk: bcm: rpi: Add an enum for the firmware clocks
clk: bcm: rpi: Add DT provider for the clocks
clk: bcm: rpi: Make the PLLB registration function return a clk_hw
clk: bcm: rpi: Split pllb clock hooks
clk: bcm: rpi: Rename is_prepared function
clk: bcm: rpi: Pass the clocks data to the firmware function
clk: bcm: rpi: Add clock id to data
clk: bcm: rpi: Create a data structure for the clocks
clk: bcm: rpi: Use CCF boundaries instead of rolling our own
clk: bcm: rpi: Make sure the clkdev lookup is removed
clk: bcm: rpi: Switch to clk_hw_register_clkdev
clk: bcm: rpi: Remove pllb_arm_lookup global pointer
clk: bcm: rpi: Make sure pllb_arm is removed
...
The VersaClock driver now supports some additional bindings to support
child nodes which can configure optional settings like mode, voltage
and slew.
This patch updates the binding document to describe what is available
in the driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200603154329.31579-2-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add rpm smd clocks, PMIC and bus clocks which are required on
SDM630/660 (and APQ variants) for clients to vote on.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200622090252.36568-1-konradybcio@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53
pll found on ipq6018 devices.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1592800092-20533-2-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add BCM6318 to the binding documentation for the gated clock controllers found
on BCM63xx SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20200610140858.207329-2-noltari@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the possible compatible "rockchip,rk3288w-cru" that handles
the difference between the rk3288 and the new revision rk3288w.
This compatible will be added by bootloaders.
Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200602080644.11333-3-mylene.josserand@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Convert the i.MX7ULP clock binding to DT schema format using json-schema,
the original binding doc is actually for two clock modules(SCG and PCC),
so split it to two binding docs, and the MPLL(mipi PLL) is NOT supposed
to be in clock module, so remove it from binding doc as well.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the Renesas Clock Pulse Generator (CPG) Device Tree
binding documentation to json-schema, combining support for:
- R-Mobile APE6 (R8A73A4) and A1 (R8A7740),
- R-Car M1 (R8A7778) and H1 (R8A7779),
- RZ/A1 (R7S72100),
- SH-Mobile AG5 (SH73A0).
Keep the example for R-Mobile A1, which shows most properties.
Drop the consumer examples, as they do not belong here.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200518081644.23683-1-geert+renesas@glider.be
There's no need to specify 'maxItems' with the same value as the number
of entries in 'items'. A meta-schema update will catch future cases.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Reviewed-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
function that isn't used anymore. Otherwise the main new thing for the common
clk framework is that it is selectable in the Kconfig language now. Hopefully
this will let clk drivers and clk consumers be testable on more than the
architectures that support the clk framework. The goal is to introduce some
Kunit tests for the framework.
Outside of the core framework we have the usual set of various driver updates
and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the
largest addition this time around in terms of lines of code. After that the x86
(Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or
upcoming SoCs. After that the dirstat shows the usual suspects working on their
SoC support by fixing minor bugs, correcting data and converting some of their
DT bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix clock support
on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3
drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on
aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using composite
clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined
bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time around we have four lines of diff in the core framework,
removing a function that isn't used anymore. Otherwise the main new
thing for the common clk framework is that it is selectable in the
Kconfig language now. Hopefully this will let clk drivers and clk
consumers be testable on more than the architectures that support the
clk framework. The goal is to introduce some Kunit tests for the
framework.
Outside of the core framework we have the usual set of various driver
updates and non-critical fixes. The dirstat shows that the new
Baikal-T1 driver is the largest addition this time around in terms of
lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
drivers introduce many lines to support new or upcoming SoCs. After
that the dirstat shows the usual suspects working on their SoC support
by fixing minor bugs, correcting data and converting some of their DT
bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix
clock support on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
clk-pllv3 drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support
aarch32 mode on aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using
composite clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102
defined bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on
Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
clk: mediatek: Remove ifr{0,1}_cfg_regs structures
clk: baikal-t1: remove redundant assignment to variable 'divider'
clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
dt-bindings: clock: Add a missing include to MMP Audio Clock binding
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
clk: clk-si5341: Add support for the Si5345 series
...
The include file for input clock in the example was missing, breaking the
validation.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reported-by: Rob Herring <robh+dt@kernel.org>
Link: https://lore.kernel.org/r/20200605065258.567858-1-lkundrak@v3.sk
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add documentation for the clock bindings of the X1830 Soc from Ingenic.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Rob Herring <robh@kernel.org>
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for Qualcomm's MSM8939 Generic Clock Controller
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
* clk-mmp:
clk: mmp2: Add audio clock controller driver
dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
clk: mmp2: Add support for power islands
dt-bindings: marvell,mmp2: Add ids for the power domains
dt-bindings: clock: Make marvell,mmp2-clock a power controller
clk: mmp2: Add the audio clock
clk: mmp2: Add the I2S clocks
clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
clk: mmp2: Move thermal register defines up a bit
dt-bindings: marvell,mmp2: Add clock id for the Audio clock
dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
clk: mmp: frac: Allow setting bits other than the numerator/denominator
clk: mmp: frac: Do not lose last 4 digits of precision
* clk-intel:
clk: intel: remove redundant initialization of variable rate64
clk: intel: Add CGU clock driver for a new SoC
dt-bindings: clk: intel: Add bindings document & header file for CGU
* clk-ingenic:
clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
clk: X1000: Add FIXDIV for SSI clock of X1000.
dt-bindings: clock: Add and reorder ABI for X1000.
clk: Ingenic: Add CGU driver for X1830.
dt-bindings: clock: Add X1830 clock bindings.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
clk: Ingenic: Remove unnecessary spinlock when reading registers.
* clk-qcom:
clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
clk: qcom: gcc: Add support for Secure control source clock
dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
clk: qcom: gcc: Add support for a new frequency for SC7180
clk: qcom: Add DT bindings for MSM8939 GCC
clk: qcom: gcc: Add missing UFS clocks for SM8150
clk: qcom: gcc: Add GPU and NPU clocks for SM8150
clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
clk: qcom: gdsc: Handle GDSC regulator supplies
clk: qcom: msm8916: Fix the address location of pll->config_reg
* clk-silabs:
clk: clk-si5341: Add support for the Si5345 series
IDT VersaClock 5 5P49V6965 has 5 clock outputs, 4 fractional dividers.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lkml.kernel.org/r/20200404161537.2312297-2-aford173@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
After being gained by the CCU PLLs the signals must be transformed to
be suitable for the clock-consumers. This is done by a set of dividers
embedded into the CCU. A first block of dividers is used to create
reference clocks for AXI-bus of high-speed peripheral IP-cores of the
chip. The second block dividers alter the PLLs output signals to be then
consumed by SoC peripheral devices. Both block DT nodes are ordinary
clock-providers with standard set of properties supported. But in addition
to that each clock provider can be used to reset the corresponding clock
domain. This makes the AXI-bus and System Devices CCU DT nodes to be also
reset-providers.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ru
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Baikal-T1 Clocks Control Unit is responsible for transformation of a
signal coming from an external oscillator into clocks of various
frequencies to propagate them then to the corresponding clocks
consumers (either individual IP-blocks or clock domains). In order
to create a set of high-frequency clocks the external signal is
firstly handled by the embedded into CCU PLLs. So the corresponding
dts-node is just a normal clock-provider node with standard set of
properties. Note as being part of the Baikal-T1 System Controller its
DT node is supposed to be a child the system controller node.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-2-Sergey.Semin@baikalelectronics.ru
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the i.MX8QXP LPCG binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
[robh: add additionalProperties]
Signed-off-by: Rob Herring <robh@kernel.org>
Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent
to the Si5341 family, but with more clock input options (which are not
supported yet by this driver).
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lkml.kernel.org/r/20200507061544.11388-1-mike.looijmans@topic.nl
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the i.MX1 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX21 clock binding to DT schema format using json-schema,
can NOT find any CCM interrupt info from reference manual and DT file,
so interrupts property is removed from original binding doc.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX25 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX27 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX23 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX28 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX31 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX35 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX5 clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX7D clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX6UL clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX6SLL clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX6SL clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX6SX clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the i.MX6Q clock binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
This describes the bindings for a controller that generates master and bit
clocks for the I2S interface.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-13-lkundrak@v3.sk
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This is a binding for the MMP2 power management units. As such apart from
providing the clocks, they also manage the power islands.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-10-lkundrak@v3.sk
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the Renesas Clock Pulse Generator (CPG) Module Stop (MSTP)
Clocks Device Tree binding documentation to json-schema.
Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Replace the obsolete example for R-Car H2 by an example that is still
valid.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200508100321.6720-1-geert+renesas@glider.be
Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
json-schema.
Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200507075026.31941-1-geert+renesas@glider.be
The GPU_GX GDSC depends on both GPU GDSC being enabled and that the
VDD_GX rail is powered, so update the description of the node to cover
these requirements.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20200417070044.1376212-3-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The examples template is a 'simple-bus' with a size of 1 cell for
had between 2 and 4 cells which really only errors on I2C or SPI type
devices with a single cell.
The easiest fix in most cases is to change the 'reg' property to for 1 cell
address and size. In some cases with child devices having 2 cells, that
doesn't make sense so a bus node is needed.
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the ingenic,cgu.txt doc file to ingenic,cgu.yaml.
The binding documentation has been updated as well. The node can have a
child node that corresponds to the USB PHY, which happens to be present
in the middle of the CGU registers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Rob Herring <robh@kernel.org>
Convert the Calxeda clock bindings to DT schema format using json-schema.
This just covers the actual PLL and divider clock nodes. In the actual
DTs they are somewhat unconnected (no ranges or bus compatible) children
of the sregs node, but for the actual clock bindings this is not
relevant.
One oddity is that the addresses are relative to the parent node,
without that being pronounced using a ranges property.
But this is too late to fix now.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
json-schema versions draft7 and earlier have a weird behavior in that
any keywords combined with a '$ref' are ignored (silently). The correct
form was to put a '$ref' under an 'allOf'. This behavior is now changed
in the 2019-09 json-schema spec and '$ref' can be mixed with other
keywords. The json-schema library doesn't yet support this, but the
tooling now does a fixup for this and either way works.
This has been a constant source of review comments, so let's change this
treewide so everyone copies the simpler syntax.
Scripted with ruamel.yaml with some manual fixups. Some minor whitespace
changes from the script.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-By: Vinod Koul <vkoul@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio
Reviewed-by: Stephen Boyd <sboyd@kernel.org> # clock
Signed-off-by: Rob Herring <robh@kernel.org>
Fix various inconsistencies in schema indentation. Most of these are
list indentation which should be 2 spaces more than the start of the
enclosing keyword. This doesn't matter functionally, but affects running
scripts which do transforms on the schema files.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-By: Vinod Koul <vkoul@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The following warnings are seen with 'make dt_binding_check':
Documentation/devicetree/bindings/clock/arm,syscon-icst.example.dts:17.16-24.11: Warning (unit_address_vs_reg): /example-0/clock@00: node has a unit name, but no reg or ranges property
Documentation/devicetree/bindings/clock/arm,syscon-icst.example.dts:17.16-24.11: Warning (unit_address_format): /example-0/clock@00: unit name should not have leading 0s
Fix them by removing the unneeded clock unit name.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This patch adds support for r8a77961 (R-Car M3-W+).
To avoid confusion between R-Car M3-W (R8A77960) and R-Car M3-W+
(R8A77961), this patch also updates the comment of
"renesas,r8a7796-rcar-usb2-clock-sel".
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1585200608-30103-1-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
majority of the diff is the normal collection of driver additions for new SoCs
and non-critical clk data fixes and updates. The framework must be middle aged.
The two biggest directories in the diffstat show that the Qualcomm and Unisoc
support added a handful of big drivers for new SoCs but that's not really the
whole story because those new drivers tend to add large numbers of lines of clk
data. There's a handful of AT91 clk drivers added this time around too and a
bunch of improvements to drivers like the i.MX driver. All around lots of
updates and fixes in various clk drivers which is good to see.
The core framework has only one real major change which has been baking in next
for the past couple months. It fixes the framework so that it stops caching a
clk's phase when the phase clk_op returns an error. Before this change we would
consider some negative errno as a phase and that just doesn't make sense.
Core:
- Don't show clk phase when it is invalid
New Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
Updates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for pll1443x table,
and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need to
change ARM PLL frequency. Thus, we can support core running above
1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate for
getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's not much to see in the core framework this time around.
Instead the majority of the diff is the normal collection of driver
additions for new SoCs and non-critical clk data fixes and updates.
The framework must be middle aged.
The two biggest directories in the diffstat show that the Qualcomm and
Unisoc support added a handful of big drivers for new SoCs but that's
not really the whole story because those new drivers tend to add large
numbers of lines of clk data. There's a handful of AT91 clk drivers
added this time around too and a bunch of improvements to drivers like
the i.MX driver. All around lots of updates and fixes in various clk
drivers which is good to see.
The core framework has only one real major change which has been
baking in next for the past couple months. It fixes the framework so
that it stops caching a clk's phase when the phase clk_op returns an
error. Before this change we would consider some negative errno as a
phase and that just doesn't make sense.
Core:
- Don't show clk phase when it is invalid
New Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and
at91sam9g45 SoCs
Updates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for
pll1443x table, and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need
to change ARM PLL frequency. Thus, we can support core running
above 1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate
for getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for
imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock
Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and
M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits)
clk: sprd: fix to get a correct ibias of pll
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: tegra: Use NULL for pointer initialization
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
...
- Add support for Unisoc SC9863A clks
- GPU GX GDSC support on Qualcomm sc7180
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
* clk-unisoc:
clk: sprd: fix to get a correct ibias of pll
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
* clk-tegra:
clk: tegra: Use NULL for pointer initialization
clk: tegra: Remove audio clocks configuration from clock driver
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
clk: tegra: Remove CLK_M_DIV fixed clocks
clk: tegra: Fix Tegra PMC clock out parents
clk: tegra: Add Tegra OSC to clock lookup
clk: tegra: Add support for OSC_DIV fixed clocks
dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
dt-bindings: tegra: Convert Tegra PMC bindings to YAML
dt-bindings: clock: tegra: Add IDs for OSC clocks
* clk-qcom: (21 commits)
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150
ipq806x: gcc: Added the enable regs and mask for PRNG
clk: qcom: Add modem clock controller driver for SC7180
clk: qcom: gcc: Add support for modem clocks in GCC
dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings
clk: qcom: clk-rpm: add missing rpm clk for ipq806x
clk: qcom: gcc: Add global clock controller driver for SM8250
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
clk: qcom: clk-alpha-pll: Refactor trion PLL
clk: qcom: clk-alpha-pll: Use common names for defines
dt-bindings: clock: rpmcc: Document msm8976 compatible
clk: qcom: smd: Add support for MSM8976 rpm clocks
clk: qcom: clk-rpmh: Wait for completion when enabling clocks
clk: qcom: rpmh: Add support for RPMH clocks on SM8250
dt-bindings: clock: Add RPMHCC bindings for SM8250
clk: qcom: alpha-pll: Make error prints more informative
clk: qcom: gpucc: Add support for GX GDSC for SC7180
...
* clk-imx: (43 commits)
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: imx: clk-gate2: Pass the device to the register function
clk: imx7d: Add PXP clock
clk: imx8mq: A53 core clock no need to be critical
clk: imx8mp: A53 core clock no need to be critical
clk: imx8mm: A53 core clock no need to be critical
clk: imx8mn: A53 core clock no need to be critical
clk: imx: pllv4: use prepare/unprepare
clk: imx: pfdv2: determine best parent rate
clk: imx: pfdv2: switch to use determine_rate
clk: imx: Fix division by zero warning on pfdv2
clk: imx: clk-sscg-pll: Drop unnecessary initialization
clk: imx: pll14xx: Return error if pll type is invalid
clk: imx: imx8mp: fix a53 cpu clock
clk: imx: imx8mn: fix a53 cpu clock
clk: imx: imx8mm: fix a53 cpu clock
clk: imx: imx8mq: fix a53 cpu clock
clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock
clk: imx8mn: Remove unused includes
...
Setting 'additionalProperties: false' is frequently omitted, but is
important in order to check that there aren't extra undocumented
properties in a binding.
Ideally, we'd just add this automatically and make this the default, but
there's some cases where it doesn't work. For example, if a common
schema is referenced, then properties in the common schema aren't part
of what's considered for 'additionalProperties'. Also, sometimes there
are bus specific properties such as 'spi-max-frequency' that go into
bus child nodes, but aren't defined in the child node's schema.
So let's stick with the json-schema defined default and add
'additionalProperties: false' where needed. This will be a continual
review comment and game of wack-a-mole.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Stephen Boyd <sboyd@kernel.org> # clock
Acked-by: Lee Jones <lee.jones@linaro.org>
Numerous schemas are missing 'additionalProperties: false' statements which
ensures a binding doesn't have any extra undocumented properties or child
nodes. Fixing this reveals various missing properties, so let's fix all
those occurrences.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio
Acked-by: Stephen Boyd <sboyd@kernel.org> # clock
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: dri-devel@lists.freedesktop.org
Cc: netdev@vger.kernel.org
Cc: Guillaume La Roque <glaroque@baylibre.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-iio@vger.kernel.org
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-clk@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
Cc: linux-amlogic@lists.infradead.org
Cc: linux-pm@vger.kernel.org
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-gpio@vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: linux-media@vger.kernel.org
Cc: Lee Jones <lee.jones@linaro.org>
Currently the following warning is seen with 'make dt_binding_check':
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml: $id: relative path/filename doesn't match actual path or filename
Fix it by removing the "bindings" directory from the file path.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lkml.kernel.org/r/20200326171933.13394-2-festevam@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Currently the following warning is seen with 'make dt_binding_check':
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml: $id: relative path/filename doesn't match actual path or filename
Fix it by removing the "bindings" directory from the file path.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lkml.kernel.org/r/20200326171933.13394-1-festevam@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
add a new bindings to describe sc9863a clock compatible string.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-4-zhang.lyra@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Only SC9860 clocks were described in sprd.txt, rename it with a SoC
specific name, so that we can add more SoC support.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200304072730.9193-3-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As described above single-output clock provider should have
0 cells number, so let's fix it by using 0 as cells number.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This binding describes the PMUs that are found on MMP3 as well. Add the
compatible strings and adjust the description.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-7-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the fixed-factor-clock binding to DT schema format using
json-schema.
While at that, fix a couple of small errors: make the file base name
match the compatible string, add an example and document the reg-names
property.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200309194254.29009-4-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The ICST clocks used in the ARM Integrator, Versatile and
RealView platforms are updated to use YAML schema, and two
new ICST clocks used by the Integrator IM-PD1 logical module
are added in the process.
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lkml.kernel.org/r/20200219103326.81120-1-linus.walleij@linaro.org
[sboyd@kernel.org: Fix some typos]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Modem Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for GCC MSS and MSS clocks which are required to bring
the modem out of reset.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1584596131-22741-2-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add missing definition of rpm clk for ipq806x soc
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the Renesas Clock Pulse Generator / Module Standby and Software
Reset Device Tree binding documentation to json-schema.
Note that #reset-cells was incorrecty marked a required property for
RZ/A2 before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200303094848.23670-1-geert+renesas@glider.be
Support for MSM8976 was added to the clk-smd-rpm driver: let's
document here the newly added compatible string.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lkml.kernel.org/r/20191031112951.35850-3-kholk11@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds missing required properties of power-domains and resets.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb645 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since the hardware requires to enable both USB 2.0 host and peripheral
functional clock, this patch fixes the documentation.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb645 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1583304137-28482-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fix all the warnings in the DT binding schema examples when built with
'W=1'. This is in preparation to make that the default for examples.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Several DT references got broken due to txt->yaml conversion.
Those are auto-fixed by running:
scripts/documentation-file-ref-check --fix
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Refine i.MX8MN clock binding by removing useless content and
updating the example, it makes all i.MX8M SoCs' clock binding
aligned.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Convert the i.MX8MM clock binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Convert the i.MX8MQ clock binding to DT schema format using json-schema
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- Make of_clk.h self contained
- Fix new qcom DT bindings that just merged to match the DTS files
- Fix qcom clk driver to properly detect DFS clk frequencies
- Fix the ls1028a driver to not deref a pointer before assigning it
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A collection of fixes:
- Make of_clk.h self contained
- Fix new qcom DT bindings that just merged to match the DTS files
- Fix qcom clk driver to properly detect DFS clk frequencies
- Fix the ls1028a driver to not deref a pointer before assigning it"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
of: clk: Make <linux/of_clk.h> self-contained
clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks
clk: qcom: Get rid of the test clock for videocc-sc7180
dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180
clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocks
clk: qcom: Get rid of the test clock for gpucc-sc7180
dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998
clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks
clk: qcom: Get rid of the test clock for dispcc-sc7180
clk: qcom: Get rid of fallback global names for dispcc-sc7180
dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180
clk: qcom: rcg2: Don't crash if our parent can't be found; return an error
clk: ls1028a: fix a dereference of pointer 'parent' before a null check
dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft
clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()
The $id path checks were inadequately checking the path part of the $id
value. With the check fixed, there's a number of errors that need to be
fixed. Most of the errors are including 'bindings/' in the path which
should not be as that is considered the root.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: "Nuno Sá" <nuno.sa@analog.com>
Cc: Jean Delvare <jdelvare@suse.com>
Cc: Stefan Popa <stefan.popa@analog.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
Cc: Marcus Folkesson <marcus.folkesson@gmail.com>
Cc: Kent Gustavsson <kent@minoris.se>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-iio@vger.kernel.org
Cc: linux-input@vger.kernel.org
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
This makes the qcom,videocc bindings match the recent changes to the
dispcc and gpucc.
1. Switched to using "bi_tcxo" instead of "xo".
2. Adds a description for the XO clock. Not terribly important but
nice if it cleanly matches its cousins.
3. Updates the example to use the symbolic name for the RPMH clock and
also show that the real devices are currently using 2 address cells
/ size cells and fixes the spacing on the closing brace.
4. Split into 2 files. In this case they could probably share one
file, but let's be consistent.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lkml.kernel.org/r/20200203103049.v4.11.I27bbd90045f38cd3218c259526409d52a48efb35@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The qcom,gpucc bindings had a few problems with them:
1. When things were converted to yaml the name of the "gpll0 main"
clock got changed from "gpll0" to "gpll0_main". Change it back for
msm8998.
2. Apparently there is a push not to use purist aliases for clocks but
instead to just use the internal Qualcomm names. For sdm845 and
sc7180 (where the drivers haven't already been changed) move in
this direction.
Things were also getting complicated harder to deal with by jamming
several SoCs into one file. Splitting simplifies things.
Fixes: 5c6f3a36b9 ("dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lkml.kernel.org/r/20200203103049.v4.7.I513cd73b16665065ae6c22cf594d8b543745e28c@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The qcom,dispcc bindings had a few problems with them:
1. They didn't specify all the clocks that dispcc is a client of.
Specifically on sc7180 there are two clocks from the DSI PHY and
two from the DP PHY. On sdm845 there are actually two DSI PHYs
(each of which has two clocks) and an extra clock from the gcc.
These all need to be specified.
2. The sdm845.dtsi has existed for quite some time without specifying
the clocks. The Linux driver was relying on global names to match
things up. While we should transition things, it should be noted
in the bindings.
3. The names used the bindings for "xo" and "gpll0" didn't match the
names that QC used for these clocks internally and this was causing
confusion / difficulty with their code generation tools. Switched
to the internal names to simplify everyone's lives. It's not quite
as clean in a purist sense but it should avoid headaches. This
officially changes the binding, but that seems OK in this case.
Also note that I updated the example.
Fixes: 5d28e44ba6 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lkml.kernel.org/r/20200203103049.v4.2.I0c4bbb0f75a0880cd4bd90d8b267271e2375e0d0@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
the normal collection of driver updates to support new SoCs, fix incorrect
data, and convert various drivers to clk_hw based APIs.
In the core, we allow clk_ops::init() to return an error code now so that we
can fail clk registration if the callback does something like fail to allocate
memory. We also add a new "terminate" clk_op so that things done in
clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now
when critical clks fail to enable and we support changing clk rates and
enable/disable state through debugfs when developers compile the kernel
themselves.
On the driver front, we get support for what seems like a lot of Qualcomm and
NXP SoCs given that those vendors dominate the diffstat. There are a couple new
drivers for Xilinx and Amlogic SoCs too. The updates are all small things like
fixing the way glitch free muxes switch parents, avoiding div-by-zero problems,
or fixing data like parent names. See the updates section below for more
details.
Finally, the "basic" clk types have been converted to support specifying
parents with clk_hw pointers. This work includes an overhaul of the fixed-rate
clk type to be more modern by using clk_hw APIs.
Core:
- Let clk_ops::init() return an error code
- Add a clk_ops::terminate() callback to undo clk_ops::init()
- Warn about critical clks that fail to enable or prepare
- Support dangerous debugfs actions on clks with dead code
New Drivers:
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Add a driver for BCLK of Freescale SAI cores
- Add cam, vpe and sgx clock support for TI dra7
- Add aess clock support for TI omap5
- Enable clks for CPUfreq on Allwinner A64 SoCs
- Add Amlogic meson8b DDR clock controller
- Add input clocks to Amlogic meson8b controllers
- Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2
- i.MX8MP clk driver support
Updates:
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs
- Detect more PRMCU variants in ux500 driver
- Adjust the composite clk type to new way of describing clk parents
- Fixes for clk controllers on qcom msm8998 SoCs
- Fix gmac main clock for TI dra7
- Move TI dra7-atl clock header to correct location
- Fix hidden node name dependency on TI clkctrl clocks
- Fix Amlogic meson8b mali clock update using the glitch free mux
- Fix Amlogic pll driver division by zero at init
- Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols
- Switch more i.MX clk drivers to clk_hw based APIs
- Disable non-functional divider between pll4_audio_div and
pll4_post_div on imx6q
- Fix watchdog2 clock name typo in imx7ulp clock driver
- Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs
- Suppress bind attrs for i.MX8M clock driver
- Add a big comment in imx8qxp-lpcg driver to tell why
devm_platform_ioremap_resource() shouldn't be used for the driver
- A correction on i.MX8MN usb1_ctrl parent clock setting
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There are a few changes to the core framework this time around, in
addition to the normal collection of driver updates to support new
SoCs, fix incorrect data, and convert various drivers to clk_hw based
APIs.
In the core, we allow clk_ops::init() to return an error code now so
that we can fail clk registration if the callback does something like
fail to allocate memory. We also add a new "terminate" clk_op so that
things done in clk_ops::init() can be undone, e.g. free memory. We
also spit out a warning now when critical clks fail to enable and we
support changing clk rates and enable/disable state through debugfs
when developers compile the kernel themselves.
On the driver front, we get support for what seems like a lot of
Qualcomm and NXP SoCs given that those vendors dominate the diffstat.
There are a couple new drivers for Xilinx and Amlogic SoCs too. The
updates are all small things like fixing the way glitch free muxes
switch parents, avoiding div-by-zero problems, or fixing data like
parent names. See the updates section below for more details.
Finally, the "basic" clk types have been converted to support
specifying parents with clk_hw pointers. This work includes an
overhaul of the fixed-rate clk type to be more modern by using clk_hw
APIs.
Core:
- Let clk_ops::init() return an error code
- Add a clk_ops::terminate() callback to undo clk_ops::init()
- Warn about critical clks that fail to enable or prepare
- Support dangerous debugfs actions on clks with dead code
New Drivers:
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Add a driver for BCLK of Freescale SAI cores
- Add cam, vpe and sgx clock support for TI dra7
- Add aess clock support for TI omap5
- Enable clks for CPUfreq on Allwinner A64 SoCs
- Add Amlogic meson8b DDR clock controller
- Add input clocks to Amlogic meson8b controllers
- Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2
- i.MX8MP clk driver support
Updates:
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw
based APIs
- Detect more PRMCU variants in ux500 driver
- Adjust the composite clk type to new way of describing clk parents
- Fixes for clk controllers on qcom msm8998 SoCs
- Fix gmac main clock for TI dra7
- Move TI dra7-atl clock header to correct location
- Fix hidden node name dependency on TI clkctrl clocks
- Fix Amlogic meson8b mali clock update using the glitch free mux
- Fix Amlogic pll driver division by zero at init
- Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config
symbols
- Switch more i.MX clk drivers to clk_hw based APIs
- Disable non-functional divider between pll4_audio_div and
pll4_post_div on imx6q
- Fix watchdog2 clock name typo in imx7ulp clock driver
- Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M
SoCs
- Suppress bind attrs for i.MX8M clock driver
- Add a big comment in imx8qxp-lpcg driver to tell why
devm_platform_ioremap_resource() shouldn't be used for the driver
- A correction on i.MX8MN usb1_ctrl parent clock setting"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits)
dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id
clk: ls1028a: Fix warning on clamp() usage
clk: qoriq: add ls1088a hwaccel clocks support
clk: ls1028a: Add clock driver for Display output interface
dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
clk: fsl-sai: new driver
dt-bindings: clock: document the fsl-sai driver
clk: composite: add _register_composite_pdata() variants
clk: qcom: rpmh: Sort OF match table
dt-bindings: fix warnings in validation of qcom,gcc.yaml
dt-binding: fix compilation error of the example in qcom,gcc.yaml
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
clk: zynqmp: Fix divider calculation
clk: zynqmp: Add support for get max divider
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Extend driver for versal
dt-bindings: clock: Add bindings for versal clock driver
clk: ti: clkctrl: Fix hidden dependency to node name
clk: ti: add clkctrl data dra7 sgx
clk: ti: omap5: Add missing AESS clock
...
The 'qcom,gcc.yaml' file failed self-validation (dt_binding_check)
because it required a property to be either (3 entries big),
(3 entries big), or (7 entries big), but not more than one of those
things. That didn't make a ton of sense.
This patch splits all of the exceptional device trees (AKA those that
would have needed if/then/else rules) from qcom,gcc.yaml. It also
cleans up some cruft found while doing that.
After this lands, this worked for me atop clk-next with just the known
error about msm8998:
for f in \
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml \
Documentation/devicetree/bindings/clock/qcom,gcc.yaml; do \
ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=$f; \
done
I then picked this patch atop linux-next (next-20200129) and ran:
# Delete broken yaml:
rm Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
ARCH=arm64 make dt_binding_check | grep 'clock/qcom'
...and that didn't seem to indicate problems.
Arbitrary decisions made (yell if you want changed):
- Left all the older devices (where clocks / clock-names weren't
specified) in a single file.
- Didn't make clocks "required" for msm8996 but left them as listed.
This seems a little weird but it matches the old binding.
Misc cleanups as part of this patch:
- Fixed schema id to not have "bindings/" as per Rob [1].
- Listed include files as per Stephen.
- sm8150 was claimed to be same set of clocks as sc7180, but driver
and dts appear to say that "bi_tcxo_ao" doesn't exist. Fixed.
- In "apq8064", "#thermal-sensor-cells" was missing the "#".
- Got rid of "|" at the end of top description since spacing doesn't
matter.
- Changed indentation to consistently 2 spaces (it was 3 in some
places).
- Added period at the end of protected-clocks description.
- No space before ":".
- Updated sc7180/sm8150 example to use the 'qcom,rpmh.h' include.
- Updated sc7180/sm8150 example to use larger address/size cells as
per reality.
- Updated sc7180/sm8150 example to point to the sleep_clk rather than
<0>.
- Made it so that gcc-ipq8074 didn't require #power-domain-cells since
actual dts didn't have it and I got no hits from:
git grep _GDSC include/dt-bindings/clock/qcom,gcc-ipq8074.h
- Made it so that gcc-qcs404 didn't require #power-domain-cells since
actual dts didn't have it and I got no hits from:
git grep _GDSC include/dt-bindings/clock/qcom,gcc-qcs404.h
Noticed, but not done in this patch (volunteers needed):
- Add "aud_ref_clk" to sm8150 bindings / dts even though I found a
reference to it in "gcc-sm8150.c".
- Fix node name in actual ipq8074 to be "clock-controller" (it's gcc).
- Since the example doesn't need phandes to exist, in msm8998 could
just make up places providing some of the clocks currently bogused
out with <0>.
- On msm8998 clocks are listed as required but current dts doesn't
have them.
[1] https://lore.kernel.org/r/CAL_Jsq+_2E-bAbP9F6VYkWRp0crEyRGa5peuwP58-PZniVny7w@mail.gmail.com
Fixes: ab91f72e01 ("clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20200203094843.v3.1.I4452dc951d7556ede422835268742b25a18b356b@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Having 'bindings' in here causes a warning when checking the schema.
Documentation/devicetree/bindings/clock/fsl,plldig.yaml:
$id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
Remove it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Wen He <wen.he_1@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200203052507.93215-2-sboyd@kernel.org
Acked-by: Rob Herring <robh@kernel.org>
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Fixes for clk controllers on qcom msm8998 SoCs
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Adjust composite clk to new way of describing clk parents
- Add a driver for BCLK of Freescale SAI cores
* clk-imx: (32 commits)
clk: imx: Add support for i.MX8MP clock driver
dt-bindings: imx: Add clock binding doc for i.MX8MP
clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
clk: imx: imx8mq: Switch to clk_hw based API
clk: imx: imx8mm: Switch to clk_hw based API
clk: imx: imx8mn: Switch to clk_hw based API
clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
clk: imx: gate3: Switch to clk_hw based API
clk: imx: add hw API imx_clk_hw_mux2_flags
clk: imx: add imx_unregister_hw_clocks
clk: imx: clk-composite-8m: Switch to clk_hw based API
clk: imx: clk-pll14xx: Switch to clk_hw based API
clk: imx7up: Rename the clks to hws
clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
clk: imx: Rename sccg and frac pll register to suggest clk_hw
clk: imx: imx7ulp composite: Rename to show is clk_hw based
clk: imx: pllv2: Switch to clk_hw based API
clk: imx: pllv1: Switch to clk_hw based API
...
* clk-ti:
clk: ti: clkctrl: Fix hidden dependency to node name
clk: ti: add clkctrl data dra7 sgx
clk: ti: omap5: Add missing AESS clock
clk: ti: dra7: fix parent for gmac_clkctrl
clk: ti: dra7: add vpe clkctrl data
clk: ti: dra7: add cam clkctrl data
dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
* clk-xilinx:
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
clk: zynqmp: Fix divider calculation
clk: zynqmp: Add support for get max divider
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Extend driver for versal
dt-bindings: clock: Add bindings for versal clock driver
* clk-nvidia:
clk: tegra20/30: Explicitly set parent clock for Video Decoder
clk: tegra20/30: Don't pre-initialize displays parent clock
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
clk: tegra: Mark fuse clock as critical
* clk-qcom: (35 commits)
clk: qcom: rpmh: Sort OF match table
dt-bindings: fix warnings in validation of qcom,gcc.yaml
dt-binding: fix compilation error of the example in qcom,gcc.yaml
clk: qcom: Add ipq6018 Global Clock Controller support
clk: qcom: Add DT bindings for ipq6018 gcc clock controller
clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
clk: qcom: rpmh: Add IPA clock for SC7180
clk: qcom: rpmh: skip undefined clocks when registering
clk: qcom: Add video clock controller driver for SC7180
dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
clk: qcom: Add graphics clock controller driver for SC7180
dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
clk: qcom: Add display clock controller driver for SC7180
dt-bindings: clock: Introduce QCOM sc7180 display clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings
clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
clk: qcom: alpha-pll: Remove useless read from set rate
...
* clk-freescale:
clk: fsl-sai: new driver
dt-bindings: clock: document the fsl-sai driver
clk: composite: add _register_composite_pdata() variants
* clk-qoriq:
clk: qoriq: add ls1088a hwaccel clocks support
clk: ls1028a: Add clock driver for Display output interface
dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
- Support dangerous debugfs actions on clks with dead code
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs
* clk-debugfs-danger:
clk: Add support for setting clk_rate via debugfs
* clk-basic-hw:
clk: divider: Add support for specifying parents via DT/pointers
clk: gate: Add support for specifying parents via DT/pointers
clk: mux: Add support for specifying parents via DT/pointers
clk: asm9260: Use parent accuracy in fixed rate clk
clk: fixed-rate: Document that accuracy isn't a rate
clk: fixed-rate: Add clk flags for parent accuracy
clk: fixed-rate: Add support for specifying parents via DT/pointers
clk: fixed-rate: Document accuracy member
clk: fixed-rate: Move to_clk_fixed_rate() to C file
clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
clk: fixed-rate: Convert to clk_hw based APIs
clk: gpio: Use DT way of specifying parents
* clk-renesas:
clk: renesas: Prepare for split of R-Car H3 config symbol
dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
clk: renesas: r7s9210: Add SPIBSC clock
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
clk: renesas: Remove use of ARCH_R8A7796
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
* clk-amlogic:
clk: clarify that clk_set_rate() does updates from top to bottom
clk: meson: meson8b: make the CCF use the glitch-free mali mux
clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
clk: meson: g12a: fix missing uart2 in regmap table
clk: meson: meson8b: use of_clk_hw_register to register the clocks
clk: meson: meson8b: don't register the XTAL clock when provided via OF
clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
dt-bindings: clock: meson8b: add the clock inputs
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
* clk-allwinner:
clk: sunxi: a23/a33: Export the MIPI PLL
clk: sunxi: a31: Export the MIPI PLL
clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
clk: sunxi-ng: r40: Export MBUS clock
clk: sunxi: use of_device_get_match_data
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20191213083402.35678-1-wen.he_1@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The last example in qcom,gcc.yaml set 'sleep' as the second
value of 'clock-names'. According to the schema is should
be 'sleep_clk'. Fix the example to conform the schema.
This fixes a warning when validating the schema:
"clock-names: ... is not valid under any of the given schemas"
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Link: https://lkml.kernel.org/r/20200122135741.12123-1-dafna.hirschfeld@collabora.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Running `make dt_binging_check`, gives the error:
DTC Documentation/devicetree/bindings/clock/qcom,gcc.example.dt.yaml
Error: Documentation/devicetree/bindings/clock/qcom,gcc.example.dts:111.28-29 syntax error
FATAL ERROR: Unable to parse input tree
This is because the last example uses the macro RPM_SMD_XO_CLK_SRC which
is defined in qcom,rpmcc.h but the include of this header is missing.
Add the include to fix the error.
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Link: https://lkml.kernel.org/r/20200122134639.11735-1-dafna.hirschfeld@collabora.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We currently have a hidden dependency to the device tree node name for
the clkctrl clocks. Instead of using standard node name like "clock", we
must use "l4-per-clkctrl" type naming so the clock driver can find the
associated clock domain. Further, if "clk" is specified for a clock node
name, the driver sets TI_CLK_CLKCTRL_COMPAT flag that uses different
logic for the clock name based on the parent node name for the all the
clkctrl clocks for the SoC.
If the clock node naming dependency is not understood, the related
clockdomain is not found, or a wrong one can get used if a clock manager
has multiple clock domains.
As each clkctrl instance represents a single clock domain, let's allow
using domain specific compatible names to specify the clock domain.
This simplifies things and removes the hidden dependency to the node
name. And then later on, after the node names have been standardized,
we can drop the related code for parsing the node names.
Let's also update the binding to use standard "clock" node naming
instead of "clk" and add the missing description for reg.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Most of the clock related dt-binding header files are located in
dt-bindings/clock folder. It would be good to keep all the similar
header files at a single location.
Suggested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
- add DDR clock controller
- GPU OPP updates
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Merge tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.6
- add DDR clock controller
- GPU OPP updates
* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPP
ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPP
ARM: dts: meson8b: fix the clock controller compatible string
ARM: dts: meson8b: add the DDR clock controller
ARM: dts: meson8: add the DDR clock controller
ARM: dts: meson: provide the XTAL clock using a fixed-clock
dt-bindings: clock: meson8b: add the clock inputs
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Link: https://lore.kernel.org/r/7hwo9udi7m.fsf@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
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Merge tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
This is our usual set of DT patches for the Allwinner SoCs.
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
* tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (52 commits)
arm64: dts: allwinner: a64: enable DVFS
arm64: dts: allwinner: a64: add dtsi with CPU operating points
arm64: dts: allwinner: a64: add cooling maps and thermal tripping points
arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodes
arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocks
ARM: dts: sunxi: Use macros for references to CCU clocks
arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 board
ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes
arm64: dts: allwinner: a64: pinebook: Fix lid wakeup
ARM: dts: sun8i: r40: Add device node for CSI0
ARM: dts: sun7i: Add CSI1 controller and pinmux options
ARM: dts: sun4i: Add CSI1 controller and pinmux options
ARM: dts: sunxi: Add missing LVDS resets and clocks
ARM: dts: sun8i: r40: Use tcon top clock index macros
ARM: dts: sun8i: R40: Add PMU node
ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K
arm64: dts: allwinner: h6: Add thermal sensor and thermal zones
ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 board
arm64: dts: allwinner: a64: Add MIPI DSI pipeline
arm64: dts: allwinner: a64: Add thermal sensors and thermal zones
...
Link: https://lore.kernel.org/r/20200113095555.GA29848@wens.csie.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the clock binding doc for i.MX8MP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the
SoC. Update the definition of these clocks to allow this to be wired up
to the appropriate clock source.
Retain "xo" as the global named parent to make the change a nop in the
event that DT doesn't carry the necessary clocks definition.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1577428714-17766-6-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The VIDEOCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1577428714-17766-5-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1577428714-17766-3-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Indicate sc7180 in commit subject]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The GPUCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1577428714-17766-2-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Allwinner SoCs have a legacy set of bindings (and a framework to
support it in Linux) for their clock controllers.
Now that we have the DT validation in place, let's split into separate file
and convert the device tree bindings for those clocks to schemas, and mark
them all as deprecated.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Rob Herring <robh@kernel.org>
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812245-23827-3-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Add sc7180 to subject]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The DISPCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812245-23827-2-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the qcom,mmcc-X clock controller binding to DT schema. Add the
protected-clocks property to the schema to show that is it explicitly
allowed, instead of relying on the generic, pre-schema binding.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1576596003-10093-1-git-send-email-jhugo@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The global clock controller on MSM8998 can consume a number of external
clocks. Document them.
For 7180 and 8150, the hardware always exists, so no clocks are truly
optional. Therefore, simplify the binding by removing the min/max
qualifiers to clocks. Also, fixup an example so that dt_binding_check
passes.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1576595987-10043-1-git-send-email-jhugo@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the STM32MP1 RCC binding to DT schema format using json-schema.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The Allwinner A80 SoC has a display clocks controller that is supported in
Linux, with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Allwinner A80 SoC has a USB clocks controller that is supported in
Linux, with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The newer Allwinner SoCs have a DE2 clocks controller that is supported in
Linux, with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
While my email address has changed for a while, all the schemas I
contributed still have the old one unfortunately. Update it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Rob Herring <robh@kernel.org>
The clock controller on Meson8/Meson8b/Meson8m2 has three (known)
inputs:
- "xtal": the main 24MHz crystal
- "ddr_pll": some of the audio clocks use the output of the DDR PLL as
input
- "clk_32k": an optional clock signal which can be connected to GPIOAO_6
(which then has to be switched to the CLK_32K_IN function)
Add the inputs to the documentation so we can wire up these inputs in a
follow-up patch.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in
the MMCBUS registers. There is no public documentation on this, but the
GPL u-boot sources from the Amlogic BSP show that:
- it uses the same XTAL input as the main clock controller
- it contains a PLL which seems to be implemented just like the other
PLLs in this SoC
- there is a power-of-two PLL post-divider
Add the documentation and header file for this DDR clock controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
- DT schemas for PWM, syscon, power domains, SRAM, syscon-reboot,
syscon-poweroff, renesas-irqc, simple-pm-bus, renesas-bsc, pwm-rcar,
Renesas tpu, at24 eeprom, rtc-sh, Allwinner PS/2, sharp,ld-d5116z01b
panel, Arm SMMU, max77650, Meson CEC, Amlogic canvas and DWC3 glue,
Allwinner A10 mUSB and CAN, TI Davinci MDIO, QCom QCS404 interconnect,
Unisoc/Spreadtrum SoCs and UART
- Convert a bunch of Samsung bindings to DT schema
- Convert a bunch of ST stm32 bindings to DT schema
- Realtek and Exynos additions to Arm Mali bindings
- Fix schema errors in RiscV CPU schema
- Various schema fixes from improved meta-schema checks
- Improve the handling of 'dma-ranges' and in particular fix DMA mask
setup on PCI bridges
- Fix a memory leak in add_changeset_property() and DT unit tests.
- Several documentation improvements for schema validation
- Rework build rules to improve schema validation errors
- Color output for dtx_diff
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Merge tag 'devicetree-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- DT schemas for PWM, syscon, power domains, SRAM, syscon-reboot,
syscon-poweroff, renesas-irqc, simple-pm-bus, renesas-bsc, pwm-rcar,
Renesas tpu, at24 eeprom, rtc-sh, Allwinner PS/2, sharp,ld-d5116z01b
panel, Arm SMMU, max77650, Meson CEC, Amlogic canvas and DWC3 glue,
Allwinner A10 mUSB and CAN, TI Davinci MDIO, QCom QCS404
interconnect, Unisoc/Spreadtrum SoCs and UART
- Convert a bunch of Samsung bindings to DT schema
- Convert a bunch of ST stm32 bindings to DT schema
- Realtek and Exynos additions to Arm Mali bindings
- Fix schema errors in RiscV CPU schema
- Various schema fixes from improved meta-schema checks
- Improve the handling of 'dma-ranges' and in particular fix DMA mask
setup on PCI bridges
- Fix a memory leak in add_changeset_property() and DT unit tests.
- Several documentation improvements for schema validation
- Rework build rules to improve schema validation errors
- Color output for dtx_diff
* tag 'devicetree-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (138 commits)
libfdt: define INT32_MAX and UINT32_MAX in libfdt_env.h
dt-bindings: arm: Remove leftover axentia.txt
of: unittest: fix memory leak in attach_node_and_children
of: overlay: add_changeset_property() memory leak
dt-bindings: interrupt-controller: arm,gic-v3: Add missing type to interrupt-partition-* nodes
dt-bindings: firmware: ixp4xx: Drop redundant minItems/maxItems
dt-bindings: power: Rename back power_domain.txt bindings to fix references
dt-bindings: i2c: stm32: Migrate i2c-stm32 documentation to yaml
dt-bindings: mtd: Convert stm32 fmc2-nand bindings to json-schema
dt-bindings: remoteproc: convert stm32-rproc to json-schema
dt-bindings: mailbox: convert stm32-ipcc to json-schema
dt-bindings: mfd: Convert stm32 low power timers bindings to json-schema
dt-bindings: interrupt-controller: Convert stm32-exti to json-schema
dt-bindings: crypto: Convert stm32 HASH bindings to json-schema
dt-bindings: rng: Convert stm32 RNG bindings to json-schema
dt-bindings: pwm: Convert Samsung PWM bindings to json-schema
dt-bindings: pwm: Convert PWM bindings to json-schema
dt-bindings: serial: Add a new compatible string for SC9863A
dt-bindings: serial: Convert sprd-uart to json-schema
dt-bindings: arm: Add bindings for Unisoc SC9863A
...
- Support CGU in Ingenix X1000
- Support Bitmain BM1880 clks
* clk-ingenic:
clk: ingenic: Allow drivers to be built with COMPILE_TEST
clk: Ingenic: Add CGU driver for X1000.
dt-bindings: clock: Add X1000 bindings.
* clk-init-leak:
clk: mark clk_disable_unused() as __init
clk: Fix memory leak in clk_unregister()
* clk-ux500:
MAINTAINERS: Update section for Ux500 clock drivers
* clk-bitmain:
MAINTAINERS: Add entry for BM1880 SoC clock driver
clk: Add common clock driver for BM1880 SoC
dt-bindings: clock: Add devicetree binding for BM1880 SoC
clk: Add clk_hw_unregister_composite helper function definition
clk: Zero init clk_init_data in helpers
Convert Generic Power Domain bindings to DT schema format using
json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Link: https://lkml.kernel.org/r/1573378102-72380-2-git-send-email-zhouyanjie@zoho.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The RPMHCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1572371299-16774-2-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20191014102308.27441-5-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Reword subject to make sc7180 specific, sort
compatible]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20191014102308.27441-4-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add DT binding documentation for the Clock Pulse Generator / Module
Standby and Software Reset block in the Renesas R-Car M3-W+ (R8A77961)
SoC.
Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to
avoid confusion between R-Car M3-W (R8A77960) and M3-W+.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122941.12342-2-geert+renesas@glider.be
As of commit 362b334b17 ("ARM: dts: r8a7791: Convert to new
CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files
use the unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
Hence remove the old R-Car Gen2 DT bindings describing a hierarchical
representation of the various CPG and MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191016145207.29779-1-geert+renesas@glider.be
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add devicetree binding for the Q6SSTOP clock controller found in QCS404.
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Link: https://lkml.kernel.org/r/20191011132928.9388-2-govinds@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the compatible and clock ids of the sm1 audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The px30 contains 2 separate clock controllers the regular cru creating
most clocks as well as the pmucru managing the GPLL and some other clocks.
The gpll of course also is needed by the cru, so while we normally do rely
on clock names to associate clocks getting probed later on (for example
xin32k coming from an i2c device in most cases) it is safer to declare the
explicit dependency between the two crus. This makes sure that for example
the clock-framework probes them in the correct order from the start.
The assigned-clocks properties were simply working by chance in the past
so split them accordingly to the 2 crus to honor the loading direction.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20190917082659.25549-9-heiko@sntech.de
Add a reference to the missing PCIe clock managed by this IP. The
clock resides in the south bridge.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20190627125245.26788-5-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk registration by clk providers and debugfs "nice to haves" for rate
constraints. I'll highlight that we're now setting the clk_init_data pointer
inside struct clk_hw to NULL during clk_register(), which may break some
drivers that thought they could use that pointer during normal operations. That
change has been sitting in next for a while now but maybe something is still
broken. We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.
On the clk driver side we got the usual addition of new SoC support, new
features for existing drivers, and bug fixes scattered throughout. The biggest
diffstat is the Amlogic driver that gained CPU clk support in addition to
migrating to the new way of specifying clk parents. After that the Qualcomm,
i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and
clock controllers from those vendors.
Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregistered
New Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCs
Updates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a small collection of core framework updates this time, mostly
around clk registration by clk providers and debugfs "nice to haves"
for rate constraints. I'll highlight that we're now setting the
clk_init_data pointer inside struct clk_hw to NULL during
clk_register(), which may break some drivers that thought they could
use that pointer during normal operations. That change has been
sitting in next for a while now but maybe something is still broken.
We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.
On the clk driver side we got the usual addition of new SoC support,
new features for existing drivers, and bug fixes scattered throughout.
The biggest diffstat is the Amlogic driver that gained CPU clk support
in addition to migrating to the new way of specifying clk parents.
After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
support for various new SoCs and clock controllers from those vendors.
Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregistered
New Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCs
Updates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: Drop !clk checks in debugfs dumping
clk: imx: imx8mn: fix pll mux bit
clk: imx: imx8mm: fix pll mux bit
clk: imx: clk-pll14xx: unbypass PLL by default
clk: imx: pll14xx: avoid glitch when set rate
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: sprd: add missing kfree
clk: at91: allow 24 Mhz clock as input for PLL
clk: Make clk_bulk_get_all() return a valid "id"
clk: actions: Fix factor clk struct member access
clk: qcom: rcg: Return failure for RCG update
clk: remove extra ---help--- tags in Kconfig
clk: add include guard to clk-conf.h
...
- Support qcom SM8150 RPMh clks
- Set floor ops for qcom sd clks
- Support qcom QCS404 WCSS clks
- Support for Mediatek MT6779 SoCs
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
* clk-qcom:
clk: qcom: rcg: Return failure for RCG update
clk: qcom: fix QCS404 TuringCC regmap
clk: qcom: clk-rpmh: Add support for SM8150
dt-bindings: clock: Document SM8150 rpmh-clock compatible
clk: qcom: clk-rpmh: Convert to parent data scheme
dt-bindings: clock: Document the parent clocks
clk: qcom: gcc: Use floor ops for SDCC clocks
clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
clk: qcom: define probe by index API as common API
clk: qcom: Add WCSS gcc clock control for QCS404
clk: qcom: msm8916: Don't build by default
clk: qcom: gcc: Add global clock controller driver for SM8150
dt-bindings: clock: Document gcc bindings for SM8150
clk: qcom: clk-alpha-pll: Add support for Trion PLLs
clk: qcom: clk-alpha-pll: Remove post_div_table checks
clk: qcom: clk-alpha-pll: Remove unnecessary cast
* clk-mtk:
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
clk: mediatek: Register clock gate with device
clk: mediatek: add pericfg clocks for MT8183
dt-bindings: clock: mediatek: add pericfg for MT8183
clk: mediatek: Add MT6779 clock support
clk: mediatek: Add dt-bindings for MT6779 clocks
dt-bindings: mediatek: bindings for MT6779 clk
clk: reset: Modify reset-controller driver
* clk-armada:
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: mvebu: ap806: Fix clock name for the cluster
clk: mvebu: add CPU clock driver for Armada 7K/8K
clk: mvebu: add helper file for Armada AP and CP clocks
dt-bindings: ap806: add the cluster clock node in the syscon file
* clk-ingenic:
clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
* clk-meson: (23 commits)
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
clk: meson: g12a: add support for SM1 GP1 PLL
dt-bindings: clk: meson: add sm1 periph clock controller bindings
clk: meson: axg-audio: add g12a reset support
dt-bindings: clock: meson: add resets to the audio clock controller
clk: meson: g12a: expose CPUB clock ID for G12B
clk: meson: g12a: add notifiers to handle cpu clock change
clk: meson: add g12a cpu dynamic divider driver
clk: core: introduce clk_hw_set_parent()
clk: meson: remove clk input helper
clk: meson: remove ee input bypass clocks
clk: meson: clk-regmap: migrate to new parent description method
clk: meson: meson8b: migrate to the new parent description method
clk: meson: axg: migrate to the new parent description method
clk: meson: gxbb: migrate to the new parent description method
clk: meson: g12a: migrate to the new parent description method
clk: meson: remove ao input bypass clocks
clk: meson: axg-aoclk: migrate to the new parent description method
clk: meson: gxbb-aoclk: migrate to the new parent description method
...
The new BCM2711 supports an additional clock for the emmc2 block.
So we need an additional compatible.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
With clock parent data scheme we must specify the parent clocks for the
rpmhcc nodes. So describe the parent clock for rpmhcc in the bindings.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-2-vkoul@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
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Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8qxp: Add DSP DT node
arm64: dts: imx8mn: Add cpu-freq support
arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
arm64: dts: imx8mn: Add gpio-ranges property
arm64: dts: freescale: Add i.MX8MN dtsi support
clk: imx8: Add DSP related clocks
clk: imx: Add support for i.MX8MN clock driver
clk: imx: Add API for clk unregister when driver probe fail
clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
dt-bindings: imx: Add clock binding doc for i.MX8MN
Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.
SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Rename the device tree clock bindings for Renesas EMMA Mobile EV2
from emev2-clock.txt to renesas,emev2-smu.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the documentation and bindings for the resets provided by the g12a
audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Document the global clock controller found on SM8150.
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and add external clocks
split binding to this patch]]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The path in the schema '$id' value is wrong. Fix it.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-clk@vger.kernel.org
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
side. The two main highlights in the core framework are the addition of an bulk
clk_get API that handles optional clks and an extra debugfs file that tells the
developer about the current parent of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is mostly
because that SoC has started converting to the clk_hw style of clk
registration. The next big update is in the Amlogic meson clk driver that
gained some support for audio, cpu, and temperature clks while fixing some PLL
issues. Finally, the biggest thing that stands out is the conversion of a large
part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
less strings and more pointer comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks here and
there to clk data along with the normal addition of a handful of new drivers
and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
- Support gated clk controller on MIPS based BCM63XX SoCs
- Small frequency support for SiLabs Si544 chips
- Support SiLabs Si5341 and Si5340 chips
* clk-bcm63xx:
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
* clk-silabs:
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
* clk-lochnagar:
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: lochnagar: Use new parent_data approach to register clock parents
* clk-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
- Support for CPU clks on Raspberry Pi devices
- Slow clk support for AT91 SAM9X60 SoCs
* clk-rpi-cpufreq:
clk: raspberrypi: register platform device for raspberrypi-cpufreq
firmware: raspberrypi: register clk device
clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
clk: bcm2835: remove pllb
* clk-tegra:
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
clk: tegra: Warn if an enabled PLL is in IDDQ
clk: tegra: Do not warn unnecessarily
clk: tegra210: fix PLLU and PLLU_OUT1
* clk-simplify-provider.h:
clk: consoldiate the __clk_get_hw() declarations
clk: Unexport __clk_of_table
clk: Remove ifdef for COMMON_CLK in clk-provider.h
* clk-sprd:
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: sprd: Check error only for devm_regmap_init_mmio()
clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
* clk-at91:
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: at91: sckc: add support for SAM9X60
dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
clk: at91: sckc: add support to specify registers bit offsets
clk: at91: sckc: sama5d4 has no bypass support
* clk-ti:
clk: ti: Use int to check return value from of_property_count_elems_of_size()
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: probe clocks from DT instead of firmware
clk: keystone: sci-clk: split out the fw clock parsing to own function
clk: keystone: sci-clk: cut down the clock name length
* clk-samsung:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
* clk-imx: (38 commits)
clk: imx8mq: Keep uart clocks on during system boot
clk: imx: Remove __init for imx_register_uart_clocks() API
clk: imx6q: fix section mismatch warning
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
clk: imx8mq: Use imx_check_clocks() API directly
clk: imx: Remove __init for imx_check_clocks() API
clk: imx6sll: Switch to clk_hw based API
clk: imx7d: Switch to clk_hw based API
clk: imx6ul: Switch to clk_hw based API
clk: imx6sx: Switch to clk_hw based API
clk: imx6q: Switch to clk_hw based API
clk: imx6sl: Switch to clk_hw based API
clk: imx: Switch wrappers to clk_hw based API
clk: imx: clk-fixup-mux: Switch to clk_hw based API
clk: imx: clk-fixup-div: Switch to clk_hw based API
clk: imx: clk-gate-exclusive: Switch to clk_hw based API
clk: imx: clk-pfd: Switch to clk_hw based API
clk: imx: clk-pllv3: Switch to clk_hw based API
clk: imx: clk-gate2: Switch to clk_hw based API
clk: imx: clk-cpu: Switch to clk_hw based API
...
* clk-allwinner: (29 commits)
clk: Simplify debugfs printing and add a newline
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
...
This clock was missed when the binding was initially merged but is
supported by the driver, so add it to the binding document.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Adds the devicetree bindings for the Si5341 and Si5340 chips from
Silicon Labs. These are multiple-input multiple-output clock
synthesizers.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add binding documentation for the gated clock controller found on MIPS
based BCM63XX SoCs.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add compatible string for the core clock on the 98dx1135 switch with
integrated CPU.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Update the documentation to support clock driver for the Amlogic G12B SoC.
G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The GPU for msm8998 has its own clock controller. Document it.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Allwinner SoCs have a clocks controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.
Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
These files were converted to json-schema, but the references weren't
renamed.
Fixes: 66ed144f14 ("dt-bindings: interrupt-controller: Convert ARM GIC to json-schema")
(and other similar commits)
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Support for Cirrus Logic Lochnagar clks
* clk-hisi:
clk: hi3660: Mark clk_gate_ufs_subsys as critical
* clk-lochnagar:
clk: lochnagar: Add support for the Cirrus Logic Lochnagar
clk: lochnagar: Add initial binding documentation
* clk-allwinner:
clk: sunxi-ng: sun5i: Export the MBUS clock
clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
clk: sunxi-ng: h6: Preset hdmi-cec clock parent
clk: sunxi: Add Kconfig options
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
clk: sunxi-ng: Allow DE clock to set parent rate
* clk-rockchip:
clk: rockchip: undo several noc and special clocks as critical on rk3288
clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
clk: rockchip: Limit use of USB PHY clock to USB on rk3288
clk: rockchip: Fix video codec clocks on rk3288
clk: rockchip: Make rkpwm a critical clock on rk3288
clk: rockchip: fix wrong clock definitions for rk3328
* clk-qoriq:
clk: qoriq: increase array size of cmux_to_group
dt-bindings: qoriq-clock: Add ls1028a chip compatible string
clk: qoriq: Add ls1028a clock configuration
clk: qoriq: add more PLL divider clocks support
dt-bindings: qoriq-clock: add more PLL divider clocks support
- Remove clk_readl() and introduce BE versions of basic clk types
* clk-doc:
clk: Drop duplicate clk_register() documentation
clk: Document and simplify clk_core_get_rate_nolock()
clk: Remove 'flags' member of struct clk_fixed_rate
clk: nxp: Drop 'flags' on fixed_rate clk macro
clk: Document __clk_mux_determine_rate()
clk: Document CLK_MUX_READ_ONLY mux flag
clk: Document deprecated things
clk: Collapse gpio clk kerneldoc
* clk-more-critical:
clk: highbank: Convert to CLK_IS_CRITICAL
* clk-meson: (21 commits)
clk: meson: axg-audio: add g12a support
clk: meson: axg-audio: don't register inputs in the onecell data
clk: meson: axg_audio: replace prefix axg by aud
dt-bindings: clk: axg-audio: add g12a support
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
dt-bindings: clock: meson8b: export the video decoder clocks
clk: meson-g12a: add video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
clk: meson-g12a: add PCIE PLL clocks
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
dt-bindings: clock: meson8b: drop the "ABP" clock definition
clk: meson: g12a: add cpu clocks
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
...
* clk-basic-be:
clk: core: replace clk_{readl,writel} with {readl,writel}
clk: core: remove powerpc special handling
powerpc/512x: mark clocks as big endian
clk: mux: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: gate: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: divider: add explicit big endian support
Add DT binding documentation for the Linux driver for the SiFive
PRCI clock & reset control IP block, as found on the SiFive
FU540 chip.
This version includes changes requested by Stephen Boyd
<sboyd@kernel.org> and Rob Herring <robh@kernel.org>, and
fixes some errors in the initial version.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Megan Wachs <megan@sifive.com>
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocks
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Remove the need for child nodes in the sckc binding to be able to remove
dtc warnings and have a more modern binding.
Also document optional properties.
Cc: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the board
controller chip on the Lochnagar board.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devicetree binding for the turing clock controller found in QCS404.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add a new compatible string and additional clock ids for audio clock
controller of the g12a SoC family.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190329160649.31603-2-jbrunet@baylibre.com
Clock description is part of firmware doc. Move clock description
in separate doc.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
updates this time around. It's the usual pile of new drivers for new
hardware out there and the normal small fixes and updates, but then we
have some core framework changes too.
In the core framework, we introduce support for a clk_get_optional() API
to get clks that may not always be populated and a way to devm manage clkdev
lookups registered by provider drivers. We also do some refactoring to simplify
the interface between clkdev and the common clk framework so we can reuse the DT
parsing and clk_get() path in provider drivers in the future. This work will
continue in the next few cycles while we convert how providers specify clk
parents.
On the driver side, the biggest part of the dirstat is the Amlogic clk driver
that got support for the G12A SoC. It dominates with almost half the overall
diff, while the second largest part of the diff is in the i.MX clk driver
that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor
and Qualcomm drivers rounding out the big part of the dirstat because they both
got new hardware support for SoCs. The rest is just various updates and non-critical
fixes for existing drivers.
Core:
- Convert a few clk bindings to JSON schema format
- Add a {devm_}clk_get_optional() API
- Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
- Start rewriting clk parent registration and supporting device links
by moving around code that supports clk_get() and DT parsing of the
'clocks' property
New Drivers:
- Add Qualcomm MSM8998 RPM managed clks
- IPA clk support on Qualcomm RPMh clk controllers
- Actions Semi S500 SoC clk support
- Support for fixed rate clks populated from an MMIO register
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
- Add TMU (timer) clocks on Renesas RZ/G2E
- Add Amlogic G12A Always-On Clock Controller
- Add 32k clock generation for Amlogic AXG
- Add support for the Mali GPU clocks on Amlogic Meson8
- Add Amlogic G12A EE clock controller driver
- Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
- Add i.MX8MM SoC clk driver support
Removed Drivers:
- Remove clps711x driver as the board support is gone
Updates:
- 3rd ECO fix for Mediatek MT2712 SoCs
- Updates for Qualcomm MSM8998 GCC clks
- Random static analysis fixes for clk drivers
- Support for sleeping gpios in the clk-gpio type
- Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
- Split LCDC into two clks on the Marvell MMP2 SoC
- Various DT of_node refcount fixes
- Get rid of CLK_IS_BASIC from TI code (yay!)
- TI Autoidle clk support
- Fix Amlogic Meson8 APB clock ID name
- Claim input clocks through DT for Amlogic AXG and GXBB
- Correct the DU (display unit) parent clock on Renesas RZ/G2E
- Exynos5433 IMEM CMU crypto clk support (SlimSS)
- Fix for the PLL-MIPI on the Allwinner A23
- Fix Rockchip rk3328 PLL rate calculation
- Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
- i.MX SCU clk driver clk_set_parent() and cpufreq support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk subsystem updates from Stephen Boyd:
"We have a fairly balanced mix of clk driver updates and clk framework
updates this time around. It's the usual pile of new drivers for new
hardware out there and the normal small fixes and updates, but then we
have some core framework changes too.
In the core framework, we introduce support for a clk_get_optional()
API to get clks that may not always be populated and a way to devm
manage clkdev lookups registered by provider drivers. We also do some
refactoring to simplify the interface between clkdev and the common
clk framework so we can reuse the DT parsing and clk_get() path in
provider drivers in the future. This work will continue in the next
few cycles while we convert how providers specify clk parents.
On the driver side, the biggest part of the dirstat is the Amlogic clk
driver that got support for the G12A SoC. It dominates with almost
half the overall diff, while the second largest part of the diff is in
the i.MX clk driver that gained support for imx8mm SoCs. After that,
we have the Actions Semiconductor and Qualcomm drivers rounding out
the big part of the dirstat because they both got new hardware support
for SoCs. The rest is just various updates and non-critical fixes for
existing drivers.
Core:
- Convert a few clk bindings to JSON schema format
- Add a {devm_}clk_get_optional() API
- Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
- Start rewriting clk parent registration and supporting device links
by moving around code that supports clk_get() and DT parsing of the
'clocks' property
New Drivers:
- Add Qualcomm MSM8998 RPM managed clks
- IPA clk support on Qualcomm RPMh clk controllers
- Actions Semi S500 SoC clk support
- Support for fixed rate clks populated from an MMIO register
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
- Add TMU (timer) clocks on Renesas RZ/G2E
- Add Amlogic G12A Always-On Clock Controller
- Add 32k clock generation for Amlogic AXG
- Add support for the Mali GPU clocks on Amlogic Meson8
- Add Amlogic G12A EE clock controller driver
- Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
- Add i.MX8MM SoC clk driver support
Removed Drivers:
- Remove clps711x driver as the board support is gone
Updates:
- 3rd ECO fix for Mediatek MT2712 SoCs
- Updates for Qualcomm MSM8998 GCC clks
- Random static analysis fixes for clk drivers
- Support for sleeping gpios in the clk-gpio type
- Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
- Split LCDC into two clks on the Marvell MMP2 SoC
- Various DT of_node refcount fixes
- Get rid of CLK_IS_BASIC from TI code (yay!)
- TI Autoidle clk support
- Fix Amlogic Meson8 APB clock ID name
- Claim input clocks through DT for Amlogic AXG and GXBB
- Correct the DU (display unit) parent clock on Renesas RZ/G2E
- Exynos5433 IMEM CMU crypto clk support (SlimSS)
- Fix for the PLL-MIPI on the Allwinner A23
- Fix Rockchip rk3328 PLL rate calculation
- Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
- i.MX SCU clk driver clk_set_parent() and cpufreq support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT
clk: fixup default index for of_clk_get_by_name()
clk: Move of_clk_*() APIs into clk.c from clkdev.c
clk: Inform the core about consumer devices
clk: Introduce of_clk_get_hw_from_clkspec()
clk: core: clarify the check for runtime PM
clk: Combine __clk_get() and __clk_create_clk()
clk: imx8mq: add GPIO clocks to clock tree
clk: mediatek: correct cpu clock name for MT8173 SoC
clk: imx: Refactor entire sccg pll clk
clk: imx: scu: add cpu frequency scaling support
clk: mediatek: Mark bus and DRAM related clocks as critical
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Add MUX_FLAGS macro
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
clk: ingenic: Remove set but not used variable 'enable'
clk: at91: programmable: remove unneeded register read
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
clk: mediatek: add MUX_GATE_FLAGS_2
...
- Split LCDC into two clks on the Marvell MMP2 SoC
* clk-imx:
clk: imx8mq: add GPIO clocks to clock tree
clk: imx: Refactor entire sccg pll clk
clk: imx: scu: add cpu frequency scaling support
clk: imx: imx8mm: Mark init function __init
clk: imx8mq: Add the missing ARM clock
dt-bindings: imx8mq-clock: Add the missing ARM clock
clk: imx: imx8mq: Fix the rate propagation for arm pll
clk: imx8mq: Add support for the CLKO1 clock
clk: imx8mq: Fix the CLKO2 source select list
clk: imx8mq: Add missing M4 clocks
clk: imx: Add clock driver support for imx8mm
dt-bindings: imx: Add clock binding doc for imx8mm
clk: imx: Add PLLs driver for imx8mm soc
clk: imx5: add imx5_SCC2_IPG_GATE
clk: imx: scu: add set parent support
clk: imx: scu: add fallback compatible string support
clk: imx8mq: Make parent names arrays const pointers
clk: imx: Make parents const pointer in mux wrappers
clk: imx: Make parent_names const pointer in composite-8m
* clk-samsung:
clk: samsung: s3c2443: Mark expected switch fall-through
clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override
clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure
clk: samsung: exynos5433: Add selected IMEM clocks
clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU
clk: samsung: exynos5433: Fix name typo in sssx
clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs
* clk-ti:
clk: clk-twl6040: Fix imprecise external abort for pdmclk
ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that
clk: ti: check clock type before doing autoidle ops
clk: ti: add a usecount for autoidle
clk: ti: generalize the init sequence of clk_hw_omap clocks
clk: ti: remove usage of CLK_IS_BASIC
clk: ti: add new API for checking if a provided clock is an OMAP clock
clk: ti: move clk_hw_omap list handling under generic part of the driver
* clk-uniphier-gear:
clk: uniphier: Fix update register for CPU-gear
* clk-mmp2-lcdc:
clk: mmp2: separate LCDC peripheral clk form the display clock
dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
Add the clock binding doc for i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This contains device tree binding updates for CPU frequency scaling on
Tegra210, BPMP support on Tegra210 and support for NVIDIA Shield TV.
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Merge tag 'tegra-for-5.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
dt-bindings: tegra: Changes for v5.1-rc1
This contains device tree binding updates for CPU frequency scaling on
Tegra210, BPMP support on Tegra210 and support for NVIDIA Shield TV.
* tag 'tegra-for-5.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties
dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties
dt-bindings: clock: tegra124-dfll: add Tegra210 support
dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator
dt-bindings: firmware: tegra186-bpmp: Remove name property
dt-bindings: firmware: Add bindings for Tegra210 BPMP
dt-bindings: tegra: Add Shield TV device tree binding documentation
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Tegra210 support for DFLL clock.
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add new properties to configure the DFLL PWM regulator support.
Cc: devicetree@vger.kernel.org
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the g12a SoC
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-3-jbrunet@baylibre.com
Convert the fixed-factor-clock binding to DT schema format using
json-schema.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Drop full stop on title]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert the fixed-clock binding to DT schema format using json-schema.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Drop full stop on title]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds a DT binding documentation for Fixed
Memory Mapped IO clocks.
Signed-off-by: Jan Kotas <jank@cadence.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As usual, this is where the bulk of our changes end up landing each
merge window.
The individual updates are too many to enumerate, many many platforms
have seen additions of device descriptions such that they are
functionally more complete (in fact, this is often the bulk of updates
we see).
Instead I've mostly focused on highlighting the new platforms below as
they are introduced. Sometimes the introduction is of mostly a fragment,
that later gets filled in on later releases, and in some cases it's
near-complete platform support. The latter is more common for derivative
platforms that already has similar support in-tree.
Two SoCs are slight outliers from the usual range of additions. Allwinner
support for F1C100s, a quite old SoC (ARMv5-based) shipping in the
Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A,
a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at
infrastructure/networking.
TI updates stick out in the diff stats too, in particular because they
have moved the description of their L4 on-chip interconnect to devicetree,
which opens up for removal of even more of their platform-specific
'hwmod' description tables over the next few releases.
SoCs:
- Qualcomm QCS404 (4x Cortex-A53)
- Allwinner T3 (rebranded R40) and f1c100s (armv5)
- NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
- NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)
New platforms:
- Rockchip: Gru Scarlet (RK3188 Tablet)
- Amlogic: Phicomm N1 (S905D), Libretech S805-AC
- Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
- Qualcomm: QCS404 base platform and EVB
- Qualcomm: Remove of Arrow SD600
- PXA: First PXA3xx DT board: Raumfeld
- Aspeed: Facebook Backpack-CMM BMC
- Renesas iWave G20D-Q7 (RZ/G1N)
- Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
- Allwinner Emlid Neutis N5, Mapleboard MP130
- Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
- i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
- VF610: Liebherr's BK4 device, ZII SCU4 AIB board
- i.MX7D PICO Hobbit baseboard
- i.MX7ULP EVK board
- NXP LX2160AQDS and LX2160ARDB boards
Other:
- Coresight binding updates across the board
- CPU cooling maps updates across the board
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"As usual, this is where the bulk of our changes end up landing each
merge window.
The individual updates are too many to enumerate, many many platforms
have seen additions of device descriptions such that they are
functionally more complete (in fact, this is often the bulk of updates
we see).
Instead I've mostly focused on highlighting the new platforms below as
they are introduced. Sometimes the introduction is of mostly a
fragment, that later gets filled in on later releases, and in some
cases it's near-complete platform support. The latter is more common
for derivative platforms that already has similar support in-tree.
Two SoCs are slight outliers from the usual range of additions.
Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping
in the Lychee Pi Nano platform. At the other end is NXP Layerscape
LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O
aimed at infrastructure/networking.
TI updates stick out in the diff stats too, in particular because they
have moved the description of their L4 on-chip interconnect to
devicetree, which opens up for removal of even more of their
platform-specific 'hwmod' description tables over the next few
releases.
SoCs:
- Qualcomm QCS404 (4x Cortex-A53)
- Allwinner T3 (rebranded R40) and f1c100s (armv5)
- NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
- NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)
New platforms:
- Rockchip: Gru Scarlet (RK3188 Tablet)
- Amlogic: Phicomm N1 (S905D), Libretech S805-AC
- Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
- Qualcomm: QCS404 base platform and EVB
- Qualcomm: Remove of Arrow SD600
- PXA: First PXA3xx DT board: Raumfeld
- Aspeed: Facebook Backpack-CMM BMC
- Renesas iWave G20D-Q7 (RZ/G1N)
- Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
- Allwinner Emlid Neutis N5, Mapleboard MP130
- Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
- i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
- VF610: Liebherr's BK4 device, ZII SCU4 AIB board
- i.MX7D PICO Hobbit baseboard
- i.MX7ULP EVK board
- NXP LX2160AQDS and LX2160ARDB boards
Other:
- Coresight binding updates across the board
- CPU cooling maps updates across the board"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits)
ARM: dts: suniv: Fix improper bindings include patch
ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards
arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node
ARM: dts: suniv: Fix improper bindings include patch
arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
arm64: dts: Remove unused properties from FSL QSPI driver nodes
ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes
ARM: dts: Remove unused properties from FSL QSPI driver nodes
arm64: dts: ti: k3-am654: Enable main domain McSPI0
arm64: dts: ti: k3-am654: Add McSPI DT nodes
arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes
arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
arm64: dts: ti: k3-am65-main: Add ECAP PWM node
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
ARM: dts: exynos: Specify I2S assigned clocks in proper node
ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2
...
Notable changes:
- Mitigations for Spectre v2 on some Freescale (NXP) CPUs.
- A large series adding support for pass-through of Nvidia V100 GPUs to guests
on Power9.
- Another large series to enable hardware assistance for TLB table walk on
MPC8xx CPUs.
- Some preparatory changes to our DMA code, to make way for further cleanups
from Christoph.
- Several fixes for our Transactional Memory handling discovered by fuzzing the
signal return path.
- Support for generating our system call table(s) from a text file like other
architectures.
- A fix to our page fault handler so that instead of generating a WARN_ON_ONCE,
user accesses of kernel addresses instead print a ratelimited and
appropriately scary warning.
- A cosmetic change to make our unhandled page fault messages more similar to
other arches and also more compact and informative.
- Freescale updates from Scott:
"Highlights include elimination of legacy clock bindings use from dts
files, an 83xx watchdog handler, fixes to old dts interrupt errors, and
some minor cleanup."
And many clean-ups, reworks and minor fixes etc.
Thanks to:
Alexandre Belloni, Alexey Kardashevskiy, Andrew Donnellan, Aneesh Kumar K.V,
Arnd Bergmann, Benjamin Herrenschmidt, Breno Leitao, Christian Lamparter,
Christophe Leroy, Christoph Hellwig, Daniel Axtens, Darren Stevens, David
Gibson, Diana Craciun, Dmitry V. Levin, Firoz Khan, Geert Uytterhoeven, Greg
Kurz, Gustavo Romero, Hari Bathini, Joel Stanley, Kees Cook, Madhavan
Srinivasan, Mahesh Salgaonkar, Markus Elfring, Mathieu Malaterre, Michal
Suchánek, Naveen N. Rao, Nick Desaulniers, Oliver O'Halloran, Paul Mackerras,
Ram Pai, Ravi Bangoria, Rob Herring, Russell Currey, Sabyasachi Gupta, Sam
Bobroff, Satheesh Rajendran, Scott Wood, Segher Boessenkool, Stephen Rothwell,
Tang Yuantian, Thiago Jung Bauermann, Yangtao Li, Yuantian Tang, Yue Haibing.
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Merge tag 'powerpc-4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
"Notable changes:
- Mitigations for Spectre v2 on some Freescale (NXP) CPUs.
- A large series adding support for pass-through of Nvidia V100 GPUs
to guests on Power9.
- Another large series to enable hardware assistance for TLB table
walk on MPC8xx CPUs.
- Some preparatory changes to our DMA code, to make way for further
cleanups from Christoph.
- Several fixes for our Transactional Memory handling discovered by
fuzzing the signal return path.
- Support for generating our system call table(s) from a text file
like other architectures.
- A fix to our page fault handler so that instead of generating a
WARN_ON_ONCE, user accesses of kernel addresses instead print a
ratelimited and appropriately scary warning.
- A cosmetic change to make our unhandled page fault messages more
similar to other arches and also more compact and informative.
- Freescale updates from Scott:
"Highlights include elimination of legacy clock bindings use from
dts files, an 83xx watchdog handler, fixes to old dts interrupt
errors, and some minor cleanup."
And many clean-ups, reworks and minor fixes etc.
Thanks to: Alexandre Belloni, Alexey Kardashevskiy, Andrew Donnellan,
Aneesh Kumar K.V, Arnd Bergmann, Benjamin Herrenschmidt, Breno Leitao,
Christian Lamparter, Christophe Leroy, Christoph Hellwig, Daniel
Axtens, Darren Stevens, David Gibson, Diana Craciun, Dmitry V. Levin,
Firoz Khan, Geert Uytterhoeven, Greg Kurz, Gustavo Romero, Hari
Bathini, Joel Stanley, Kees Cook, Madhavan Srinivasan, Mahesh
Salgaonkar, Markus Elfring, Mathieu Malaterre, Michal Suchánek, Naveen
N. Rao, Nick Desaulniers, Oliver O'Halloran, Paul Mackerras, Ram Pai,
Ravi Bangoria, Rob Herring, Russell Currey, Sabyasachi Gupta, Sam
Bobroff, Satheesh Rajendran, Scott Wood, Segher Boessenkool, Stephen
Rothwell, Tang Yuantian, Thiago Jung Bauermann, Yangtao Li, Yuantian
Tang, Yue Haibing"
* tag 'powerpc-4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (201 commits)
Revert "powerpc/fsl_pci: simplify fsl_pci_dma_set_mask"
powerpc/zImage: Also check for stdout-path
powerpc: Fix HMIs on big-endian with CONFIG_RELOCATABLE=y
macintosh: Use of_node_name_{eq, prefix} for node name comparisons
ide: Use of_node_name_eq for node name comparisons
powerpc: Use of_node_name_eq for node name comparisons
powerpc/pseries/pmem: Convert to %pOFn instead of device_node.name
powerpc/mm: Remove very old comment in hash-4k.h
powerpc/pseries: Fix node leak in update_lmb_associativity_index()
powerpc/configs/85xx: Enable CONFIG_DEBUG_KERNEL
powerpc/dts/fsl: Fix dtc-flagged interrupt errors
clk: qoriq: add more compatibles strings
powerpc/fsl: Use new clockgen binding
powerpc/83xx: handle machine check caused by watchdog timer
powerpc/fsl-rio: fix spelling mistake "reserverd" -> "reserved"
powerpc/fsl_pci: simplify fsl_pci_dma_set_mask
arch/powerpc/fsl_rmu: Use dma_zalloc_coherent
vfio_pci: Add NVIDIA GV100GL [Tesla V100 SXM2] subdriver
vfio_pci: Allow regions to add own capabilities
vfio_pci: Allow mapping extra regions
...
Add more SoC compatible strings to support more chips.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Scott Wood <oss@buserror.net>
* clk-renesas:
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
clk: renesas: rcar-gen3: Add documentation for SD clocks
clk: renesas: rcar-gen3: Set state when registering SD clocks
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
clk: renesas: r8a77995: Add missing CPEX clock
clk: renesas: r8a77995: Remove non-existent SSP clocks
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
clk: renesas: r8a77995: Correct parent clock of DU
clk: renesas: r8a77990: Correct parent clock of DU
clk: renesas: r8a77970: Add CPEX clock
clk: renesas: r8a77965: Add CPEX clock
clk: renesas: r8a7796: Add CPEX clock
clk: renesas: r8a7795: Add CPEX clock
clk: renesas: r8a774a1: Add CPEX clock
dt-bindings: clock: r8a7796: Remove CSIREF clock
dt-bindings: clock: r8a7795: Remove CSIREF clock
clk: renesas: Mark rza2_cpg_clk_register static
clk: renesas: r7s9210: Add USB clocks
clk: renesas: r8a77970: Add RPC clocks
clk: renesas: r7s9210: Add SDHI clocks
* clk-allwinner:
clk: sunxi-ng: a64: Allow parent change for VE clock
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: h3: Allow parent change for ve clock
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
clk: sunxi-ng: Add support for H6 DE3 clocks
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
clk: sunxi-ng: h6: Set video PLLs limits
clk: sunxi-ng: Use u64 for calculation of NM rate
clk: sunxi-ng: Adjust MP clock parent rate when allowed
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock
* clk-tegra:
clk: tegra: Return the exact clock rate from clk_round_rate
clk: tegra30: Use Tegra CPU powergate helper function
soc/tegra: pmc: Drop SMP dependency from CPU APIs
clk: tegra: Fix maximum audio sync clock for Tegra124/210
clk: tegra: get rid of duplicate defines
clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
clk: tegra20: Turn EMC clock gate into divider
* clk-meson: (25 commits)
clk: meson: axg-audio: use the clk input helper function
clk: meson: add clk-input helper function
clk: meson: Mark some things static
clk: meson: meson8b: add the read-only video clock trees
clk: meson: meson8b: add the fractional divider for vid_pll_dco
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
clk: meson: Fix GXL HDMI PLL fractional bits width
clk: meson: meson8b: add the CPU clock post divider clocks
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
clk: meson: clk-regmap: add read-only gate ops
clk: meson: meson8b: allow changing the CPU clock tree
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
clk: meson: meson8b: add support for more M/N values in sys_pll
clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
clk: meson: clk-pll: check if the clock is already enabled
clk: meson: meson8b: fix the width of the cpu_scale_div clock
clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
clk: meson: meson8b: use the HHI syscon if available
dt-bindings: clock: meson8b: use the registers from the HHI syscon
...
* clk-rockchip:
clk: rockchip: add clock-id to gate of ACODEC for rk3328
clk: rockchip: add clock ID of ACODEC for rk3328
clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
clk: rockchip: fix I2S1 clock gate register for rk3328
clk: rockchip: make rk3188 hclk_vio_bus critical
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
clk: rockchip: fix rk3188 sclk_smc gate data
clk: rockchip: fix typo in rk3188 spdif_frac parent
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
Note:
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When specifying external clock inputs to the CCM the current code
requires the clocks to be in a "clocks" child node of the DT root.
This is not really conformant with DT best practices.
To avoid the need to deviate from those best practices, allow the
clock inputs to be specified via standard clock handles. This is
in line with how drivers of the later CCM driver revisions on
newer i.MX SoCs handle this.
As we can't retroactively change the DT binding, allow this as an
option with a fallback to the old way of how this has been handled.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the clock input of the main clock controller
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the clock inputs of amlogic AO clock controller
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This adds the binding for the i.MX8MQ Clock Controller Module.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The #reset-cells was listed as optional in the bindings for
qcom,sdm845-videocc. There's no reason for it to be optional. As per
Stephen [1]:
> We should update the binding to make it a required property. It
> doesn't make any sense why that property would be optional given
> that the hardware either has support for resets or it doesn't.
sdm845 support is still in its infancy so we shouldn't be affecting
any real device trees by modifying the bindings here.
[1] https://lkml.kernel.org/r/154330186815.88331.12720647562079303842@swboyd.mtv.corp.google.com
Fixes: 84b66b2116 ("dt-bindings: clock: Introduce QCOM Video clock bindings")
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the bindings that landed for the gpucc we require that the XO clock
(one possible parent of the gpucc) be listed. The code doesn't use
this yet--this is just to allow us to move toward the day when it does
use it. What the code does do today is to hardcode the parent name to
"bi_tcxo". That's all well and good.
...but the example in the bindings shows this clock mapping to the
clock "xo_board". On the current sdm845.dtsi file the "xo_board"
clock is a fixed clock with an output name of "xo_board". The clock
with the name "bi_tcxo" is actually provided by the RPMh Clock
Controller. Presumably that's the one that was wanted.
Let's update the example to make this clearer.
Fixes: e431c92188 ("dt-bindings: clock: Introduce QCOM Graphics clock bindings")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clock controller on Meson8/Meson8m2 and Meson8b is part of a
register region called "HHI". This register area contains more
functionality than just a clock controller:
- the clock controller
- some reset controller bits
- temperature sensor calibration coefficient (only on Meson8b and
Meson8m2 - one one out of five TSC bits is stored in the HHI
registers)
- HDMI controller
The HHI register area may be accessed concurrently. Allow this by using
a "system controller" as parent node.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181028120859.5735-2-martin.blumenstingl@googlemail.com
Add a generic clk property for clks which are not intended to be used by
the OS due to security restrictions put in place by firmware. For
example, on some Qualcomm firmwares reading or writing certain clk
registers causes the entire system to reboot, but on other firmwares
reading and writing those same registers is required to make devices
like QSPI work. Rather than adding one-off properties each time a new
set of clks appears to be protected, let's add a generic clk property to
describe any set of clks that shouldn't be touched by the OS. This way
we never need to register the clks or use them in certain firmware
configurations.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add rpm smd clocks, PMIC and bus clocks which are required on QCS404
for clients to vote on.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bjorn: Dropped cxo, voter clocks and static initialization]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit adds necessary description and dt includes for H6 DE3 clock.
It is very similar to others, but memory region has some additional
registers not found in DE2.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
because of summer time holidays/vacations. The biggest change in the diffstat
is in the Qualcomm clk driver, where they got support for CPUs and handful of
SoCs. After that, the at91 driver got a major rewrite for newer DT bindings
that should make things easier going forward and the TI code moved to a
clockdomain based design. The long tail is mostly small driver updates for
newer clks and some simpler SoC clock drivers such as the Hisilicon and imx
support.
In the core framework, we only have two small changes this time. One is a new
clk API to get all clks for a device with the bulk clk APIs. This allows
drivers that don't care about doing anything besides turning on all the clks to
just clk_get() them all and turn them on. The other change is the beginning of
a way to support save and restore of clk settings in the clk framework. TI is
the only user right now, but we will want to expand upon this design in the
future to support more save and restore of clk registers. At least this gets
us started and works well enough for one SoC, but there's more work in the
future.
Core:
- clk_bulk_get_all() API and friends to get all the clks for a device
- Basic clk state save/restore hooks
New Drivers:
- Renesas RZ/A2 (R7S9210) SoC, including early clocks
- Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Rensas RZ/G2M (r8a774a1) SoC
- Qualcomm Krait CPU clk support
- Qualcomm QCS404 GCC support
- Qualcomm SDM660 GCC support
- Qualcomm SDM845 camera clock controller
- Ingenic jz4725b CGU
- Hisilicon 3670 SoC support
- TI SCI clks on K3 SoCs
- iMX6 MMDC clks
- Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs
Updates:
- Rework at91 PMC clock driver for new DT bindings
- Nvidia Tegra clk driver MBIST workaround fix
- S2RAM support for Marvell mvebu periph clks
- Use updated printk format for OF node names
- Fix TI code to only search DT subnodes
- Various static analysis finds
- Tag various drivers with SPDX license tags
- Support dynamic frequency switching (DFS) on qcom SDM845 GCC
- Only use s2mps11 dt-binding defines instead of redefining them in the driver
- Add some more missing clks to qcom MSM8996 GCC
- Quad SPI clks on qcom SDM845
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs
- Amlogic clk-pll driver improvements and updates
- Amlogic axg audio controller system clocks
- Register Amlogic meson8b clock controller early
- Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N
- Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers
- Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC
- Remove obsoleted Exynos4212 ISP clock definitions
- Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design
- TI RTC+DDR sleep mode support for clock save/restore
- Allwinner A64 display engine support and fixes
- Allwinner A83t display engine support and fixes
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time it looks like a quieter release cycle in the clk tree. I
guess that's because of summer time holidays/vacations. The biggest
change in the diffstat is in the Qualcomm clk driver, where they got
support for CPUs and handful of SoCs. After that, the at91 driver got
a major rewrite for newer DT bindings that should make things easier
going forward and the TI code moved to a clockdomain based design.
The long tail is mostly small driver updates for newer clks and some
simpler SoC clock drivers such as the Hisilicon and imx support.
In the core framework, we only have two small changes this time.
One is a new clk API to get all clks for a device with the bulk clk
APIs. This allows drivers that don't care about doing anything besides
turning on all the clks to just clk_get() them all and turn them on.
The other change is the beginning of a way to support save and restore
of clk settings in the clk framework. TI is the only user right now,
but we will want to expand upon this design in the future to support
more save and restore of clk registers. At least this gets us started
and works well enough for one SoC, but there's more work in the
future.
Core:
- clk_bulk_get_all() API and friends to get all the clks for a device
- Basic clk state save/restore hooks
New Drivers:
- Renesas RZ/A2 (R7S9210) SoC, including early clocks
- Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Rensas RZ/G2M (r8a774a1) SoC
- Qualcomm Krait CPU clk support
- Qualcomm QCS404 GCC support
- Qualcomm SDM660 GCC support
- Qualcomm SDM845 camera clock controller
- Ingenic jz4725b CGU
- Hisilicon 3670 SoC support
- TI SCI clks on K3 SoCs
- iMX6 MMDC clks
- Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs
Updates:
- Rework at91 PMC clock driver for new DT bindings
- Nvidia Tegra clk driver MBIST workaround fix
- S2RAM support for Marvell mvebu periph clks
- Use updated printk format for OF node names
- Fix TI code to only search DT subnodes
- Various static analysis finds
- Tag various drivers with SPDX license tags
- Support dynamic frequency switching (DFS) on qcom SDM845 GCC
- Only use s2mps11 dt-binding defines instead of redefining them in the driver
- Add some more missing clks to qcom MSM8996 GCC
- Quad SPI clks on qcom SDM845
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs
- Amlogic clk-pll driver improvements and updates
- Amlogic axg audio controller system clocks
- Register Amlogic meson8b clock controller early
- Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N
- Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers
- Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC
- Remove obsoleted Exynos4212 ISP clock definitions
- Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design
- TI RTC+DDR sleep mode support for clock save/restore
- Allwinner A64 display engine support and fixes
- Allwinner A83t display engine support and fixes"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (186 commits)
clk: qcom: Remove unused arrays in SDM845 GCC
clk: fixed-rate: fix of_node_get-put imbalance
clk: s2mps11: Add used attribute to s2mps11_dt_match
clk: qcom: gcc-sdm660: Add MODULE_LICENSE
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: clock: Document qcom,krait-cc
clk: qcom: Add Krait clock controller driver
dt-bindings: arm: Document qcom,kpss-gcc
clk: qcom: Add KPSS ACC/GCC driver
clk: qcom: Add support for Krait clocks
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add MSM8960/APQ8064's HFPLLs
dt-bindings: clock: Document qcom,hfpll
clk: qcom: Add HFPLL driver
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
ARM: Add Krait L2 register accessor functions
clk: imx6q: add mmdc0 ipg clock
clk: imx6sl: add mmdc ipg clocks
clk: imx6sll: add mmdc1 ipg clock
clk: imx6sx: add mmdc1 ipg clock
...
- Hisilicon 3670 SoC support
* clk-samsung:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
* clk-hisi3670:
clk: hisilicon: Add clock driver for Hi3670 SoC
dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
* clk-at91-div-0:
clk: at91: Fix division by zero in PLL recalc_rate()
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document the new PMC binding with only one PMC node for all the PMC clocks
instead of one node per clock as this proved to be problematic.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This is better than letting the other developers wondering what are the
supported strings.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.
The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there are no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Business as usual -- the bulk of our changes are to devicetree files
with new hardware support, new SoCs and platforms, and new board types.
New SoCs/platforms:
- Raspberry Pi Compute Module (CM1) and IO board
- i.MX6SSL from NXP
- Renesas RZ/N1D SoC (R9A06G032), Dual Cortex-A7 with Ethernet, CAN and
PLC interfaces
- TI AM654 SoC, Quad Cortex-A53, safety subsystem with Cortex-R5
controllers, communication and PRU subsystem and lots of other
interfaces (PCIe, USB3, etc).
New boards and systems:
- Several Atmel at91-based boards from Laird
- Marvell Armada388-based Helios4 board from SolidRun
- Samsung Aires-based phones (s5pv210)
- Allwinner A64-based Pinebook laptop
In addition to the above, there's the usual amount of new devices
described on existing platforms, fixes and tweaks and new minor variants
of boards/platforms.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Olof Johansson:
"Business as usual -- the bulk of our changes are to devicetree files
with new hardware support, new SoCs and platforms, and new board
types.
New SoCs/platforms:
- Raspberry Pi Compute Module (CM1) and IO board
- i.MX6SSL from NXP
- Renesas RZ/N1D SoC (R9A06G032), Dual Cortex-A7 with Ethernet, CAN
and PLC interfaces
- TI AM654 SoC, Quad Cortex-A53, safety subsystem with Cortex-R5
controllers, communication and PRU subsystem and lots of other
interfaces (PCIe, USB3, etc).
New boards and systems:
- Several Atmel at91-based boards from Laird
- Marvell Armada388-based Helios4 board from SolidRun
- Samsung Aires-based phones (s5pv210)
- Allwinner A64-based Pinebook laptop
In addition to the above, there's the usual amount of new devices
described on existing platforms, fixes and tweaks and new minor
variants of boards/platforms"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (478 commits)
arm64: dts: sdm845: Add tsens nodes
arm64: dts: msm8996: thermal: Initialise via DT and add second controller
arm64: dts: sprd: Add one suspend timer
arm64: dts: sprd: Add SC27XX ADC device
arm64: dts: sprd: Add SC27XX eFuse device
arm64: dts: sprd: Add SC27XX vibrator device
arm64: dts: sprd: Add SC27XX breathing light controller device
arm64: dts: meson-axg: add spdif-dit codec
arm64: dts: meson-axg: add lineout codec
arm64: dts: meson-axg: add linein codec
arm64: dts: meson-axg: add tdm interfaces
arm64: dts: meson-axg: add tdmout formatters
arm64: dts: meson-axg: add tdmin formatters
arm64: dts: meson-axg: add spdifout
arm64: dts: rockchip: add led support for Firefly-RK3399
arm64: dts: rockchip: remove deprecated Type-C PHY properties on rk3399
arm64: dts: rockchip: add power button support for Firefly-RK3399
ARM: dts: aspeed: Add coprocessor interrupt controller
arm64: dts: meson-axg: add audio arb reset controller
arm64: dts: meson-axg: add usb power regulator
...
Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multiple
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
soc: sunxi: Add the A13, A23 and H3 system control compatibles
reset: uniphier: add reset control support for SPI
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
soc: mediatek: pwrap: fix cipher init setting error
dt-bindings: pwrap: mediatek: add pwrap support for MT6797
reset: uniphier: add USB3 core reset control
dt-bindings: reset: uniphier: add USB3 core reset support
...
We've added duty cycle support to the clk API so that clk signal
duty cycle ratios can be adjusted while taking into account things
like clk dividers and clk tree hierarchy. So far only one SoC has
implemented support for this, but I expect there will be more to
come in the future.
Outside of the core, we have the usual pile of clk driver updates
and additions. The Amlogic meson driver got the most lines in the
diffstat this time around because it added support for a whole bunch
of hardware and duty cycle configuration. After that the Rockchip PX30,
Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff.
We're left with the collection of non-critical fixes after that. Overall
it looks pretty quiet this time.
Core:
- Clk duty cycle support
- Proper CLK_SET_RATE_GATE support throughout the tree
New Drivers:
- Actions Semi Owl series S700 SoC clk driver
- Qualcomm SDM845 display clock controller
- i.MX6SX ocram_s clk support
- Uniphier NAND, USB3 PHY, and SPI clk support
- Qualcomm RPMh clk driver
- i.MX7D mailbox clk support
- Maxim 9485 Programmable Clock Generator
- Expose 32 kHz PLL on PXA SoCs
- imx6sll GPIO clk gate support
- Atmel at91 I2S audio clk support
- SI544/SI514 clk on/off support
- i.MX6UL GPIO clock gates in CCM CCGR
- Renesas Crypto Engine clocks on R-Car H3
- Renesas clk support for the new RZ/N1D SoC
- Allwinner A64 display engine clock support
- Support for Rockchip's PX30 SoC
- Amlogic Meson axg PCIe and audio clocks
- Amlogic Meson GEN CLK on gxbb, gxl and axg
Updates:
- Remove an unused variable from Exynos4412 ISP driver
- Fix a thinko bug in SCMI clk division logic
- Add missing of_node_put()s in some i.MX clk drivers
- Tegra SDMMC clk jitter improvements with high speed signaling modes
- SPDX tagging for qcom and cs2000-cp drivers
- Stop leaking con ids in __clk_put()
- Fix a corner case in fixed factor clk probing where node is in DT but
parent clk is registered much later
- Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value
- i.MX clk init arrays removed in place of CLK_IS_CRITICAL
- Convert to CLK_IS_CRITICAL for i.MX51/53 driver
- Fix Tegra BPMP driver oops when xlating a NULL clk
- Proper default configuration for vic03 and vde clks on Tegra124
- Mark Tegra memory controller clks as critical
- Fix array bounds clamp in Tegra's emc determine_rate() op
- Ingenic i2s bit update and allow UDC clk to gate
- Fix name of aspeed SDC clk define to have only one 'CLK'
- Fix i.MX6QDL video clk parent
- Critical clk markings for qcom SDM845
- Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
- Mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying
the pwm used to drive the logic supply of the rk3399 core.
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The new and exciting feature this time around is in the clk core.
We've added duty cycle support to the clk API so that clk signal duty
cycle ratios can be adjusted while taking into account things like clk
dividers and clk tree hierarchy. So far only one SoC has implemented
support for this, but I expect there will be more to come in the
future.
Outside of the core, we have the usual pile of clk driver updates and
additions. The Amlogic meson driver got the most lines in the diffstat
this time around because it added support for a whole bunch of
hardware and duty cycle configuration. After that the Rockchip PX30,
Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the
diff. We're left with the collection of non-critical fixes after that.
Overall it looks pretty quiet this time.
Core:
- Clk duty cycle support
- Proper CLK_SET_RATE_GATE support throughout the tree
New Drivers:
- Actions Semi Owl series S700 SoC clk driver
- Qualcomm SDM845 display clock controller
- i.MX6SX ocram_s clk support
- Uniphier NAND, USB3 PHY, and SPI clk support
- Qualcomm RPMh clk driver
- i.MX7D mailbox clk support
- Maxim 9485 Programmable Clock Generator
- expose 32 kHz PLL on PXA SoCs
- imx6sll GPIO clk gate support
- Atmel at91 I2S audio clk support
- SI544/SI514 clk on/off support
- i.MX6UL GPIO clock gates in CCM CCGR
- Renesas Crypto Engine clocks on R-Car H3
- Renesas clk support for the new RZ/N1D SoC
- Allwinner A64 display engine clock support
- support for Rockchip's PX30 SoC
- Amlogic Meson axg PCIe and audio clocks
- Amlogic Meson GEN CLK on gxbb, gxl and axg
Updates:
- remove an unused variable from Exynos4412 ISP driver
- fix a thinko bug in SCMI clk division logic
- add missing of_node_put()s in some i.MX clk drivers
- Tegra SDMMC clk jitter improvements with high speed signaling modes
- SPDX tagging for qcom and cs2000-cp drivers
- stop leaking con ids in __clk_put()
- fix a corner case in fixed factor clk probing where node is in DT
but parent clk is registered much later
- Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return
value
- i.MX clk init arrays removed in place of CLK_IS_CRITICAL
- convert to CLK_IS_CRITICAL for i.MX51/53 driver
- fix Tegra BPMP driver oops when xlating a NULL clk
- proper default configuration for vic03 and vde clks on Tegra124
- mark Tegra memory controller clks as critical
- fix array bounds clamp in Tegra's emc determine_rate() op
- Ingenic i2s bit update and allow UDC clk to gate
- fix name of aspeed SDC clk define to have only one 'CLK'
- fix i.MX6QDL video clk parent
- critical clk markings for qcom SDM845
- fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
- mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it
supplying the pwm used to drive the logic supply of the rk3399
core"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits)
clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
clk: cs2000-cp: convert to SPDX identifiers
clk: scmi: Fix the rounding of clock rate
clk: qcom: Add display clock controller driver for SDM845
clk: mvebu: armada-37xx-periph: Remove unused var num_parents
clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable
clk: actions: Add S700 SoC clock support
dt-bindings: clock: Add S700 support for Actions Semi Soc's
clk: actions: Add missing REGMAP_MMIO dependency
clk: uniphier: add clock frequency support for SPI
clk: uniphier: add more USB3 PHY clocks
clk: uniphier: add NAND 200MHz clock
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
clk: tegra: Add sdmmc mux divider clock
clk: tegra: Refactor fractional divider calculation
clk: tegra: Fix includes required by fence_udelay()
clk: imx6sll: fix missing of_node_put()
clk: imx6ul: fix missing of_node_put()
clk: imx: add ocram_s clock for i.mx6sx
clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
...
- new SoC: S905W
- new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini
- AXG: add DT for new audio clock controller
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Merge tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
Amlogic 64-bit DT changes for v4.19, round 2
- new SoC: S905W
- new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini
- AXG: add DT for new audio clock controller
* tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: meson-gxl: add support for the Oranth Tanix TX3 Mini
ARM64: dts: meson-gxl: add support for the S905W SoC and the P281 board
dt-bindings: arm: amlogic: Add support for the Oranth Tanix TX3 Mini
dt-bindings: arm: amlogic: Add support for GXL S905W and the P281 board
dt-bindings: add vendor prefix for Shenzhen Oranth Technology Co., Ltd.
ARM64: dts: meson-axg: add the audio clock controller
clk: meson: expose GEN_CLK clkid
clk: meson-axg: add pcie and mipi clock bindings
dt-bindings: clock: add meson axg audio clock controller bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
'interrupt-parent' is often documented as part of define bindings, but
it is really outside the scope of a device binding. It's never required
in a given node as it is often inherited from a parent node. Or it can
be implicit if a parent node is an 'interrupt-controller' node. So
remove it from all the binding files.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
The Exynos5440 is not actively developed, there are no development
boards available and probably there are no real products with it.
Remove wide-tree support for Exynos5440.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Sylwester Nawrocki <snawrocki@kernel.org>
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds the devicetree bindings for MAX9485, a programmable audio
clock generator.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The I2S mux clock can be used to select the I2S input clock. The
available parents are the peripheral and the generated clocks.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Allwinner A64 SoC has a DE2 CCU like the one in the DE2 of Allwinner
H5 SoC.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Export the clock ids dt-bindings usable by the consumers of the clock
controller and add the documentation for the device tree bindings of
the audio clock controller of the A113 based SoCs.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add missing PMC compatibles to the list of available compatibles.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
As we move stuff around, some doc references are broken. Fix some of
them via this script:
./scripts/documentation-file-ref-check --fix
Manually checked that produced results are valid.
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Miguel Ojeda <miguel.ojeda.sandonis@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: Jonathan Corbet <corbet@lwn.net>
As always, a large number of DT updates. Too many to enumerate them all,
but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set
top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other on-chip
ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current high-end
mobile SoCs.
It's great to see mainline support for it. So far, you
can't do much with it, since a lot of peripherals are not yet in the
DTs but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC upstream if
the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive entertainment-targeted
SoC. Currently only one Cortex-A53 CPU is enabled, we are eagerly
awaiting more. So far, basic drivers such as serial, gpios, PMU and
ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and ethernet
enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions might
not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too many to enumerate them
all, but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
set top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other
on-chip ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current
high-end mobile SoCs.
It's great to see mainline support for it. So far, you can't do
much with it, since a lot of peripherals are not yet in the DTs
but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC
upstream if the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive
entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
enabled, we are eagerly awaiting more. So far, basic drivers
such as serial, gpios, PMU and ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and
ethernet enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions
might not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
ARM: dts: aspeed: Fix hwrng register address
arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
arm64: dts: sprd: Add GPIO and GPIO keys device nodes
arm64: dts: sprd: fix typo in 'remote-endpoint'
arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
arm64: dts: fix regulator property name for wlan pcie endpoint
arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
ARM: dts: pxa3xx: fix MMC clocks
ARM: pxa: dts: add pin definitions for extended GPIOs
ARM: pxa: dts: add gpio-ranges to gpio controller
ARM: dts: ipq8074: Enable few peripherals for hk01 board
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Change the max opp frequency
...
* clk-qcom-sdm845:
clk: qcom: Export clk_fabia_pll_configure()
clk: qcom: Add video clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Video clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SDM845
clk: qcom: Add DT bindings for SDM845 gcc clock controller
clk: qcom: Configure the RCGs to a safe source as needed
clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
clk: qcom: Simplify gdsc status checking logic
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: Add support for controlling Fabia PLL
clk: qcom: Clear hardware clock control bit of RCG
Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the
description and also the video Kconfig says things slightly differently
from the GCC one so just make it the same.
* clk-match-string:
clk: use match_string() helper
clk: bcm2835: use match_string() helper
* clk-ingenic:
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
clk: ingenic: jz4770: Change OTG from custom to standard gated clock
clk: ingenic: Support specifying "wait for clock stable" delay
clk: ingenic: Add support for clocks whose gate bit is inverted
* clk-si544-round-fix:
clk-si544: Properly round requested frequency to nearest match
* clk-bcm-stingray:
clk: bcm: Update and add Stingray clock entries
dt-bindings: clk: Update Stingray binding doc
* clk-qcom-rpmh:
dt-bindings: clock: Introduce QCOM RPMh clock bindings
* clk-npcm7xx:
clk: npcm7xx: fix return value check in npcm7xx_clk_init()
clk: npcm7xx: add clock controller
dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock
* clk-of-parent-count:
pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding
soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding
ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding
clk: Extract OF clock helpers in <linux/of_clk.h>
* clk-qcom-rcg-fix:
clk: qcom: Base rcg parent rate off plan frequency
Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson into v4.18/dt64
First round of binding update for meson clocks targeted at v4.18
# gpg: Signature made Wed May 16 01:23:15 2018 PDT
# gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Can't check signature: No public key
* tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson:
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
dt-bindings: clock: meson8b: export the NAND clock
Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.
As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.
That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.
Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Initial support for R-Car E3 (r8a77990), including core and module
clocks.
Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".
Inspried by patches by Takeshi Kihara in the BSP.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add compatible string and the include file for gcc clock
controller for SDM845.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The HHI register region hosts more than just clocks and needs to
accessed drivers other than the clock controller, such as the display
driver.
This register region should be managed by syscon. It is already the case
on gxbb/gxl and it soon will be on axg. The clock controllers must use
this system controller instead of directly mapping the registers.
This changes the bindings of gxbb and axg's clock controllers. This is
due to an initial 'incomplete' knowledge of these SoCs, which is why the
meson bindings are unstable ATM.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add support for the global clock controller found on MSM8998
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: Imran Khan <kimran@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[bjorn: Specify regs for alpha_plls, fix white spaces and add binding]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk-davinci:
clk: davinci: Remove redundant dev_err calls
clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
clk: davinci: New driver for TI DA8XX CFGCHIP clocks
dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks
clk: davinci: Add platform information for TI DM646x PSC
clk: davinci: Add platform information for TI DM644x PSC
clk: davinci: Add platform information for TI DM365 PSC
clk: davinci: Add platform information for TI DM355 PSC
clk: davinci: Add platform information for TI DA850 PSC
clk: davinci: Add platform information for TI DA830 PSC
clk: davinci: New driver for davinci PSC clocks
dt-bindings: clock: New bindings for TI Davinci PSC
clk: davinci: Add platform information for TI DM646x PLL
clk: davinci: Add platform information for TI DM644x PLL
clk: davinci: Add platform information for TI DM365 PLL
clk: davinci: Add platform information for TI DM355 PLL
clk: davinci: Add platform information for TI DA850 PLL
clk: davinci: Add platform information for TI DA830 PLL
clk: davinci: New driver for davinci PLL clocks
dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
* clk-si544:
clk: Add driver for the si544 clock generator chip
* clk-rockchip:
clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
clk: rockchip: Fix error return in phase clock registration
clk: rockchip: Correct the behaviour of restoring cached phase
clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
clk: rockchip: Add 1.6GHz PLL rate for rk3399
clk: rockchip: Restore the clock phase after the rate was changed
clk: rockchip: Prevent calculating mmc phase if clock rate is zero
clk: rockchip: Free the memory on the error path
clk: rockchip: document hdmi_phy external input for rk3328
clk: rockchip: add flags for rk3328 dclk_lcdc
clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
clk: rockchip: protect all remaining rk3328 interconnect clocks
clk: rockchip: export sclk_hdmi_sfc on rk3328
clk: rockchip: remove HCLK_VIO from rk3328 dt header
clk: rockchip: fix hclk_vio_niu on rk3328
* clk-uniphier:
clk: uniphier: add additional ethernet clock lines for Pro4
clk: uniphier: add SATA clock control support
clk: uniphier: add PCIe clock control support
clk: uniphier: add ethernet clock control support for PXs3
clk: uniphier: add Pro4/Pro5/PXs2 audio system clock
* clk-ti-flag-fix:
clk: ti: fix flag space conflict with clkctrl clocks
clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
Document that Stratix10 clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Stratix10
platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Nuvoton NPCM7XX Clock Controller
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This adds a new binding for the clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This adds a new binding for the Power Sleep Controller (PSC) for the
mach-davinci family of processors.
Note: Although TI Keystone has a very similar PSC, we are not using the
existing bindings. Keystone is using a legacy one-node-per-clock binding
(actually two nodes if you count the separate reset binding for the same
IP block). Also, some davinci LPSCs have quirks that aren't handled by
the keystone bindings, so we would be adding one compatible string per
clock with quirks instead of just a new compatible string for each
controller.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This adds a new binding for the PLL IP blocks in the mach-davinci
family of processors. Currently, only da850 has device tree support
but these bindings can also work for other SoCs in this family just
by adding new compatible strings.
Note: Although these PLL controllers are very similar to the TI Keystone
SoCs, we are not re-using those bindings. The Keystone bindings use a
legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
have a slightly different PLL register layout and a number of quirks
that can't be handled by the existing bindings, so the keystone bindings
could not be used as-is anyway.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Allwinner H6 main CCU uses the internal oscillator of the SoC, which
is different with old SoCs' main CCU.
Add device tree binding for the Allwinner H6 main CCU.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The RCC block is responsible of the management of the clock and reset
generation for the complete circuit.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Certain hardware configurations, like dra76x, have some of the clock
registers partitioned in a funky manner that requires the clock
control setup to be latched for PRCM to be notified of the change. This
is accomplished with a separate control bit under the register. Add
support for this clock latching support to divider and mux clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Initial support for R-Car M3-N (r8a77965), including core and module
clocks.
Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual:
Hardware (Rev. 0.80, Oct 31, 2017)".
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The hdmi-phy block inside the soc also loops its pll output back
into the clock controller, so document that already used input clock.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
to the clk rate protection support added by Jerome Brunet. This feature
will allow consumers to lock in a certain rate on the output of a clk so
that things like audio playback don't hear pops when the clk frequency
changes due to shared parent clks changing rates. Currently the clk
API doesn't guarantee the rate of a clk stays at the rate you request
after clk_set_rate() is called, so this new API will allow drivers
to express that requirement. Beyond this, the core got some debugfs
pretty printing patches and a couple minor non-critical fixes.
Looking outside of the core framework diff we have some new driver
additions and the removal of a legacy TI clk driver. Both of these hit
high in the dirstat. Also, the removal of the asm-generic/clkdev.h file
causes small one-liners in all the architecture Kbuild files. Overall, the
driver diff seems to be the normal stuff that comes all the time to
fix little problems here and there and to support new hardware.
Core:
- Clk rate protection
- Symbolic clk flags in debugfs output
- Clk registration enabled clks while doing bookkeeping updates
New Drivers:
- Spreadtrum SC9860
- HiSilicon hi3660 stub
- Qualcomm A53 PLL, SPMI clkdiv, and MSM8916 APCS
- Amlogic Meson-AXG
- ASPEED BMC
Removed Drivers:
- TI OMAP 3xxx legacy clk (non-DT) support
- asm*/clkdev.h got removed (not really a driver)
Updates:
- Renesas FDP1-0 module clock on R-Car M3-W
- Renesas LVDS module clock on R-Car V3M
- Misc fixes to pr_err() prints
- Qualcomm MSM8916 audio fixes
- Qualcomm IPQ8074 rounded out support for more peripherals
- Qualcomm Alpha PLL variants
- Divider code was using container_of() on bad pointers
- Allwinner DE2 clks on H3
- Amlogic minor data fixes and dropping of CLK_IGNORE_UNUSED
- Mediatek clk driver compile test support
- AT91 PMC clk suspend/resume restoration support
- PLL issues fixed on si5351
- Broadcom IProc PLL calculation updates
- DVFS support for Armada mvebu CPU clks
- Allwinner fixed post-divider support
- TI clkctrl fixes and support for newer SoCs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The core framework has a handful of patches this time around, mostly
due to the clk rate protection support added by Jerome Brunet.
This feature will allow consumers to lock in a certain rate on the
output of a clk so that things like audio playback don't hear pops
when the clk frequency changes due to shared parent clks changing
rates. Currently the clk API doesn't guarantee the rate of a clk stays
at the rate you request after clk_set_rate() is called, so this new
API will allow drivers to express that requirement.
Beyond this, the core got some debugfs pretty printing patches and a
couple minor non-critical fixes.
Looking outside of the core framework diff we have some new driver
additions and the removal of a legacy TI clk driver. Both of these hit
high in the dirstat. Also, the removal of the asm-generic/clkdev.h
file causes small one-liners in all the architecture Kbuild files.
Overall, the driver diff seems to be the normal stuff that comes all
the time to fix little problems here and there and to support new
hardware.
Summary:
Core:
- Clk rate protection
- Symbolic clk flags in debugfs output
- Clk registration enabled clks while doing bookkeeping updates
New Drivers:
- Spreadtrum SC9860
- HiSilicon hi3660 stub
- Qualcomm A53 PLL, SPMI clkdiv, and MSM8916 APCS
- Amlogic Meson-AXG
- ASPEED BMC
Removed Drivers:
- TI OMAP 3xxx legacy clk (non-DT) support
- asm*/clkdev.h got removed (not really a driver)
Updates:
- Renesas FDP1-0 module clock on R-Car M3-W
- Renesas LVDS module clock on R-Car V3M
- Misc fixes to pr_err() prints
- Qualcomm MSM8916 audio fixes
- Qualcomm IPQ8074 rounded out support for more peripherals
- Qualcomm Alpha PLL variants
- Divider code was using container_of() on bad pointers
- Allwinner DE2 clks on H3
- Amlogic minor data fixes and dropping of CLK_IGNORE_UNUSED
- Mediatek clk driver compile test support
- AT91 PMC clk suspend/resume restoration support
- PLL issues fixed on si5351
- Broadcom IProc PLL calculation updates
- DVFS support for Armada mvebu CPU clks
- Allwinner fixed post-divider support
- TI clkctrl fixes and support for newer SoCs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
clk: aspeed: Fix return value check in aspeed_cc_init()
clk: aspeed: Add reset controller
clk: aspeed: Register gated clocks
clk: aspeed: Add platform driver and register PLLs
clk: aspeed: Register core clocks
clk: Add clock driver for ASPEED BMC SoCs
clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built
clk: fix reentrancy of clk_enable() on UP systems
clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
clk: Simplify debugfs registration
clk: Fix debugfs_create_*() usage
clk: Show symbolic clock flags in debugfs
clk: renesas: r8a7796: Add FDP clock
clk: Move __clk_{get,put}() into private clk.h API
clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks
clk: Improve flags doc for of_clk_detect_critical()
arch: Remove clkdev.h asm-generic from Kbuild
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
clk: Prepare to remove asm-generic/clkdev.h
...
We get a moderate number of new machines this time, and only one
new SoC variant (Actions S700):
Actions:
S700 Soc and CubieBoard7 development board
Allo.com Sparky Single-board-computer
Allwinner:
Orange Pi R1 development board
Libre Computer Board ALL-H3-CC H3 single-board computer
ASpeed ast2x00:
Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500
Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500
Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400
AT91:
Axentia Nattis/Natte digital signage
sama5d2 PTC-ek Evaluation board
Freescale/NXP i.MX:
SolidRun Humminboard2 development board
Variscite DART-MX6 SoM and Carrier-board
Technologic TS-4600 and TS-7970 development board
Toradex Colibri iMX7D SoM board
v1.5 variant of Solidrun Cubox-i and Hummingboard
Freescale/NXP Layerscape:
Moxa UC-8410A Series industrial computer
Gemini:
D-Link DNS-313 NAS enclosure
OMAP:
LogicPD OMAP35xx SOM-LV devkit
LogicPD OMAP35xx Torpedo devkit
Renesas:
r8a77970 (V3M) Starter Kit board
r8a7795 (M3-W) Salvator-XS board
We finally managed to get the dtc warnings under control, with no more
build-time warnings for bad device tree files. This includes fixes for
the majority of platforms, including nomadik, samsung, lpc32xx, STi,
spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood,
renesas, hisilicon, and broadcom.
Files get rearranged on a few platforms, in particular the Marvell
Armada 7K/8K device tree files are changed in preparation for future
SoC support, based on more than two of the same chips in one package,
and some boards get renamed for oxnas for consistency.
Finally, many existing SoCs gain descriptions for additional on-chip
devices that we can now support with kernel drivers:
Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG)
Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi)
Aspeed clk controller support
Freescale LS1088A, LS1021A device support
Gemini Ethernet, PCI, TVE, panel
Keystone gpio, qspi, more uarts
Mediatek cpufreq, regulator, clock, reset
Marvell thermal, cpufreq, nand
Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu
Rockchip Mipi, GPU, display
Samsung Exynos5433 PMU, power domain, nfc
Spreadtrum: sc9860 clocks
Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ...
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Arnd Bergmann:
"We get a moderate number of new machines this time, and only one new
SoC variant (Actions S700):
Actions:
- S700 Soc and CubieBoard7 development board
- Allo.com Sparky Single-board-computer
Allwinner:
- Orange Pi R1 development board
- Libre Computer Board ALL-H3-CC H3 single-board computer
ASpeed ast2x00:
- Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500
- Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500
- Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400
AT91:
- Axentia Nattis/Natte digital signage
- sama5d2 PTC-ek Evaluation board
Freescale/NXP i.MX:
- SolidRun Humminboard2 development board
- Variscite DART-MX6 SoM and Carrier-board
- Technologic TS-4600 and TS-7970 development board
- Toradex Colibri iMX7D SoM board
- v1.5 variant of Solidrun Cubox-i and Hummingboard
Freescale/NXP Layerscape:
- Moxa UC-8410A Series industrial computer
Gemini:
- D-Link DNS-313 NAS enclosure
OMAP:
- LogicPD OMAP35xx SOM-LV devkit
- LogicPD OMAP35xx Torpedo devkit
Renesas:
- r8a77970 (V3M) Starter Kit board
- r8a7795 (M3-W) Salvator-XS board
We finally managed to get the dtc warnings under control, with no more
build-time warnings for bad device tree files. This includes fixes for
the majority of platforms, including nomadik, samsung, lpc32xx, STi,
spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood,
renesas, hisilicon, and broadcom.
Files get rearranged on a few platforms, in particular the Marvell
Armada 7K/8K device tree files are changed in preparation for future
SoC support, based on more than two of the same chips in one package,
and some boards get renamed for oxnas for consistency.
Finally, many existing SoCs gain descriptions for additional on-chip
devices that we can now support with kernel drivers:
- Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG)
- Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi)
- Aspeed clk controller support
- Freescale LS1088A, LS1021A device support
- Gemini Ethernet, PCI, TVE, panel
- Keystone gpio, qspi, more uarts
- Mediatek cpufreq, regulator, clock, reset
- Marvell thermal, cpufreq, nand
- Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu
- Rockchip Mipi, GPU, display
- Samsung Exynos5433 PMU, power domain, nfc
- Spreadtrum: sc9860 clocks
- Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ..."
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (690 commits)
arm64: dts: stratix10: fix SPI settings
ARM: dts: socfpga: add i2c reset signals
arm64: dts: stratix10: add USB ECC reset bit
arm64: dts: stratix10: enable USB on the devkit
ARM: dts: socfpga: disable over-current for Arria10 USB devkit
ARM: dts: Nokia N9: add support for up/down keys in the dts
ARM: dts: nomadik: add interrupt-parent for clcd
ARM: dts: Add ethernet to a bunch of platforms
ARM: dts: Add ethernet to the Gemini SoC
ARM: dts: rename oxnas dts files
ARM: dts: s5pv210: add interrupt-parent for ohci
ARM: lpc3250: fix uda1380 gpio numbers
ARM: dts: STi: Add gpio polarity for "hdmi,hpd-gpio" property
ARM: dts: dra7: Reduce shut down temperature of non-cpu thermal zones
ARM: dts: n900: Add aliases for lcd and tvout displays
ARM: dts: Update ti-sysc data for existing users
ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance
arm64: dts: marvell: armada-80x0: Fix pinctrl compatible string
arm: spear13xx: Fix spics gpio controller's warning
arm: spear13xx: Fix dmas cells
...
* clk-aspeed:
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
clk: aspeed: Fix return value check in aspeed_cc_init()
clk: aspeed: Add reset controller
clk: aspeed: Register gated clocks
clk: aspeed: Add platform driver and register PLLs
clk: aspeed: Register core clocks
clk: Add clock driver for ASPEED BMC SoCs
dt-bindings: clock: Add ASPEED constants
* clk-lock-UP:
clk: fix reentrancy of clk_enable() on UP systems
* clk-mediatek:
clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built
clk: mediatek: Fix all warnings for missing struct clk_onecell_data
clk: mediatek: fixup test-building of MediaTek clock drivers
clk: mediatek: group drivers under indpendent menu
* clk-allwinner:
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: Support fixed post-dividers on MP style clocks
clk: sunxi: Use PTR_ERR_OR_ZERO()
* clk-remove-asm-clkdev:
clk: Move __clk_{get,put}() into private clk.h API
clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks
arch: Remove clkdev.h asm-generic from Kbuild
clk: Prepare to remove asm-generic/clkdev.h
blackfin: Use generic clkdev.h header
* clk-debugfs-fixes:
clk: Simplify debugfs registration
clk: Fix debugfs_create_*() usage
clk: Show symbolic clock flags in debugfs
clk: Improve flags doc for of_clk_detect_critical()
* clk-renesas:
clk: renesas: r8a7796: Add FDP clock
clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend
clk: renesas: mstp: Keep wakeup sources active during system suspend
clk: renesas: r8a77970: Add LVDS clock
* clk-meson:
clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
clk: meson-axg: make local symbol axg_gp0_params_table static
clk: meson-axg: fix return value check in axg_clkc_probe()
clk: meson: mpll: use 64-bit maths in params_from_rate
clk: meson-axg: add clock controller drivers
clk: meson-axg: add clocks dt-bindings required header
dt-bindings: clock: add compatible variant for the Meson-AXG
clk: meson: make the spinlock naming more specific
clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks
clk: meson: gxbb: fix wrong clock for SARADC/SANA
* clk-iproc:
clk: iproc: Minor tidy up of iproc pll data structures
clk: iproc: Allow plls to do minor rate changes without reset
clk: iproc: Fix error in the pll post divider rate calculation
clk: iproc: Allow iproc pll to runtime calculate vco parameters
* clk-mvebu:
clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()
* clk-qcom-a53:
clk: qcom: Add APCS clock controller support
clk: qcom: Add regmap mux-div clocks support
clk: qcom: Add A53 PLL support
* clk-at91:
clk: at91: pmc: Support backup for programmable clocks
clk: at91: pmc: Save SCSR during suspend
clk: at91: pmc: Wait for clocks when resuming
* clk-imx7ulp:
clk: Don't touch hardware when reparenting during registration
* clk-axigen:
clk: axi-clkgen: Round closest in round_rate() and recalc_rate()
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()
* clk-si5351:
clk: si5351: _si5351_clkout_reset_pll() can be static
clk: si5351: Do not enable parent clocks on probe
clk: si5351: Rename internal plls to avoid name collisions
clk: si5351: Apply PLL soft reset before enabling the outputs
clk: si5351: Add DT property to enable PLL reset
clk: si5351: implement remove handler
* clk-pxa:
clk: pxa: unbreak lookup of CLK_POUT
include IR, SPI and ethernet MAC support for the new AXG family SoCs.
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Merge tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
Another round of 64-bit DT changes for the new Amlogic SoCs. These
include IR, SPI and ethernet MAC support for the new AXG family SoCs.
* tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: meson-axg: enable ethernet for A113D S400 board
ARM64: dts: meson-axg: add ethernet mac controller
ARM64: dts: meson-axg: add the SPICC controller
ARM64: dts: meson-axg: enable IR controller
arm64: dts: meson-axg: switch uart_ao clock to CLK81
clk: meson-axg: add clocks dt-bindings required header
dt-bindings: clock: add compatible variant for the Meson-AXG
Signed-off-by: Olof Johansson <olof@lixom.net>
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.
This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a6 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
DT unit addresses should be lower case hex. Fix all the
binding examples.
Converted with the following command from Krzysztof Kozlowski:
sed -e 's/@\([a-fA-F0-9_-]*\) {/@\L\1 {/' -i $(find Documentation/devicetree/bindings -name '*.txt')
Signed-off-by: Rob Herring <robh@kernel.org>
Add optional output clock DT property to enable PLL reset when a clock
output is enabled.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Introduce a new binding with its documentation for Spreadtrum clock
sub-framework.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Update the documentation to support clock driver for the Amlogic's
Meson-AXG SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Document the DT binding for stub clock which is used for CPU,
GPU and DDR frequency scaling.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds device tree bindings for Qualcomm SPMI PMIC
clock divider module.
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
[sboyd: Moved file to match compatible of binding]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:
Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
Converted using the following command:
find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ ])\@0x([0-9a-f])/$1\@$2/g' {} +
This is a follow up to commit 48c926cd34
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Rob Herring <robh@kernel.org>
large change that introduces runtime PM support to the clk framework. Now we
properly call runtime PM operations on the device providing a clk when the clk
is in use. This helps on SoCs where the clks provided by a device need
something to be powered on before using the clks, like power domains or
regulators. It also helps power those things down when clks aren't in use. The
other core change is a devm API addition for clk providers so we can get rid of
a bunch of clk driver remove functions that are just doing
of_clk_del_provider().
Outside of the core, we have the usual addition of clk drivers and smattering
of non-critical fixes to existing drivers. The biggest diff is support for
Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch
of data.
By the way, we're trying something new here where we build the tree up with
topic branches. We plan to work this into our workflow so that we don't step
on each other's toes, and so the fixes branch can be merged on an as-needed
basis.
Core:
- Runtime PM support for clk providers
- devm API for of_clk_add_hw_provider()
New Drivers:
- Mediatek MT2712 and MT7622
- Renesas R-Car V3M SoC
Updates:
- Runtime PM support for Samsung exynos5433/exynos4412 providers
- Removal of clkdev aliases on Samsung SoCs
- Convert clk-gpio to use gpio descriptors
- Various driver cleanups to match kernel coding style
- Amlogic Video Processing Unit VPU and VAPB clks
- Sigma-delta modulation for Allwinner audio PLLs
- Allwinner A83t Display clks
- Support for the second display unit clock on Renesas RZ/G1E
- Suspend/resume support for Renesas R-Car Gen3 CPG/MSSR
- New clock ids for Rockchip rk3188 and rk3368 SoCs
- Various 'const' markings on clk_ops structures
- RPM clk support on Qualcomm MSM8996/MSM8660 SoCs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have two changes to the core framework this time around.
The first being a large change that introduces runtime PM support to
the clk framework. Now we properly call runtime PM operations on the
device providing a clk when the clk is in use. This helps on SoCs
where the clks provided by a device need something to be powered on
before using the clks, like power domains or regulators. It also helps
power those things down when clks aren't in use.
The other core change is a devm API addition for clk providers so we
can get rid of a bunch of clk driver remove functions that are just
doing of_clk_del_provider().
Outside of the core, we have the usual addition of clk drivers and
smattering of non-critical fixes to existing drivers. The biggest diff
is support for Mediatek MT2712 and MT7622 SoCs, but those patches
really just add a bunch of data.
By the way, we're trying something new here where we build the tree up
with topic branches. We plan to work this into our workflow so that we
don't step on each other's toes, and so the fixes branch can be merged
on an as-needed basis.
Summary:
Core:
- runtime PM support for clk providers
- devm API for of_clk_add_hw_provider()
New Drivers:
- Mediatek MT2712 and MT7622
- Renesas R-Car V3M SoC
Updates:
- runtime PM support for Samsung exynos5433/exynos4412 providers
- removal of clkdev aliases on Samsung SoCs
- convert clk-gpio to use gpio descriptors
- various driver cleanups to match kernel coding style
- Amlogic Video Processing Unit VPU and VAPB clks
- sigma-delta modulation for Allwinner audio PLLs
- Allwinner A83t Display clks
- support for the second display unit clock on Renesas RZ/G1E
- suspend/resume support for Renesas R-Car Gen3 CPG/MSSR
- new clock ids for Rockchip rk3188 and rk3368 SoCs
- various 'const' markings on clk_ops structures
- RPM clk support on Qualcomm MSM8996/MSM8660 SoCs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: stm32h7: fix test of clock config
clk: pxa: fix building on older compilers
clk: sunxi-ng: a83t: Fix i2c buses bits
clk: ti: dra7-atl-clock: fix child-node lookups
clk: qcom: common: fix legacy board-clock registration
clk: uniphier: fix DAPLL2 clock rate of Pro5
clk: uniphier: fix parent of miodmac clock data
clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()
clk: hi3660: fix incorrect uart3 clock freqency
clk: kona-setup: Delete error messages for failed memory allocations
ARC: clk: fix spelling mistake: "configurarion" -> "configuration"
clk: cdce925: remove redundant check for non-null parent_name
clk: versatile: Improve sizeof() usage
clk: versatile: Delete error messages for failed memory allocations
clk: ux500: Improve sizeof() usage
clk: ux500: Delete error messages for failed memory allocations
clk: spear: Delete error messages for failed memory allocations
clk: ti: Delete error messages for failed memory allocations
clk: mmp: Adjust checks for NULL pointers
...
We add device tree files for a couple of additional SoCs in various areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking,
Amlogic A113D for audio, and Renesas R-Car V3M for automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic
and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues that
the latest version of 'dtc' now warns about. Unfortunately there is still
a lot left to do.
A rework of the ARM foundation model introduced several new files
for common variations of the model.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"We add device tree files for a couple of additional SoCs in various
areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
networking, Amlogic A113D for audio, and Renesas R-Car V3M for
automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
Amlogic and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues
that the latest version of 'dtc' now warns about. Unfortunately there
is still a lot left to do.
A rework of the ARM foundation model introduced several new files for
common variations of the model"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
dt-bindings: bus: Add documentation for the Technologic Systems NBUS
arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
ARM: dts: owl-s500: Add CubieBoard6
dt-bindings: arm: actions: Add CubieBoard6
ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
arm: dts: mt7623: remove unused compatible string for pio node
arm: dts: mt7623: update usb related nodes
arm: dts: mt7623: update crypto node
ARM: dts: sun8i: a711: Enable USB OTG
ARM: dts: sun8i: a711: Add regulator support
ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
ARM: dts: sunxi: Add dtsi for AXP81x PMIC
arm64: dts: allwinner: H5: Restore EMAC changes
...
- kbuild cleanups and improvements for dtbs
- Code clean-up of overlay code and fixing for some long standing memory
leak and race condition in applying overlays
- Improvements to DT memory usage making sysfs/kobjects optional and
skipping unflattening of disabled nodes. This is part of kernel
tinification efforts.
- Final piece of removing storing the full path for every DT node. The
prerequisite conversion of printk's to use device_node format
specifier happened in 4.14.
- Sync with current upstream dtc. This brings additional checks to dtb
compiling.
- Binding doc tree wide removal of leading 0s from examples
- RTC binding documentation adding missing devices and some
consolidation of duplicated bindings
- Vendor prefix documentation for nutsboard, Silicon Storage Technology,
shimafuji, Tecon Microprocessor Technologies, DH electronics GmbH,
Opal Kelly, and Next Thing
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Merge tag 'devicetree-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull DeviceTree updates from Rob Herring:
"A bigger diffstat than usual with the kbuild changes and a tree wide
fix in the binding documentation.
Summary:
- kbuild cleanups and improvements for dtbs
- Code clean-up of overlay code and fixing for some long standing
memory leak and race condition in applying overlays
- Improvements to DT memory usage making sysfs/kobjects optional and
skipping unflattening of disabled nodes. This is part of kernel
tinification efforts.
- Final piece of removing storing the full path for every DT node.
The prerequisite conversion of printk's to use device_node format
specifier happened in 4.14.
- Sync with current upstream dtc. This brings additional checks to
dtb compiling.
- Binding doc tree wide removal of leading 0s from examples
- RTC binding documentation adding missing devices and some
consolidation of duplicated bindings
- Vendor prefix documentation for nutsboard, Silicon Storage
Technology, shimafuji, Tecon Microprocessor Technologies, DH
electronics GmbH, Opal Kelly, and Next Thing"
* tag 'devicetree-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
dt-bindings: usb: add #phy-cells to usb-nop-xceiv
dt-bindings: Remove leading zeros from bindings notation
kbuild: handle dtb-y and CONFIG_OF_ALL_DTBS natively in Makefile.lib
MIPS: dts: remove bogus bcm96358nb4ser.dtb from dtb-y entry
kbuild: clean up *.dtb and *.dtb.S patterns from top-level Makefile
.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore
.gitignore: sort normal pattern rules alphabetically
dt-bindings: add vendor prefix for Next Thing Co.
scripts/dtc: Update to upstream version v1.4.5-6-gc1e55a5513e9
of: dynamic: fix memory leak related to properties of __of_node_dup
of: overlay: make pr_err() string unique
of: overlay: pr_err from return NOTIFY_OK to overlay apply/remove
of: overlay: remove unneeded check for NULL kbasename()
of: overlay: remove a dependency on device node full_name
of: overlay: simplify applying symbols from an overlay
of: overlay: avoid race condition between applying multiple overlays
of: overlay: loosen overly strict phandle clash check
of: overlay: expand check of whether overlay changeset can be removed
of: overlay: detect cases where device tree may become corrupt
of: overlay: minor restructuring
...
Improve the binding example by removing all the leading zeros to fix the
following dtc warnings:
Warning (unit_address_format): Node /XXX unit name should not have leading 0s
Converted using the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"`
Some unnecessary changes were manually fixed.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Add all RPM controlled clocks on msm8996 platform
[srini: Fixed various issues with offsets and made names specific to msm8996]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These compatible strings need to be added to extend support
for the RPM CC to cover MSM8660/APQ8060. We also need to add
enumberators to the include file for a few clocks that were
missing.
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The concept of "active" clocks is just explained in a bried comment in the
device driver, let's explain it a bit more in the device tree bindings
so everyone understands this.
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- Add support for the second display unit clock on RZ/G1E,
- Add git repository to MAINTAINERS,
- Add suspend/resume support for R-Car Gen3 CPG/MSSR,
- Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the second display unit clock on RZ/G1E,
- Add git repository to MAINTAINERS,
- Add suspend/resume support for R-Car Gen3 CPG/MSSR,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Restore R clock during resume
clk: renesas: rcar-gen3: Restore SDHI clocks during resume
clk: renesas: div6: Restore clock state during resume
clk: renesas: cpg-mssr: Add support to restore core clocks during resume
clk: renesas: cpg-mssr: Restore module clocks during resume
MAINTAINERS: Add git repository to Renesas clock driver section
clk: renesas: cpg-mssr: Add du1 clock to R8A7745
clk: renesas: rz: clk-rz is meant for RZ/A1
clk: renesas: r8a77995: Correct parent clock of INTC-AP
clk: renesas: r8a7796: Correct parent clock of INTC-AP
clk: renesas: r8a7795: Correct parent clock of INTC-AP
- An addition of separate driver for the Exynos 4412 ISP CMU, needed
to model and properly handle the clock controller's dependencies
on the ISP power domain.
- Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
resume} ops to suppress compiler warnings with CONFIG_PM disabled.
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Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
- An addition of separate driver for the Exynos 4412 ISP CMU, needed
to model and properly handle the clock controller's dependencies
on the ISP power domain.
- Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
resume} ops to suppress compiler warnings with CONFIG_PM disabled.
* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add a separate driver for Exynos4412 ISP clocks
clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
clk: samsung: Instantiate Exynos4412 ISP clocks only when available
clk: samsung: exynos5433: mark PM functions as __maybe_unused
please pull the following:
- Eric adds support for the CLCD and PWM controller on Cygnus chis
- Loic fixes the console path on the Raspberry Pi 3 (already submitted as
fixes) and then proceeds with enabling the BCM43438 bluetooth chip on
the Raspberry Pi 3
- Rafal specifies the USB ports on the Luxul XWR-1200
- Dan adds support for the Luxul ABR-4500 based on BCM47094, the Luxul XAP-810
and XAP-1440 both based on BCM53573
- Florian adds support for the Broadcom Hurricane 2 SoC by adding general
machine binding, clock binding, SoC DTS include file and a DTS for the
Ubiquiti Networks UniFi Switch 8
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Merge tag 'arm-soc/for-4.15/devicetree' of http://github.com/Broadcom/stblinux into next/dt
Pull "Broadcom devicetree changes for 4.15" from Florian Fainelli:
This pull request contains Broadcom ARM-based Device Tree changes for 4.15,
please pull the following:
- Eric adds support for the CLCD and PWM controller on Cygnus chis
- Loic fixes the console path on the Raspberry Pi 3 (already submitted as
fixes) and then proceeds with enabling the BCM43438 bluetooth chip on
the Raspberry Pi 3
- Rafal specifies the USB ports on the Luxul XWR-1200
- Dan adds support for the Luxul ABR-4500 based on BCM47094, the Luxul XAP-810
and XAP-1440 both based on BCM53573
- Florian adds support for the Broadcom Hurricane 2 SoC by adding general
machine binding, clock binding, SoC DTS include file and a DTS for the
Ubiquiti Networks UniFi Switch 8
* tag 'arm-soc/for-4.15/devicetree' of http://github.com/Broadcom/stblinux:
ARM: dts: Hurricane 2: Add basic support for Ubiquiti UniFi Switch 8
dt-bindings: Add Ubiquiti Networks vendor prefix
ARM: dts: Add Broadcom Hurricane 2 DTS include file
dt-bindings: Document Broadcom Hurricane 2 clocks
dt-bindings: Add documentation for Broadcom Hurricane 2 SoCs
ARM: dts: BCM53573: Add DT for Luxul XAP-1440
ARM: dts: BCM53573: Add DT for Luxul XAP-810
ARM: dts: BCM5301X: Add DT for Luxul ABR-4500
ARM: dts: BCM5301X: Add DT for Luxul XBR-4500
ARM: dts: BCM5301X: Specify USB ports for USB LED of Luxul XWR-1200
ARM: dts: bcm2837-rpi-3-b: Add bcm43438 serial slave
ARM: dts: bcm283x: Fix console path on RPi3
ARM: dts: cygnus: Add the PWM node
ARM: dts: cygnus: Add the CLCD controller
- Add support for the new R-Car V3M SoC,
- Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new R-Car V3M SoC,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen2: Delete error message for failed memory allocation
clk: renesas: mstp: Delete error messages for failed memory allocations
clk: renesas: cpg-mssr: Add R8A77970 support
dt-bindings: clock: Add R8A77970 CPG core clock definitions
The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT
bindings and clk-rz driver apply to RZ/A1 only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are
located in the ISP power domain. Because those registers are also
located in a different memory region than the main clock controller,
support for them can be provided by a separate clock controller.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add a Device Tree binding document for the Broadcom Hurricane 2 SoC
which is an iProc based system.
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* clk-pm-runtime:
clk: samsung: exynos-audss: Add support for runtime PM
clk: samsung: exynos-audss: Use local variable for controller's device
clk: samsung: exynos5433: Add support for runtime PM
clk: samsung: Add support for runtime PM
clk: Add support for runtime PM
The clock-cell size is 1 on stm32h7 plaform.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Fixes: 3e4d618b07 ("clk: stm32h7: Add stm32h743 clock driver")
Signed-off-by: Rob Herring <robh@kernel.org>
Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
the sunxi-ng framework. Otherwise, the heavy hitters are various drivers
for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are some other
new clk drivers in here too but overall this is just a bunch of clk
drivers for various different pieces of hardware and a collection of
non-critical fixes for clk drivers.
New Drivers:
- Allwinner R40 SoCs
- Renesas R-Car Gen3 USB 2.0 clock selector PHY
- Atmel AT91 audio PLL
- Uniphier PXs3 SoCs
- ARC HSDK Board PLLs
- AXS10X Board PLLs
- STMicroelectronics STM32H743 SoCs
Removed Drivers:
- Non-compiling mb86s7x support
Updates:
- Allwinner A10/A20 SoCs converted to sunxi-ng framework
- Allwinner H3 CPU clk fixes
- Renesas R-Car D3 SoC
- Renesas V2H and M3-W modules
- Samsung Exynos5420/5422/5800 audio fixes
- Rockchip fractional clk approximation fixes
- Rockchip rk3126 SoC support within the rk3128 driver
- Amlogic gxbb CEC32 and sd_emmc clks
- Amlogic meson8b reset controller support
- IDT VersaClock 5P49V5925/5P49V6901 support
- Qualcomm MSM8996 SMMU clks
- Various 'const' applications for struct clk_ops
- si5351 PLL reset bugfix
- Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
- Assorted Tegra clk driver fixes
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The diff is dominated by the Allwinner A10/A20 SoCs getting converted
to the sunxi-ng framework. Otherwise, the heavy hitters are various
drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
some other new clk drivers in here too but overall this is just a
bunch of clk drivers for various different pieces of hardware and a
collection of non-critical fixes for clk drivers.
New Drivers:
- Allwinner R40 SoCs
- Renesas R-Car Gen3 USB 2.0 clock selector PHY
- Atmel AT91 audio PLL
- Uniphier PXs3 SoCs
- ARC HSDK Board PLLs
- AXS10X Board PLLs
- STMicroelectronics STM32H743 SoCs
Removed Drivers:
- Non-compiling mb86s7x support
Updates:
- Allwinner A10/A20 SoCs converted to sunxi-ng framework
- Allwinner H3 CPU clk fixes
- Renesas R-Car D3 SoC
- Renesas V2H and M3-W modules
- Samsung Exynos5420/5422/5800 audio fixes
- Rockchip fractional clk approximation fixes
- Rockchip rk3126 SoC support within the rk3128 driver
- Amlogic gxbb CEC32 and sd_emmc clks
- Amlogic meson8b reset controller support
- IDT VersaClock 5P49V5925/5P49V6901 support
- Qualcomm MSM8996 SMMU clks
- Various 'const' applications for struct clk_ops
- si5351 PLL reset bugfix
- Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
- Assorted Tegra clk driver fixes"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
clk: si5351: fix PLL reset
ASoC: atmel-classd: remove aclk clock
ASoC: atmel-classd: remove aclk clock from DT binding
clk: at91: clk-generated: make gclk determine audio_pll rate
clk: at91: clk-generated: create function to find best_diff
clk: at91: add audio pll clock drivers
dt-bindings: clk: at91: add audio plls to the compatible list
clk: at91: clk-generated: remove useless divisor loop
clk: mb86s7x: Drop non-building driver
clk: ti: check for null return in strrchr to avoid null dereferencing
clk: Don't write error code into divider register
clk: uniphier: add video input subsystem clock
clk: uniphier: add audio system clock
clk: stm32h7: Add stm32h743 clock driver
clk: gate: expose clk_gate_ops::is_enabled
clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
clk: uniphier: add PXs3 clock data
clk: hi6220: change watchdog clock source
clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
clk: cs2000: Add cs2000_set_saved_rate
...
As usual, device tree updates is the bulk of our material in this merge
window. This time around, 559 patches affecting both 32- and 64-bit
platforms.
Changes are too many to list individually, but some of the larger ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also several
new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board
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Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM/arm64 Devicetree updates from Olof Johansson:
"As usual, device tree updates is the bulk of our material in this
merge window. This time around, 559 patches affecting both 32- and
64-bit platforms.
Changes are too many to list individually, but some of the larger
ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also
several new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board"
* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
ARM: dts: at91: at91sam9g45: add AC97
arm64: dts: marvell: mcbin: enable more networking ports
arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
arm64: dts: marvell: add TX interrupts for PPv2.2
arm64: dts: uniphier: add PXs3 SoC support
ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
ARM: dts: uniphier: fix size of sdctrl nodes
ARM: dts: uniphier: add AIDET nodes
arm64: dts: uniphier: fix size of sdctrl node
arm64: dts: uniphier: add AIDET nodes
Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
arm64: dts: uniphier: add reset controller node of analog amplifier
arm64: dts: marvell: add Device Tree files for Armada-8KP
arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
dt-bindings: add rk3399-q7 SoM
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
...
This patch adds support for runtime PM to Exynos Audio SubSystem driver to
enable full support for audio power domain on Exynos5 SoCs. The main change
is moving register saving and restoring code from system sleep PM ops to
runtime PM ops and implementing system sleep PM ops with generic
pm_runtime_force_suspend/resume helpers. Runtime PM of the Exynos AudSS
device is managed from clock core depending on the preparation status
of the provided clocks.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-6-git-send-email-m.szyprowski@samsung.com
Add runtime pm support for all clock controller units (CMU), which belong
to power domains and require special handling during on/off operations.
Typically special values has to be written to MUX registers to change
internal clocks parents to OSC clock before turning power off. During such
operation all clocks, which enter CMU has to be enabled to let MUX to
stabilize. Also for each CMU there is one special parent clock, which has
to be enabled all the time when any access to CMU registers is being done.
This patch solves most of the mysterious external abort and freeze issues
caused by a lack of proper parent CMU clock enabled or incorrect turn off
procedure.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-4-git-send-email-m.szyprowski@samsung.com
- Convert more DT code to use of_property_read_* API.
- Improve DT overlay support when adding multiple overlays.
- Convert printk's to %pOF format specifiers. Most went via subsystem
trees, but picked up the remaining orphans.
- Correct unittests to use preferred "okay" for "status" property value.
- Add a KASLR seed property.
- Vendor prefixes for Mellanox, Theobroma System, Adaptrum, Moxa.
- Fix modalias buffer handling.
- Clean-up of include paths for building dtbs.
- Add bindings for amc6821, isl1208, tsl2x7x, srf02, and srf10 devices.
- Add nvmem bindings for MediaTek MT7623 and MT7622 SoC.
- Add compatible string for Allwinner H5 Mali-450 GPU.
- Fix links to old OpenFirmware docs with new mirror on devicetree.org.
- Remove status property from binding doc examples.
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Merge tag 'devicetree-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull DeviceTree updates from Rob Herring:
"There's a few orphans in the conversion to %pOF printf specifiers
included here that no one else picked up.
Summary:
- Convert more DT code to use of_property_read_* API.
- Improve DT overlay support when adding multiple overlays
- Convert printk's to %pOF format specifiers. Most went via subsystem
trees, but picked up the remaining orphans
- Correct unittests to use preferred "okay" for "status" property
value
- Add a KASLR seed property
- Vendor prefixes for Mellanox, Theobroma System, Adaptrum, Moxa
- Fix modalias buffer handling
- Clean-up of include paths for building dtbs
- Add bindings for amc6821, isl1208, tsl2x7x, srf02, and srf10
devices
- Add nvmem bindings for MediaTek MT7623 and MT7622 SoC
- Add compatible string for Allwinner H5 Mali-450 GPU
- Fix links to old OpenFirmware docs with new mirror on
devicetree.org
- Remove status property from binding doc examples"
* tag 'devicetree-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (45 commits)
devicetree: Adjust status "ok" -> "okay" under drivers/of/
dt-bindings: Remove "status" from examples
dt-bindings: pinctrl: sh-pfc: Use generic node name
dt-bindings: Add vendor Mellanox
dt-binding: net/phy: fix interrupts description
virt: Convert to using %pOF instead of full_name
macintosh: Convert to using %pOF instead of full_name
ide: pmac: Convert to using %pOF instead of full_name
microblaze: Convert to using %pOF instead of full_name
dt-bindings: usb: musb: Grammar s/the/to/, s/is/are/
of: Use PLATFORM_DEVID_NONE definition
of/device: Fix of_device_get_modalias() buffer handling
of/device: Prevent buffer overflow in of_device_modalias()
dt-bindings: add amc6821, isl1208 trivial bindings
dt-bindings: add vendor prefix for Theobroma Systems
of: search scripts/dtc/include-prefixes path for both CPP and DTC
of: remove arch/$(SRCARCH)/boot/dts from include search path for CPP
of: remove drivers/of/testcase-data from include search path for CPP
of: return of_get_cpu_node from of_cpu_device_node_get if CPUs are not registered
iio: srf08: add device tree binding for srf02 and srf10
...
Pretty much any node can have a status property, so it doesn't need to
be in examples.
Converted with the following command and removed examples with SoC and
board specific splits:
git grep -l -E 'status.*=.*' Documentation/devicetree/ | xargs sed -i -E '/\sstatus.*=.*"(disabled|ok|okay)/d'
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.
The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.
This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch enables clocks for STM32H743 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
for MFD changes:
Acked-by: Lee Jones <lee.jones@linaro.org>
for DT-Bindings
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework.
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Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull more Allwinner clock changes from Maxime Ripard:
* Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework
* tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Add sun4i/sun7i CCU driver
dt-bindings: List devicetree binding for the CCU of Allwinner A10
dt-bindings: List devicetree binding for the CCU of Allwinner A20
HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.
We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.
As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.
By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Allwinner A10 is now driven by sunxi-ng CCU driver.
Add devicetree binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner A20 is now driven by sunxi-ng CCU driver.
Add devicetree binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Add more module clocks for R-Car V2H and M3-W,
- Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
- Add support for the new R-Car D3 SoC,
- Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
- Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
* Add more module clocks for R-Car V2H and M3-W,
* Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
* Add support for the new R-Car D3 SoC,
* Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
* Small fixes and cleanups.
* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add USB3.0 clock
clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
clk: renesas: cpg-mssr: Add R8A77995 support
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
clk: renesas: Add r8a77995 CPG Core Clock Definitions
clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
clk: renesas: rcar-gen3-cpg: Drop superfluous variable
clk: renesas: Allow compile-testing of all (sub)drivers
clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
clk: renesas: div6: Document fields used for parent selection
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).
Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).
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Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk driver updates from Heiko Stuebner:
The biggest change is fixing the jitter on the fractional clock-type
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).
Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).
* tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rv1108 clk_mac sel register description
clk: rockchip: rename rv1108 macphy clock to mac
clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks
clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id
clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID
clk: rockchip: add rk3228 sclk_sdio_src ID
clk: rockchip: add special approximation to fix up fractional clk's jitter
clk: fractional-divider: allow overriding of approximation
clk: rockchip: modify rk3128 clk driver to also support rk3126
dt-bindings: add documentation for rk3126 clock
clk: rockchip: add some critical clocks for rv1108 SoC
clk: rockchip: rename some of clks for rv1108 SoC
clk: rockchip: fix up some clks describe error for rv1108 SoC
clk: rockchip: support more clks for rv1108
clk: rockchip: fix up the pll clks error for rv1108 SoC
clk: rockchip: support more rates for rv1108 cpuclk
clk: rockchip: fix up indentation of some RV1108 clock-ids
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
clk: rockchip: add more clk ids for rv1108
Usual improvements:
- Added support for fixed post-divider on divider and NKM-style clocks
- Added driver for R40 CCU
Non critical fixes (from round 1):
- Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
- Make fractional clock modes really used and correctly configured
- Make H3 cpu clock rate change correctly to be used with cpufreq
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Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock changes from Chen-Yu Tsai:
* Added support for fixed post-divider on divider and NKM-style clocks
* Added driver for R40 CCU
* Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
* Make fractional clock modes really used and correctly configured
* Make H3 cpu clock rate change correctly to be used with cpufreq
* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: support R40 SoC
dt-bindings: add compatible string for Allwinner R40 CCU
clk: sunxi-ng: nkm: add support for fixed post-divider
clk: sunxi-ng: div: Add support for fixed post-divider
dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Wait for lock when using fractional mode
clk: sunxi-ng: Make fractional helper less chatty
clk: sunxi-ng: multiplier: Fix fractional mode
clk: sunxi-ng: Fix fractional mode for N-M clocks
clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
R-Car USB 2.0 controller can change the clock source from an oscillator
to an external clock via a register. So, this patch adds support
the clock source selector as a clock driver.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.
Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
The bindings were not updated when the sun5i CCU driver was added in
commit 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: Jonathan Liu <net147@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
On the first revision of the bindings, only the gates + resets were known
in the AO Clock HW, but more registers used to configures AO clock are known
to be spread among the AO register space.
This patch adds a parent node for the entire system control zone for the AO
domain then moves the clock controller as a subnode of the system control
node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.
This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The old place is Documentation/devicetree/bindings/clock/ that would
let people hard to find how to use MediaTek cpufreq driver, so moving
it to the appropriate place as other cpufreq drivers done would be
better.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.
We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.
As of today we add support for PLLs that generate clock for the
following devices:
* ARC core on AXC CPU tiles.
* ARC PGU on ARC SDP Mainboard.
and more to come later.
By this patch we add support for two plls (arc core pll and pgu pll),
so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
regular probing for pgu pll.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
[sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
make of_axs10x_pll_clk_setup() unregister clk on failure]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clock consumer usage description was erroneously referring to
couple of dt-binding headers that are no longer valid. The definition
and/or usage of these headers is incorrect and the only file present
at the moment, dt-bindings/soc/k2g.h is also being cleaned up. The
examples in this binding were updated properly, but the update to
description was missed out. So, fix this.
Fixes: 8f306cfe43 ("Documentation: dt: Add TI SCI clock driver")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Rob Herring <robh@kernel.org>
checkpatch.pl doesn't know how to expand "silabs,si5351{a,a-msop,b,c}"
and so generates warnings about si5351-compatible devices appearing to
be un-documented. Resolve this by documenting the compatible options
supported by the clk-si5351 driver individually.
Signed-off-by: Brandon Streiff <brandon.streiff@ni.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Pull MIPS updates from Ralf Baechle:
"Boston platform support:
- Document DT bindings
- Add CLK driver for board clocks
CM:
- Avoid per-core locking with CM3 & higher
- WARN on attempt to lock invalid VP, not BUG
CPS:
- Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6
- Prevent multi-core with dcache aliasing
- Handle cores not powering down more gracefully
- Handle spurious VP starts more gracefully
DSP:
- Add lwx & lhx missaligned access support
eBPF:
- Add MIPS support along with many supporting change to add the
required infrastructure
Generic arch code:
- Misc sysmips MIPS_ATOMIC_SET fixes
- Drop duplicate HAVE_SYSCALL_TRACEPOINTS
- Negate error syscall return in trace
- Correct forced syscall errors
- Traced negative syscalls should return -ENOSYS
- Allow samples/bpf/tracex5 to access syscall arguments for sane
traces
- Cleanup from old Kconfig options in defconfigs
- Fix PREF instruction usage by memcpy for MIPS R6
- Fix various special cases in the FPU eulation
- Fix some special cases in MIPS16e2 support
- Fix MIPS I ISA /proc/cpuinfo reporting
- Sort MIPS Kconfig alphabetically
- Fix minimum alignment requirement of IRQ stack as required by
ABI / GCC
- Fix special cases in the module loader
- Perform post-DMA cache flushes on systems with MAARs
- Probe the I6500 CPU
- Cleanup cmpxchg and add support for 1 and 2 byte operations
- Use queued read/write locks (qrwlock)
- Use queued spinlocks (qspinlock)
- Add CPU shared FTLB feature detection
- Handle tlbex-tlbp race condition
- Allow storing pgd in C0_CONTEXT for MIPSr6
- Use current_cpu_type() in m4kc_tlbp_war()
- Support Boston in the generic kernel
Generic platform:
- yamon-dt: Pull YAMON DT shim code out of SEAD-3 board
- yamon-dt: Support > 256MB of RAM
- yamon-dt: Use serial* rather than uart* aliases
- Abstract FDT fixup application
- Set RTC_ALWAYS_BCD to 0
- Add a MAINTAINERS entry
core kernel:
- qspinlock.c: include linux/prefetch.h
Loongson 3:
- Add support
Perf:
- Add I6500 support
SEAD-3:
- Remove GIC timer from DT
- Set interrupt-parent per-device, not at root node
- Fix GIC interrupt specifiers
SMP:
- Skip IPI setup if we only have a single CPU
VDSO:
- Make comment match reality
- Improvements to time code in VDSO"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits)
locking/qspinlock: Include linux/prefetch.h
MIPS: Fix MIPS I ISA /proc/cpuinfo reporting
MIPS: Fix minimum alignment requirement of IRQ stack
MIPS: generic: Support MIPS Boston development boards
MIPS: DTS: img: Don't attempt to build-in all .dtb files
clk: boston: Add a driver for MIPS Boston board clocks
dt-bindings: Document img,boston-clock binding
MIPS: Traced negative syscalls should return -ENOSYS
MIPS: Correct forced syscall errors
MIPS: Negate error syscall return in trace
MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select
MIPS16e2: Provide feature overrides for non-MIPS16 systems
MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo
MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions
MIPS: MIPS16e2: Identify ASE presence
MIPS: VDSO: Fix a mismatch between comment and preprocessor constant
MIPS: VDSO: Add implementation of gettimeofday() fallback
MIPS: VDSO: Add implementation of clock_gettime() fallback
MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()
MIPS: Use current_cpu_type() in m4kc_tlbp_war()
...
Add device tree binding documentation for the clocks provided by the
MIPS Boston development board from Imagination Technologies, and a
header file describing the available clocks for use by device trees &
driver.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add the compatible strings and the include file for ipq8074 gcc
clock controller.
Acked-by: Rob Herring <robh@kernel.org> (bindings)
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Add new compatible to the meson8 clock controller for meson8b
* Add missing parents to gxbb clk81
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Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clk driver updates from Jerome Brunet:
* Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
* Add new compatible to the meson8 clock controller for meson8b
* Add missing parents to gxbb clk81
* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
clk: meson: gxbb: add all clk81 parents
clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
clk: meson8b: export the ethernet gate clock
clk: meson8b: export the USB clocks
clk: meson8b: export the gate clock for the HW random number generator
clk: meson8b: export the SDIO clock
clk: meson8b: export the SAR ADC clocks
Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.
There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.
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Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches from Maxime Ripard:
Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.
There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.
* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
clk: sunxi-ng: Move all clock types to a library
clk: sunxi-ng: a83t: Add support for A83T's PRCM
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
clk: sunxi-ng: a83t: Fix audio PLL divider offset
clk: sunxi-ng: a83t: Fix PLL lock status register offset
clk: sunxi-ng: Add driver for A83T CCU
clk: sunxi-ng: Support multiple variable pre-dividers
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
clk: sunxi-ng: sun5i: Export video PLLs
clk: sunxi-ng: mux: Re-adjust parent rate
clk: sunxi-ng: mux: Change pre-divider application function prototype
clk: sunxi-ng: mux: split out the pre-divider computation code
clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
clk: sunxi-ng: div: Switch to divider_round_rate
clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
clk: divider: Make divider_round_rate take the parent clock
clk: sunxi-ng: explicitly include linux/spinlock.h
clk: sunxi-ng: add support for DE2 CCU
...
Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.
The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.
Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.
Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.
The reasons for using #clock-cells = <2> are:
1. We need to specify the clkctrl offset from the instance base. Otherwise
we end up with a large number of device tree nodes that need to be
patched when new clocks are discovered in a clkctrl clock with minor
hardware revision changes for example
2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
need to use a separate cell for optional gate clocks to avoid address
space conflicts
There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.
For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
table and the usual bunch of some new clock-ids and some clocks marked as
critical.
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Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
critical.
* tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: mark some special clk as critical on rk3368
clk: rockchip: mark noc and some special clk as critical on rk3288
clk: rockchip: mark noc and some special clk as critical on rk3228
clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
clk: rockchip: add clock controller for rk3128
dt-bindings: add bindings for rk3128 clock controller
clk: rockchip: export more rk3228 clocks ids
clk: rockchip: add ids for rk3399 testclks used for camera handling
clk: rockchip: add dt-binding header for rk3128
clk: rockchip: fix up the RK3228 clk cpu setting table
clk: rockchip: add clock-ids for more rk3228 clocks
clk: rockchip: add ids for camera on rk3399
Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI
protocol.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.
In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).
The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
The PRCM also has controls for various power domains. These are not
supported yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
- Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
for module resets, which are not supported by the existing driver,
- Rework Kconfig and Makefile logic,
- Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
clk: renesas: Updates for v4.13
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
- Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
for module resets, which are not supported by the existing driver,
- Rework Kconfig and Makefile logic,
- Small fixes and cleanups.
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The AR100 clock in the PRCM has parents, one of which is pll-periph from
the main CCU.
Add it to the list of required clocks for the PRCM CCU.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Document use of the Renesas Clock Pulse Generator / Module Standby and
Software Reset DT Bindings for various member of the R-Car Gen2 family
(H2, M2-W, V2H, M2-N, and E2).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
to me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core, mostly
small non-critical fixes here and there as well as driver updates for new
and existing hardware support. The biggest things are the TI clk driver
rework to lay the groundwork for clkctrl support in the next merge window
and the AmLogic audio/graphics clk support.
Core:
* clk_possible_parents debugfs file so we know which parents a clk
could possibly have
* Fix to make clk rate change notifiers stop on the first failure instead
of continuing
New Drivers:
* Mediatek MT6797 SoCs
* hi655x PMIC clks
* AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
* Allwinner H5 SoCs and PRCM hardware
Updates:
* Nvidia Tegra T210 cleanups and non-critical fixes
* TI OMAP cleanups in preparation for clkctrl support
* Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
* ZTE zx296718 SoC VGA clks
* Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
* Support for IDT VersaClock 5P49V5935
* Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
changes, but also some new platforms that are worth mentioning:
* Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
Plus (Kevin)
* Orange Pi PC2 (Allwinner H5)
* Freescale LS2088A and LS1088A SoCs
* Expanded support for Nvidia Tegra186 (and Jetson TX2)
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved over
from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using arm/
and arm64/ as include prefixes. This will avoid other local hacks such as
per-file links between the two arch trees (this broke for external mirroring
of DT contents). Now they can just provide their own appropriate dt-include
hierarcy per platform.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved
over from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology
DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more
description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using
arm/ and arm64/ as include prefixes. This will avoid other local hacks
such as per-file links between the two arch trees (this broke for
external mirroring of DT contents). Now they can just provide their
own appropriate dt-include hierarcy per platform"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
ARM: dts: exynos: Use - instead of @ for DT OPP entries
arm: spear6xx: add DT description of the ADC on SPEAr600
arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
arm: spear6xx: switch spear600-evb to the new flash partition DT binding
arm: spear6xx: fix spaces in spear600-evb.dts
arm: spear6xx: use node labels in spear600-evb.dts
arm: spear6xx: add labels to various nodes in spear600.dtsi
ARM: dts: vexpress: fix few unit address format warnings
ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
ARM: dts: at91: sama5d3_xplained: fix ADC vref
ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
ARM: dts: armada-38x: label USB and SATA nodes
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
...
Document the device tree binding for the pin controllers found on the
Armada 37xx SoCs.
Update the binding documention of the xtal clk which is a subnode of this
syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Fixed gpios node]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either integrated crystal or from
external reference clock.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
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Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
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Merge tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.12:
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
dt-bindings: clockgen: Add compatible string for LS1088A
arm64: dts: Add support for FSL's LS1088A SoC
arm64: dts: ls1012a: add crypto node
arm64: dts: ls1012a: add thermal monitor node
arm64: dts: updated sata node on ls1012a platform
arm64: dts: added ecc register address to sata node on ls1046a
arm64: dts: added ecc register address to sata node on ls1043a
arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
arm64: dts: freescale: ls2080a: Split devicetree for code resuability
dt-bindings: Add compatible for LS2088A QDS and RDB board
Signed-off-by: Olof Johansson <olof@lixom.net>
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
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Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next
Same great taste as the previous pull request, but now with 50% less DT
bikeshedding!
Amlogic clock driver updates for v4.12
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.
Moving the binding to the DFX block enables support for different clock
strapping options in hardware.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.
Add its support in our existing H3 CCU driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
to existing clk drivers. The bulk of the work is on Allwinner and
Rockchip SoCs, but there's also an Intel Atom driver in here too.
New Drivers:
- Tegra BPMP firmware
- Hisilicon hi3660 SoCs
- Rockchip rk3328 SoCs
- Intel Atom PMC
- STM32F746
- IDT VersaClock 5P49V5923 and 5P49V5933
- Marvell mv98dx3236 SoCs
- Allwinner V3s SoCs
Removed Drivers:
- Samsung Exynos4415 SoCs
Updates:
- Migrate ABx500 to OF
- Qualcomm IPQ4019 CPU clks and general PLL support
- Qualcomm MSM8974 RPM
- Rockchip non-critical fixes and clk id additions
- Samsung Exynos4412 CPUs
- Socionext UniPhier NAND and eMMC support
- ZTE zx296718 i2s and other audio clks
- Renesas CAN and MSIOF clks for R-Car M3-W
- Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
- TI CDCE913, CDCE937, and CDCE949 clk generators
- Marvell Armada ap806 CPU frequencies
- STM32F4* I2S/SAI support
- Broadcom BCM2835 DSI support
- Allwinner sun5i and A80 conversion to new style clk bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The usual collection of new drivers, non-critical fixes, and updates
to existing clk drivers. The bulk of the work is on Allwinner and
Rockchip SoCs, but there's also an Intel Atom driver in here too.
New Drivers:
- Tegra BPMP firmware
- Hisilicon hi3660 SoCs
- Rockchip rk3328 SoCs
- Intel Atom PMC
- STM32F746
- IDT VersaClock 5P49V5923 and 5P49V5933
- Marvell mv98dx3236 SoCs
- Allwinner V3s SoCs
Removed Drivers:
- Samsung Exynos4415 SoCs
Updates:
- Migrate ABx500 to OF
- Qualcomm IPQ4019 CPU clks and general PLL support
- Qualcomm MSM8974 RPM
- Rockchip non-critical fixes and clk id additions
- Samsung Exynos4412 CPUs
- Socionext UniPhier NAND and eMMC support
- ZTE zx296718 i2s and other audio clks
- Renesas CAN and MSIOF clks for R-Car M3-W
- Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
- TI CDCE913, CDCE937, and CDCE949 clk generators
- Marvell Armada ap806 CPU frequencies
- STM32F4* I2S/SAI support
- Broadcom BCM2835 DSI support
- Allwinner sun5i and A80 conversion to new style clk bindings"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits)
clk: renesas: mstp: ensure register writes complete
clk: qcom: Do not drop device node twice
clk: mvebu: adjust clock handling for the CP110 system controller
clk: mvebu: Expand mv98dx3236-core-clock support
clk: zte: add i2s clocks for zx296718
clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
clk: tegra: Add BPMP clock driver
clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
clk: uniphier: add NAND clock for all UniPhier SoCs
ARM: dts: sun9i: Switch to new clock bindings
clk: sunxi-ng: Add A80 Display Engine CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
clk: qcom: SDHCI enablement on Nexus 5X / 6P
...
ARM64 DT updates are fairly small this time, only two new SoCs and a handful
of new machines get added, all of them similar to other hardware we already
support.
New SoC:
- HiSilicon Kirin960/Hi3660 and HiKey960 development board
- NXP LS1012a with three reference boards
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A
New development board:
- Banana Pi M64, based on Allwinner A64
http://www.banana-pi.org/m64.html
- SolidRun MACCHIATOBin based on Marvell Armada 8K
https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/
- Broadcom BCM958712DxXMC NorthStar2 reference board (another one)
A lot of platforms improve support for existing machines by adding
extra devices for which a binding and driver is availabe:
Allwinner: MMC, USB
ARM Juno: Coresight, STM
Broadcom: NS2 GICv2m irqchip and PCIe
Marvell: Armada 3700 SPI, I2C, ethernet switch
Mediatek: MT8173 thermal
NXP i.MX: LS1046A thermal
Qualcomm: coresight on MSM8916, HDMI, WCNSS, SCM
Renesas: r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd
Rockchip: thermal, eDP, pinctrl enhancements
Samsung: TM2 touchkey, Exynos5433 HDMI and power management improvements
UniPhier: SD reset, eMMC controller
ZTE: oppv2 cpufreq
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"ARM64 DT updates are fairly small this time, only two new SoCs and a
handful of new machines get added, all of them similar to other
hardware we already support.
New SoC:
- HiSilicon Kirin960/Hi3660 and HiKey960 development board
- NXP LS1012a with three reference boards:
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A
New development board:
- Banana Pi M64, based on Allwinner A64:
http://www.banana-pi.org/m64.html
- SolidRun MACCHIATOBin based on Marvell Armada 8K:
https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/
- Broadcom BCM958712DxXMC NorthStar2 reference board (another one)
A lot of platforms improve support for existing machines by adding
extra devices for which a binding and driver is availabe:
Allwinner:
- MMC, USB
ARM Juno:
- Coresight, STM
Broadcom:
- NS2 GICv2m irqchip and PCIe
Marvell:
- Armada 3700 SPI, I2C, ethernet switch
Mediatek:
- MT8173 thermal
NXP i.MX:
- LS1046A thermal
Qualcomm:
- coresight on MSM8916, HDMI, WCNSS, SCM
Renesas:
- r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd
Rockchip:
- thermal, eDP, pinctrl enhancements
Samsung:
- TM2 touchkey, Exynos5433 HDMI and power management improvements
UniPhier:
- SD reset, eMMC controller
ZTE:
- oppv2 cpufreq"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (110 commits)
arm64: dts: qcom: Add msm8916 CoreSight components
arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
arm64: allwinner: add BananaPi-M64 support
arm64: allwinner: a64: add UART1 pin nodes
arm64: allwinner: pine64: add MMC support
arm64: allwinner: a64: Increase the MMC max frequency
arm64: allwinner: a64: Add MMC pinctrl nodes
arm64: allwinner: a64: Add MMC nodes
dt-bindings: clockgen: Add compatible string for LS1012A
Documentation: DT: add LS1012A compatible for SCFG and DCFG
Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
arm64: tegra: Use symbolic reset identifiers
arm64: dts: r8a7796: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: tidyup audma definition order
arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
arm64: dts: r8a7796: Add R-Car Gen3 thermal support
arm64: dts: r8a7795: Add R-Car Gen3 thermal support
...
A total of 380 patches this time, mostly adding support for more hardware
in the device tree descriptions. There is not much exciting here for 4.11,
but I've tried my best to condense the information from the pull requests
I got into a readable summary.
Noteworthy changes to existing platforms include:
- The GIC memory map was a bit wrong almost everywhere and now
gets fixed up
- The Allwinner platforms convert to the generic pinmux properties
- The Marvell EBU platforms now use the new DSA binding
- Samsung Exynos4212 was unused and gets removed
- The Renesas power management got improved
New production machines:
- Lego Mindstorms EV3
https://www.lego.com/en-us/mindstorms/about-ev3
- Beelink X2 Android media box
http://linux-sunxi.org/Beelink_X2
- "Romulus" baseboard management controller for OpenPower
- Axentia TSE-850 Data Radio Channel (DARC) encoder
http://www.axentia.se/db/equipment.html
- Luxul XAP-1410 and XWR-1200 wireless access points
https://luxul.com/xap-1410
New SoCs:
- Allwinner H2+ and V3s, both minor variations of already
supported chips
http://www.allwinnertech.com/index.php?c=product&a=index&id=38
- Marvell Prestera DX packet processors based on Armada XP architecture
http://www.marvell.com/switching/prestera-dx/
- Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412
New developer and reference boards:
- Lichee Pi One, Lichee Pi Zero and Orange Pi Zero,
all based on Allwinner SoCs
http://linux-sunxi.org/LicheePi_Onehttp://www.orangepi.org/orangepizero/
- SAMA5d36ek Reference platform
http://www.atmel.com/tools/sama5d36-ek.aspx
- Beaglebone Green Wireless and Black Wireless
https://beagleboard.org/black-wirelesshttps://beagleboard.org/green-wireless
- phyCORE-AM335x System on Module
http://phytec.com/products/system-on-modules/phycore/am335x/
- New revision of "vf610-zii" Zodiac Inflight Innovations board
- Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core
http://www.opossom.com/english/index.htmlhttp://www.savageboard.org/http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ulhttp://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
- Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is
Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom,
rockchip, sti, stm32 and tegra
New device supports added to some boards and SoCs, briefly by platform:
- Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU
- Aspeed: network, ipmi bt, gpio, pinmux
- Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc
- TI DaVinci: gpio, lcdc, usb, video-in, uart
- TI Keystone 2: MSM RAM, power/reset, uart
- Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal
- Marvell EBU: ethernet switch on Turris Omnia
- NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic,
eeprom, mmc, nand
- TI OMAP:
- Qualcomm: coresight, gyro/accelerometer, hdmi
- Renesas: pmic, soc-id
- Rockchip: qos
- Samsung: audio on Odroid-X
- Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor
- STi: video in/out
- STM32: timer, pwm, i2c, rtc, add, i2s
- NVIDIA Tegra: tpm
- Uniphier: mmc/sd pinmux
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"A total of 380 patches this time, mostly adding support for more
hardware in the device tree descriptions. There is not much exciting
here for 4.11, but I've tried my best to condense the information from
the pull requests I got into a readable summary.
Noteworthy changes to existing platforms include:
- The GIC memory map was a bit wrong almost everywhere and now gets
fixed up
- The Allwinner platforms convert to the generic pinmux properties
- The Marvell EBU platforms now use the new DSA binding
- Samsung Exynos4212 was unused and gets removed
- The Renesas power management got improved
New production machines:
- Lego Mindstorms EV3:
https://www.lego.com/en-us/mindstorms/about-ev3
- Beelink X2 Android media box:
http://linux-sunxi.org/Beelink_X2
- "Romulus" baseboard management controller for OpenPower
- Axentia TSE-850 Data Radio Channel (DARC) encoder:
http://www.axentia.se/db/equipment.html
- Luxul XAP-1410 and XWR-1200 wireless access points:
https://luxul.com/xap-1410
New SoCs:
- Allwinner H2+ and V3s, both minor variations of already supported
chips:
http://www.allwinnertech.com/index.php?c=product&a=index&id=38
- Marvell Prestera DX packet processors based on Armada XP
architecture:
http://www.marvell.com/switching/prestera-dx/
- Samsung Exynos4412 Prime gets added, a minor variation of
Exynos4412
New developer and reference boards:
- Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on
Allwinner SoCs:
http://linux-sunxi.org/LicheePi_Onehttp://www.orangepi.org/orangepizero/
- SAMA5d36ek Reference platform:
http://www.atmel.com/tools/sama5d36-ek.aspx
- Beaglebone Green Wireless and Black Wireless:
https://beagleboard.org/black-wirelesshttps://beagleboard.org/green-wireless
- phyCORE-AM335x System on Module:
http://phytec.com/products/system-on-modules/phycore/am335x/
- New revision of "vf610-zii" Zodiac Inflight Innovations board
- Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam
i.Core:
http://www.opossom.com/english/index.htmlhttp://www.savageboard.org/http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ulhttp://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
- Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is
- Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas,
qcom, rockchip, sti, stm32 and tegra
New device supports added to some boards and SoCs, briefly by platform:
- Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU
- Aspeed: network, ipmi bt, gpio, pinmux
- Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc
- TI DaVinci: gpio, lcdc, usb, video-in, uart
- TI Keystone 2: MSM RAM, power/reset, uart
- Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal
- Marvell EBU: ethernet switch on Turris Omnia
- NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom,
mmc, nand
- TI OMAP:
- Qualcomm: coresight, gyro/accelerometer, hdmi
- Renesas: pmic, soc-id
- Rockchip: qos
- Samsung: audio on Odroid-X
- Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor
- STi: video in/out
- STM32: timer, pwm, i2c, rtc, add, i2s
- NVIDIA Tegra: tpm
- Uniphier: mmc/sd pinmux"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits)
ARM: dts: armada-385-linksys: fix DSA compatible property
ARM: dts: Fix typo in armada-xp-98dx4251
ARM: DTS: Fix register map for virt-capable GIC
dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
ARM: dts: sun8i: sinlinx: Enable audio nodes
ARM: dts: sun8i: parrot: Enable audio nodes
ARM: dts: sun8i: Add audio codec, dai and card for A33
ARM: dts: Add EMAC AXI settings for Arria10
ARM: dts: am335x-chiliboard: Support charger
ARM: dts: am335x-chiliboard: Support power button
ARM: sun8i: dt: Add mali node
dt-bindings: gpu: Add Mali Utgard bindings
ARM: dts: stm32: Add I2C1 support for STM32429 eval board
ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
ARM: dts: stm32: Use clock DT binding definition on stm32f429 family
dt-bindings: mfd: stm32f4: Add missing binding definition
dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
ARM: dts: stm32: add Timers driver for stm32f429 MCU
ARM: dts: add the AB8500 sysclk to the device trees
...
- Support for one new SoC, the V3s
- Convertion of two old SoCs to the new framework, the old sun5i family
and the A80
- A bunch of fixes
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Merge tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock updates from Maxime Ripard:
- Support for one new SoC, the V3s
- Conversion of two old SoCs to the new framework, the old sun5i family
and the A80
- A bunch of fixes
* tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
ARM: dts: sun9i: Switch to new clock bindings
clk: sunxi-ng: Add A80 Display Engine CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU
clk: sunxi-ng: Call divider_round_rate if we only have a single parent
ARM: gr8: Convert to CCU
ARM: sun5i: Convert to CCU
clk: sunxi-ng: Add sun5i CCU driver
clk: sunxi-ng: Implement global pre-divider
clk: sunxi-ng: Implement multiplier maximum
clk: sunxi-ng: mult: Fix minimum in round rate
clk: sunxi-ng: Implement factors offsets
clk: sunxi-ng: multiplier: Add fractional support
clk: sunxi-ng: add support for V3s CCU
dt-bindings: add device binding for the CCU of Allwinner V3s
...
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.
One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.
Add support for the display engine clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add support for the USB clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.
Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Use CLK_IS_CRITICAL to handle critical clocks,
- Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
- Add IIC-DVFS clocks for R-Car H3 and M3-W,
- Minor cleanups.
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Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Use CLK_IS_CRITICAL to handle critical clocks,
- Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
- Add IIC-DVFS clocks for R-Car H3 and M3-W,
- Minor cleanups.
* tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add IIC-DVFS clock
clk: renesas: r8a7795: Add IIC-DVFS clock
clk: renesas: cpg-mssr: Add support for reset control
clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
clk: renesas: cpg-mssr: Document suitability for RZ/G1
dt-bindings: clock: renesas: cpg-mssr: Document reset control support
clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
clk: renesas: mstp: Make INTC-SYS a critical clock
clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Document properties needed to use the Reset Control feature of the
Renesas Clock Pulse Generator / Module Standby and Software Reset
module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk-ux500:
clk: ux500: Convert ABx500 clocks to use OF probing
clk: ux500: Add device tree bindings for ABx500 clocks
clk: ux500: move AB8500 sysclk over to PRCMU clk driver
This adds device tree bindings for the ABx500 clocks on the
ST-Ericsson platforms.
Cc: devicetree@vger.kernel.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces the stm32f7 clock DT bindings.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver. In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
These are I2C clock generators with optional clock source from
either XTal or dedicated clock generator and, depending on the
model, two or more clock outputs.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: devicetree@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
controlled through the General Register Files, support for the rk3328
clock-controller (including a new pll-type) and the usual clock ids and
some fixes.
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Merge tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk updates from Heiko Stuebner:
A new clock-type for the 1-2 muxes per soc that are for whatever reason
controlled through the General Register Files, support for the rk3328
clock-controller (including a new pll-type) and the usual clock ids and
some fixes.
* tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: clk: add rockchip,grf property for RK3399
clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: use rk3288 isp_in clock ids
clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: add rk3288 isp_in clock ids
clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER
clk: rockchip: add clock controller for rk3328
dt-bindings: add bindings for rk3328 clock controller
clk: rockchip: add dt-binding header for rk3328
clk: rockchip: add new pll-type for rk3328
clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288
clk: rockchip: add a clock-type for muxes based in the grf
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
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Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk updates from Sylwester Nawrocki:
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
* tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)
clk: samsung: exynos-audss: Replace syscore PM with platform device PM
clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
Allwinner V3s is now driven by sunxi-ng CCU driver.
Add devicetree binding for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Support for Exynos4415 is going away because there are no internal nor
external users.
Since commit 46dcf0ff0d ("ARM: dts: exynos: Remove exynos4415.dtsi"),
the platform cannot be instantiated so remove also the drivers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add support for rockchip,grf property which is used for GRF muxes
on RK3399.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index 1 to use these clocks in DT.
e.g. <&rcc 1 CLK_LSI>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family. There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.
The clk-cdce925 driver supports only CDCE925 in the family. This adds
support for the CDCE913, CDCE937, CDCE949, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
It adds the compatible string for zx296718 audio clock controller.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
SATA Host 0 clock is (as correctly documented) id 15/sata0.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index 1 to use these clocks in DT.
e.g. <&rcc 1 CLK_LSI>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds all RPM based clocks for msm8974, except cxo and
gfx3d_clk_src.
Tested-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
A couple of interesting new SoC platforms are now supported, these are
the respective DTS sources:
- Samsung Exynos5433 mobile phone platform, including an (almost) fully
supported phone reference board.
- Hisilicon Hip07 server platform and D05 board, the latest iteration
of their product line, now with 64 Cortex-A72 cores across two
sockets.
- Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
line, used in Android tablets and ultra-cheap development boards
- NXP LS1046A Communication processor, improving on the earlier LS1043A
with faster CPU cores
- Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
mobile phone SoCs
- Early support for the Nvidia Tegra Tegra186 SoC
- Amlogic S905D is a minor variant of their existing Android consumer
product line
- Rockchip PX5 automotive platform, a close relative of their popular
rk3368 Android tablet chips
Aside from the respective evaluation platforms for the above
chips, there are only a few consumer devices and boards added
this time:
- Huawei Nexus 6P (Angler) mobile phone
- LG Nexus 5x (Bullhead) mobile phone
- Nexbox A1 and A95X Android TV boxes
- Pine64 development board based on Allwinner A64
- Globalscale Marvell ESPRESSOBin community board based on Armada 3700
- Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board
For the existing platforms, we get bug fixes and new peripheral support
for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin,
and ZTE.
Conflicts:
- Documentation/devicetree/bindings/arm/shmobile.txt: a
rename/add conflict, keep both modifications and maintain
alphabetical ordering.
- arch/arm64/boot/dts/*/*.dtsi: nodes were added in netdev,
mmc and clk, keep both sides in each case.
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"A couple of interesting new SoC platforms are now supported, these are
the respective DTS sources:
- Samsung Exynos5433 mobile phone platform, including an (almost)
fully supported phone reference board.
- Hisilicon Hip07 server platform and D05 board, the latest iteration
of their product line, now with 64 Cortex-A72 cores across two
sockets.
- Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
line, used in Android tablets and ultra-cheap development boards
- NXP LS1046A Communication processor, improving on the earlier
LS1043A with faster CPU cores
- Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
mobile phone SoCs
- Early support for the Nvidia Tegra Tegra186 SoC
- Amlogic S905D is a minor variant of their existing Android consumer
product line
- Rockchip PX5 automotive platform, a close relative of their popular
rk3368 Android tablet chips
Aside from the respective evaluation platforms for the above chips,
there are only a few consumer devices and boards added this time:
- Huawei Nexus 6P (Angler) mobile phone
- LG Nexus 5x (Bullhead) mobile phone
- Nexbox A1 and A95X Android TV boxes
- Pine64 development board based on Allwinner A64
- Globalscale Marvell ESPRESSOBin community board based on Armada 3700
- Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board
For the existing platforms, we get bug fixes and new peripheral
support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,
Rockchip, Berlin, and ZTE"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)
arm64: dts: fix build errors from missing dependencies
ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
ARM64: dts: meson-gxl: Add support for Nexbox A95X
ARM64: dts: meson-gxm: Add support for the Nexbox A1
ARM: dts: artpec: add pcie support
arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
arm64: dts: berlin4ct-stb: add missing unit name to /memory node
arm64: dts: berlin4ct: add missing unit name to /soc node
arm64: dts: qcom: msm8916: Add ddr support to sdhc1
arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM64: dts: Add support for Meson GXM
dt-bindings: add rockchip RK1108 Evaluation board
arm64: dts: NS2: Add PCI PHYs
arm64: dts: NS2: enable sdio1
arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
arm64: tegra: Add NVIDIA P2771 board support
arm64: tegra: Enable PSCI on P3310
arm64: tegra: Add NVIDIA P3310 processor module support
arm64: tegra: Add GPIO controllers on Tegra186
...
As usual, we queue up a few fixes that don't seem urgent enough to go in
through -rc, or that just came a little too late given their size.
The zx fixes make the platform finally boot on real hardware, the
davinci and imx31 get the DT support working better for some of
the machines that are still normally used with classic board files.
One tegra fix is important for new bootloader versions, but the
bug has been around for a while without anyone noticing.
The other changes are mostly cosmetic.
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Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-urgent fixes from Arnd Bergmann:
"As usual, we queue up a few fixes that don't seem urgent enough to go
in through -rc, or that just came a little too late given their size.
The zx fixes make the platform finally boot on real hardware, the
davinci and imx31 get the DT support working better for some of the
machines that are still normally used with classic board files. One
tegra fix is important for new bootloader versions, but the bug has
been around for a while without anyone noticing.
The other changes are mostly cosmetic"
* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
arm64: tegra: Add missing Smaug revision
arm64: tegra: Add VDD_GPU regulator to Jetson TX1
arm64: dts: zte: clean up gic-v3 redistributor properties
arm64: dts: zx: Fix gic GICR property
bus: vexpress-config: fix device reference leak
soc: ti: qmss: fix the case when !SMP
ARM: lpc32xx: drop duplicate header device.h
ARM: ixp4xx: drop duplicate header gpio.h
ARM: socfpga: fix spelling mistake in error message
ARM: dts: imx6q-cm-fx6: fix fec pinctrl
ARM: dts: imx7d-pinfunc: fix UART pinmux defines
ARM: dts: imx6qp: correct LDB clock inputs
ARM: OMAP2+: pm-debug: Use seq_putc() in two functions
ARM: OMAP2+: Remove the omapdss_early_init_of() function
mfd: tps65217: Fix mismatched interrupt number
ARM: zx: Fix error handling
ARM: spear: Fix error handling
ARM: davinci: da850: Fix pwm name matching
ARM: clk: imx31: properly init clocks for machines with DT
clk: imx31: fix rewritten input argument of mx31_clocks_init()
...
Pull rockchip clk driver updates from Heiko Stuebner:
A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.
* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for rk1108
dt-bindings: add documentation for rk1108 cru
clk: rockchip: add dt-binding header for rk1108
clk: rockchip: fix copy-paste error in rk3399 testclk
clk: rockchip: validity should be checked prior to cpu clock rate change
- addition of missing documentation and DT properties for the CMU_AUD
block source clocks,
- correction of CMU_FSYS parent clock definition,
- marking as critical clocks which have to be enabled in order
to access control registers of child CMUs.
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Merge tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Exynos5433 SoC updates from Sylwester Nawrocki:
- addition of missing documentation and DT properties for the CMU_AUD
block source clocks,
- correction of CMU_FSYS parent clock definition,
- marking as critical clocks which have to be enabled in order
to access control registers of child CMUs.
* tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung:
clk: exynos5433: Mark some clocks as critical
clk: exynos5433: Add documentation for the audio block parent clocks
clk: exynos5433: Fix parent clocks for FSYS block
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
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Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add TMU device tree support for LS2080A
arm64: dts: ls1043a: Add TMU device tree support for LS1043A
arm64: dts: add LS1046A-QDS board support
Documentation: DT: Add entry for QorIQ LS1046A-QDS board
arm64: dts: add LS1046A-RDB board support
Documentation: DT: Add entry for QorIQ LS1046A-RDB board
arm64: dts: add QorIQ LS1046A SoC support
dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
dt-bindings: i2c: adds two more nxp devices
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings
Signed-off-by: Olof Johansson <olof@lixom.net>
- A series from Vladimir to fix broken i.MX31 DT clock initialization.
As i.MX31 DT support is still not quite complete, the changes are
tested on qemu kzm target and mx31lite board with simple written DTS
files.
- A fix for CompuLab's sbc-fx6 baseboard to remove wrong fec pinctrl
setting.
- A DTS correction for i.MX6QP to reflect the change that the gate of
LDB clock has been moved before the divider.
- An imx7d-pinfunc fix for UART pinmux defines
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Merge tag 'imx-fix-nc-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/fixes-non-critical
i.MX non-critical fixes for 4.10:
- A series from Vladimir to fix broken i.MX31 DT clock initialization.
As i.MX31 DT support is still not quite complete, the changes are
tested on qemu kzm target and mx31lite board with simple written DTS
files.
- A fix for CompuLab's sbc-fx6 baseboard to remove wrong fec pinctrl
setting.
- A DTS correction for i.MX6QP to reflect the change that the gate of
LDB clock has been moved before the divider.
- An imx7d-pinfunc fix for UART pinmux defines
* tag 'imx-fix-nc-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6q-cm-fx6: fix fec pinctrl
ARM: dts: imx7d-pinfunc: fix UART pinmux defines
ARM: dts: imx6qp: correct LDB clock inputs
ARM: clk: imx31: properly init clocks for machines with DT
clk: imx31: fix rewritten input argument of mx31_clocks_init()
ARM: dts: imx31: move CCM device node to AIPS2 bus devices
ARM: dts: imx31: fix clock control module interrupts description
Signed-off-by: Olof Johansson <olof@lixom.net>
* 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: Add support for msm8994 global clock controller
dt-bindings: qcom: clocks: Add msm8994 clock bindings
Audio block requires access to two parent clocks: audio PLL and oscillator,
so add this information to device tree bindings documentation.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The proper parent clock for FSYS block is "aclk_fsys_200"
according to the Exynos5433 reference manual.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The usual patches from us, but most notably the introduction of the A64
clocks unit.
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Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock changes from Maxime Ripard:
The usual patches from us, but most notably the introduction of the A64
clocks unit.
* tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks
clk: sunxi-ng: Add A64 clocks
clk: sunxi-ng: Implement minimum for multipliers
clk: sunxi-ng: Add minimums for all the relevant structures and clocks
clk: sunxi-ng: Finish to convert to structures for arguments
clk: sunxi-ng: Remove the use of rational computations
clk: sunxi-ng: Rename the internal structures
clk: sunxi: mod0: improve function-level documentation
This adds the dt-binding documentation for the clock and reset unit
found on Rockchip rk1108 SoCs.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.
This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove useless braces for single line if]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
[sboyd@codeaurora.org: Dropped unused and incorrect GDSC defines]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the A64 CCU clocks set.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The type of AVIC interrupt controller found on i.MX31 is one-cell,
namely 31 for CCM DVFS and 53 for CCM, however for clock control
module its interrupts are specified as 3-cells, fix it.
Fixes: ef0e4a606f ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds the QSPI clock for stm32f469 discovery board.
The gate mapping is a little bit different from stm32f429 soc.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add OX820 bindings and remove clock indices from bindings since they are present
in the dt-bindings headers files.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20161005150752.22618-7-narmstrong@baylibre.com
Adds compatible for SoCs which use clockgen, the SoCs are LS1043A,
LS1046A, LS2080A.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
I made a mistake as for naming for this block. The MIO block is not
implemented for these 3 SoCs in the first place. The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.
This driver has just been merged in the previous merge window.
Rename it before the release.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These are as usual a very large number of mostly boring updates to
enable devices in existing machines, or to fix minor bugs. Notably,
an ongoing treewide effort to fix warnings caused by an update to the
device tree compiler. These are enabled with "make W=1" at the moment
but can hopefully become the default once all issues have been addressed.
No new SoC platform is added this time around (Armada 395 and Orion
mv88f5181 are slight variations of existing ones), but a significant
number of new dts files are added, which I list by platform:
- Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets;
Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E,
Orange Pi Lite, Olimex A33-Olinuxino, and Nano Pi Neo
single-board computers
- ARM Realview: all supported machines (ported from board files)
- Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and
BCM958622hr reference boards for Northstar platform;
Raspberry Pi Zero single-board computer
- Marvell EBU: Netgear WNR854T router (ported from board file);
Armada 395 SoC platform and GP board
Armada 390 DB development board
- NXP i.MX: imx7s Warp7 reference board;
Gateworks Ventana GW553x single-board computer,
Technologic Systems TS-4900 and
Engicam IMX6UL GEA M6UL computer-on-module,
Inverse Path USB armory board
- Qualcomm: LG Nexus 5 Phone
- Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards
- Rockchip: Rockchip RK3288 Fennec reference board;
Firefly RK3288 Reload platform
- ST Microelectronics STi: B2260 (96boards) single-board computer
- TI Davinci: OMAP-L138 LCDK Development kit
- TI OMAP: beagleboard-x15 rev B1 single-board computer
Conflicts: vendor-prefixes.txt has conflicting additions, keep all of
them in alphabetical order.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are as usual a very large number of mostly boring updates to
enable devices in existing machines, or to fix minor bugs. Notably, an
ongoing treewide effort to fix warnings caused by an update to the
device tree compiler. These are enabled with "make W=1" at the moment
but can hopefully become the default once all issues have been
addressed.
No new SoC platform is added this time around (Armada 395 and Orion
mv88f5181 are slight variations of existing ones), but a significant
number of new dts files are added, which I list by platform:
- Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets,
Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E, Orange Pi Lite,
Olimex A33-Olinuxino, and Nano Pi Neo single-board computers
- ARM Realview: all supported machines (ported from board files)
- Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and
BCM958622hr reference boards for Northstar platform, Raspberry Pi
Zero single-board computer
- Marvell EBU: Netgear WNR854T router (ported from board file),
Armada 395 SoC platform and GP board Armada 390 DB development
board
- NXP i.MX: imx7s Warp7 reference board, Gateworks Ventana GW553x
single-board computer, Technologic Systems TS-4900 and Engicam
IMX6UL GEA M6UL computer-on-module, Inverse Path USB armory board
- Qualcomm: LG Nexus 5 Phone
- Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards
- Rockchip: Rockchip RK3288 Fennec reference board, Firefly RK3288
Reload platform
- ST Microelectronics STi: B2260 (96boards) single-board computer
- TI Davinci: OMAP-L138 LCDK Development kit
- TI OMAP: beagleboard-x15 rev B1 single-board computer"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (390 commits)
ARM: dts: sony-nsz-gs7: add missing unit name to /memory node
ARM: dts: chromecast: add missing unit name to /memory node
ARM: dts: berlin2q-marvell-dmp: add missing unit name to /memory node
ARM: dts: berlin2: Add missing unit name to /soc node
ARM: dts: berlin2cd: Add missing unit name to /soc node
ARM: dts: berlin2q: Add missing unit name to /soc node
ARM: dts: berlin2: Remove skeleton.dtsi inclusion
ARM: dts: berlin2cd: Remove skeleton.dtsi inclusion
ARM: dts: berlin2q: Remove skeleton.dtsi inclusion
arm: dts: berlin2q: enable all wdt nodes unconditionally
arm: dts: berlin2: enable all wdt nodes unconditionally
ARM: dts: omap5-igep0050.dts: Use tabs for indentation
ARM: dts: Fix igepv5 power button GPIO direction
ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node
ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
ARM: dts: s3c64xx: Use macros for pinctrl configuration
ARM: dts: s3c2416: Use macros for pinctrl configuration
ARM: dts: s5pv210: Use macros for pinctrl configuration
ARM: dts: s3c64xx: Use common macros for pinctrl configuration
...
Driver updates for ARM SoCs, including a couple of newly added drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the
EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant
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Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into next/drivers
Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT:
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant
* tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu:
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.
[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Starting with sama5d4, the crystal oscillator is always enabled at startup
and the SCKC doesn't have an OSC32EN bit anymore.
Add support for that new controller.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add clock data arrays for all UniPhier SoCs with a binding document.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This clock is present on BCM53573 devices (including BCM47189) that use
Cortex-A7. ILP is a part of PMU (Power Management Unit) multi-function
device so we use syscon (and regmap) for it.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove 0 from clk_init_data to silence sparse]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch configures the semi-synchronous mode of the video clocks
of clkgenD2.
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch allows fine tuning of the quads FS for audio clocks
accuracy.
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
STiH415 and STiH416 platforms are no longer used.
these platforms will be deprecated for the next kernel.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ZX296718 clocks are statically listed and registered. More
clock will be added later.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).
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Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock driver changes from Maxime Ripard:
Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).
* tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi-ng: Add hardware dependency
clk: sunxi-ng: Add A23 CCU
clk: sunxi-ng: Add A33 CCU support
clk: sunxi-ng: Add N-class clocks support
clk: sunxi-ng: mux: Add mux table macro
clk: sunxi-ng: div: Allow to set a maximum
clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
clk: sunxi-ng: div: Add mux table macros
clk: sunxi-ng: Add A31/A31s clocks
clk: sunxi-ng: mux: Add clk notifier functions
clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
clk: sunxi-ng: mux: Add support for mux tables
clk: sunxi-ng: mux: Rename mux macro to be consistent
clk: sunxi-ng: nkm: Add mux to support multiple parents
clk: sunxi-ng: mux: Increase fixed pre-divider div size
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
(EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
clock drivers co-maintainer.
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Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki:
In addition to a few clean up and code consolidation patches this
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
(EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
clock drivers co-maintainer.
* tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Add support for EPLL on exynos5410
clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
clk: samsung: clk-exynos-audss: Add exynos5410 compatible
clk: samsung: clk-exynos-audss: controller variant handling rework
clk: samsung: Use common registration function for pll2550x
clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
Add support for the clock unit found in the A23. Due to the similarities
with the A33, it also shares its clock IDs to allow sharing the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This commit introduces the clocks found in the Allwinner A33 CCU.
Since this SoC is very similar to the A23, and we share a significant share
of the DTSI, the clock IDs that are going to be used will also be shared
with the A23, hence the name of the various header files.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This patch adds code instantiating the EPLL, which is used as the
audio subsystem's root clock.
The requirement to specify the external root clock in clocks property
is documented. Having the consumer 'clocks' property ensures proper
initialization order by explicitly specifying dependencies in DT.
It prevents situations when the SoC's clock controller driver has
initialized, the external oscillator clock is not yet registered
and setting clock frequencies through assigned-clock-rates property
doesn't work properly due to unknown external oscillator frequency.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Exynos5410 Audio Subsystem Clock Controller, comparing to the already
supported IP block revisions, has additionally an I2S_MST divider
so a new compatible string is added.
It is not clear from the Exynos5410 User's Manual released on 2012.03.09
where in the clock tree the I2S_MST clock divider can be found exactly
so this clock is left unimplemented for now.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
TSENS is part of GCC, hence add TSENS properties as part of GCC node.
Also add thermal zones and qfprom nodes.
Update GCC bindings doc to mention the possibility of optional TSENS
properties that can be part of GCC node.
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a new style driver for the clock control unit in Allwinner A31/A31s.
A few clocks are still missing:
- MIPI PLL's HDMI mode support
- EMAC clock
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Integrator/AP and Integrator/CP core modules have special
versions of the ICST525 interface hardcoding some bits. Create
special compatible strings to identify these variants, also
explain a bit what is going on.
Cc: devicetree@vger.kernel.org
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds documentation of device tree bindings for the
STM32 reset controller.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add documentations and dt-bindings headers for the AO clock and reset
controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-qcom-9615:
dt-bindings: clock: Update bindings for MDM9615 GCC and LCC
clk: mdm9615: Add support for MDM9615 Clock Controllers
dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC
Maxim has used the same clock IP on multiple PMICs like MAX77686,
MAX77802, MAX77620. Only differences are the number of clocks
from these PMICs like MAX77686 has 3 clocks output, MAX776802 have
two clock output and MAX77620 has one clock output.
Add clock binding details and DT example for the MAX77620.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.
Define the common DT binding file for the clocks of Maxim PMICs
MAX77686 and MAX77802. For this, remove the separate DT binding
document file for maxim,max77802 and move all information to
maxim,max77686 DT binding document.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit adds the DT binding documentation for the peripheral clocks
used in the Marvell Armada 3700 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit adds the DT binding documentation for the Time Base Generator
clock used in the Marvell Armada 3700 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit adds the DT binding documentation for the the Xtal clock on
Armada 3700 used in the Marvell Armada 3700 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Both SATA and second USB3.0 interface are supported in Armada-39x SoC
family. Add necessary clk description, so both xhci and sata drivers
can be correctly initialized.
The binding documentation has also been updated accordingly.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Driver updates for ARM SoCs.
A slew of changes this release cycle. The reset driver tree, that we merge
through arm-soc for historical reasons, is also sizable this time around.
Among the changes:
- clps711x: Treewide changes to compatible strings, merged here for simplicity.
- Qualcomm: SCM firmware driver cleanups, move to platform driver
- ux500: Major cleanups, removal of old mach-specific infrastructure.
- Atmel external bus memory driver
- Move of brcmstb platform to the rest of bcm
- PMC driver updates for tegra, various fixes and improvements
- Samsung platform driver updates to support 64-bit Exynos platforms
- Reset controller cleanups moving to devm_reset_controller_register() APIs
- Reset controller driver for Amlogic Meson
- Reset controller driver for Hisilicon hi6220
- ARM SCPI power domain support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs.
A slew of changes this release cycle. The reset driver tree, that we
merge through arm-soc for historical reasons, is also sizable this
time around.
Among the changes:
- clps711x: Treewide changes to compatible strings, merged here for simplicity.
- Qualcomm: SCM firmware driver cleanups, move to platform driver
- ux500: Major cleanups, removal of old mach-specific infrastructure.
- Atmel external bus memory driver
- Move of brcmstb platform to the rest of bcm
- PMC driver updates for tegra, various fixes and improvements
- Samsung platform driver updates to support 64-bit Exynos platforms
- Reset controller cleanups moving to devm_reset_controller_register() APIs
- Reset controller driver for Amlogic Meson
- Reset controller driver for Hisilicon hi6220
- ARM SCPI power domain support"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits)
ARM: ux500: consolidate base platform files
ARM: ux500: move soc_id driver to drivers/soc
ARM: ux500: call ux500_setup_id later
ARM: ux500: consolidate soc_device code in id.c
ARM: ux500: remove cpu_is_u* helpers
ARM: ux500: use CLK_OF_DECLARE()
ARM: ux500: move l2x0 init to .init_irq
mfd: db8500 stop passing around platform data
ASoC: ab8500-codec: remove platform data based probe
ARM: ux500: move ab8500_regulator_plat_data into driver
ARM: ux500: remove unused regulator data
soc: raspberrypi-power: add CONFIG_OF dependency
firmware: scpi: add CONFIG_OF dependency
video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip
input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip
pwm: clps711x: Changing the compatibility string to match with the smallest supported chip
serial: clps711x: Changing the compatibility string to match with the smallest supported chip
irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip
clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip
clk: clps711x: Changing the compatibility string to match with the smallest supported chip
...
Introduce a new binding with its documentation for the brand new clock
sub-framework.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-2-maxime.ripard@free-electrons.com
This patch changes the compatibility string to match with the smallest
supported chip (EP7209). Since the DT-support for this CPU is not yet
announced, this change is safe.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The only way for a fixed factor clock to change its rate would be to change
its parent rate.
Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms
that were relying on the fact that the parent rate wouldn't change,
introduce a compatible-based whitelist that will allow clocks to opt-in
that flag.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Renesas R8A7792 SoC also has the CPG MSTP clocks...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
do have a couple core changes in here as well.
Core:
- CLK_IS_CRITICAL support has been added. This should allow drivers
to properly express that a certain clk should stay on even if
their prepare/enable count drops to 0 (and in turn the parents of
these clks should stay enabled).
- A clk registration API has been added, clk_hw_register(), and
an OF clk provider API has been added, of_clk_add_hw_provider().
These APIs have been put in place to further split clk providers
from clk consumers, with the goal being to have clk providers
never deal with struct clk pointers at all. Conversion of provider
drivers is on going. clkdev has also gained support for registering
clk_hw pointers directly so we can convert drivers that don't use
devicetree.
New Drivers:
- Marvell ap806 and cp110 system controllers (with clks inside!)
- Hisilicon Hi3519 clock and reset controller
- Axis ARTPEC-6 clock controllers
- Oxford Semiconductor OXNAS clock controllers
- AXS10X I2S PLL
- Rockchip RK3399 clock and reset controller
Updates:
- MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x
SoCs, and some more clk ID exporting for bus frequency scaling
- Proper BCM2835 PCM clk support and various other clks
- i.MX clk updates for i.MX6SX, i.MX7, and VF610
- Renesas updates for R-Car H3
- Tegra210 got updates for DisplayPort and HDMI 2.0
- Rockchip driver refactorings and fixes due to adding RK3399 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"It's the usual big pile of driver updates and additions, but we do
have a couple core changes in here as well.
Core:
- CLK_IS_CRITICAL support has been added. This should allow drivers
to properly express that a certain clk should stay on even if their
prepare/enable count drops to 0 (and in turn the parents of these
clks should stay enabled).
- A clk registration API has been added, clk_hw_register(), and an OF
clk provider API has been added, of_clk_add_hw_provider(). These
APIs have been put in place to further split clk providers from clk
consumers, with the goal being to have clk providers never deal
with struct clk pointers at all. Conversion of provider drivers is
on going. clkdev has also gained support for registering clk_hw
pointers directly so we can convert drivers that don't use
devicetree.
New Drivers:
- Marvell ap806 and cp110 system controllers (with clks inside!)
- Hisilicon Hi3519 clock and reset controller
- Axis ARTPEC-6 clock controllers
- Oxford Semiconductor OXNAS clock controllers
- AXS10X I2S PLL
- Rockchip RK3399 clock and reset controller
Updates:
- MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
542x SoCs, and some more clk ID exporting for bus frequency scaling
- Proper BCM2835 PCM clk support and various other clks
- i.MX clk updates for i.MX6SX, i.MX7, and VF610
- Renesas updates for R-Car H3
- Tegra210 got updates for DisplayPort and HDMI 2.0
- Rockchip driver refactorings and fixes due to adding RK3399 support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
clk: fix critical clock locking
clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
clk: ingenic: Allow divider value to be divided
clk: sunxi: Add display and TCON0 clocks driver
clk: rockchip: drop old_rate calculation on pll rate changes
clk: rockchip: simplify GRF handling in pll clocks
clk: rockchip: lookup General Register Files in rockchip_clk_init
clk: rockchip: fix the rk3399 sdmmc sample / drv name
clk: mvebu: new driver for Armada CP110 system controller
dt-bindings: arm: add DT binding for Marvell CP110 system controller
clk: mvebu: new driver for Armada AP806 system controller
clk: hisilicon: add CRG driver for hi3519 soc
clk: hisilicon: export some hisilicon APIs to modules
reset: hisilicon: add reset controller driver for hisilicon SOCs
clk: bcm/kona: Do not use sizeof on pointer type
clk: qcom: msm8916: Fix crypto clock flags
clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
clk/axs10x: Add I2S PLL clock driver
clk: imx7d: fix ahb clock mux 1
clk: fix comment of devm_clk_hw_register()
...
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These warnings
are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
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Merge tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.
- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.
- Sync to latest dtc which adds more dts style checking. These
warnings are enabled with "W=1" compiles.
- Tegra documentation updates related to the above warnings.
- A bunch of spelling and other doc fixes.
- Various vendor prefix additions.
* tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (52 commits)
devicetree: Add Creative Technology vendor id
gpio: dt-bindings: add ibm,ppc4xx-gpio binding
of/unittest: Remove unnecessary module.h header inclusion
drivers/of: Fix build warning in populate_node()
drivers/of: Fix depth when unflattening devicetree
of: dynamic: changeset prop-update revert fix
drivers/of: Export of_detach_node()
drivers/of: Return allocated memory from of_fdt_unflatten_tree()
drivers/of: Specify parent node in of_fdt_unflatten_tree()
drivers/of: Rename unflatten_dt_node()
drivers/of: Avoid recursively calling unflatten_dt_node()
drivers/of: Split unflatten_dt_node()
of: include errno.h in of_graph.h
of: document refcount incrementation of of_get_cpu_node()
Documentation: dt: soc: fix spelling mistakes
Documentation: dt: power: fix spelling mistake
Documentation: dt: pinctrl: fix spelling mistake
Documentation: dt: opp: fix spelling mistake
Documentation: dt: net: fix spelling mistakes
Documentation: dt: mtd: fix spelling mistake
...
Pull some non-critical i.MX clk fixes from Shawn Guo:
* Fix the commit 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
which messed up the clock enumeration when adding new clock.
* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx35: restore existing used clock enumeration
clk: imx6q: fix typo in CAN clock definition
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.
Add a driver to support both.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Silence variable sized array warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and
display-related clocks.
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Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock driver updates from Maxime Ripard:
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and
display-related clocks.
* tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi: Let divs clocks read the base factor clock name from devicetree
clk: sunxi: Add TCON channel1 clock
clk: sunxi: Add PLL3 clock
dt-bindings: clk: sun5i: add DRAM gates compatible
clk: sunxi: Use resource_size
clk: sunxi: Add sun6i/8i display support
clk: sunxi: mod1 clock should modify it's parent
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.
It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).
Add a driver for the channel 1 clock.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the clock type which is used by the sun6i/8i families for video display.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
A new element got inserted into enum mx35_clks with commit 3713e3f5e9
("clk: imx35: define two clocks for rtc"). This insertion shifted most
nummerical clock assignments to a new nummerical value which in turn
rendered most hardcoded nummeric values in imx35.dtsi incorrect.
Restore the existing order by moving the newly introduced clock to the
end of the enum. Update the dts documentation accordingly.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Fixes: 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Added unit address to binding example]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add DT binding documentation for lpc1850-creg-clk driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull Allwinner clk updates from Maxime Ripard:
Allwinner clocks additions for 4.6
A bunch of things, mostly:
- Finally switched everything over to OF_CLK_DECLARE, which should remove
orphans clocks entirely
- Reworked the clk-factors to be able to add new parameters
- Improved the error reporting
- A bunch of new clocks for new SoCs.
* tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
clk: sunxi: Add apb0 gates for H3
clk: sunxi: Improve divs_clk error handling and reporting
clk: sunxi: improve divider_clk error handling and reporting
clk: sunxi: improve mux_clk error handling and reporting
clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
clk: sunxi: Remove clk_register_clkdev calls
clk: sunxi: Remove old probe and protection code
clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
clk: sunxi: Make clocks setup functions take const pointer
clk: sunxi: Make clocks setup functions return their clock
clk: sunxi: improve error reporting for the mux clock
clk: sunxi: don't mark sun6i_ar100_data __initconst
clk: sunxi: add bus gates for A83T
clk: sunxi: Add apb0 gates for A83T
clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
clk: sunxi: rewrite sun6i-ar100 using factors clk
clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
clk: sunxi: factors: Drop round_rate from clk ops
clk: sunxi: factors: Support custom formulas
clk: sunxi: factors: Consolidate get_factors parameters into a struct
...
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.
Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.
Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A83T has similar bus gates that of H3, including single gating register has
different clock parent.
As per H3 and A83T datasheet, usbhost is under AHB2.
However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits 29, 30, 31(ohci0,1,2) => AHB2 for H3.
until, this confusion is cleared keep it H3 way.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.
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Merge tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
Pull rockchip fixes from Heiko Stuebner:
Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.
* tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3368: fix some clock gates
clk: rockchip: rk3036: rename emac ext source clock
clk: rockchip: rk3036: fix the div offset for emac clock
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: fix the FLAGs for clock mux
The clock generator has two clock inputs that can be used as the reference
clock. Add support for switching between them at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds audio clock device tree binding documentation to an
existing Cygnus clock DT bindings document.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Lori Hikichi <lhikichi@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Update APM X-Gene clock binding documentation for SoC and
PCP PLL for v2 hardware.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As usual, the bulk of this release is again DT file contents.
There's a huge number of changes here, and it's challenging to give a crisp
overview of just what is in here. To start with:
New boards:
- TI-based DM3730 from LogicPD (Torpedo)
- Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
- Raspberry Pi 2 DT files
- Watchdog on Meson8b
- Veyron-mickey (ASUS Chromebit) DTS
- Rockchip rk3228 SoC and eval board
- Sigma Designs Tango4
Improvements:
- Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
- Misc new devices for Rockchip rk3036 and rk3288
- Allwinner updates for misc SoCs and systems
... and a _large_ number of other changes across the field. Devices
added to SoC DTSI and board DTS files for a number of SoC vendors, new
product boards on already-supported SoCs, cleanups and refactorings of
existing DTS/DTSI files and a bunch of other changes.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As usual, the bulk of this release is again DT file contents.
There's a huge number of changes here, and it's challenging to give a
crisp overview of just what is in here. To start with:
New boards:
- TI-based DM3730 from LogicPD (Torpedo)
- Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
- Raspberry Pi 2 DT files
- Watchdog on Meson8b
- Veyron-mickey (ASUS Chromebit) DTS
- Rockchip rk3228 SoC and eval board
- Sigma Designs Tango4
Improvements:
- Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
- Misc new devices for Rockchip rk3036 and rk3288
- Allwinner updates for misc SoCs and systems
... and a _large_ number of other changes across the field. Devices
added to SoC DTSI and board DTS files for a number of SoC vendors, new
product boards on already-supported SoCs, cleanups and refactorings of
existing DTS/DTSI files and a bunch of other changes"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits)
ARM: dts: compulab: add new board description
ARM: versatile: add the syscon LEDs to the DT
dts: vt8500: Fix errors in SDHC node for WM8505
ARM: dts: imx6q: clean up unused ipu2grp
ARM: dts: silk: Add compatible property to "partitions" node
ARM: dts: gose: Add compatible property to "partitions" node
ARM: dts: porter: Add compatible property to "partitions" node
ARM: dts: koelsch: Add compatible property to "partitions" node
ARM: dts: lager: Add compatible property to "partitions" node
ARM: dts: bockw: Add compatible property to "partitions" node
ARM: dts: meson8b: Add watchdog node
Documentation: watchdog: Add new bindings for meson8b
ARM: meson: Add status LED for Odroid-C1
ARM: dts: uniphier: fix a typo in comment block
ARM: bcm2835: Add the auxiliary clocks to the device tree.
ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B
ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT.
ARM: bcm2835: Split the DT for peripherals from the DT for the CPU
ARM: realview: set up cache correctly on the PB11MPCore
ARM: dts: Unify G2D device node with other devices on exynos4
...
Drop the bogus "sh73a0-" part (accidentally copied from shmobile?) from
the compatible value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There is only support rmii in the RK3036, so we should use the correct
ext clock name as described in the TRM.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[update dt-binding document as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
bulk of the changes are to clk controller drivers, though some
improvements to the core and some re-usable blocks/templates also
received some love. In this past cycle the clk maintainers developed a
good workflow for handling the common case of patch submissions
containing a new drivers, new shared Device Tree header and a new Device
Tree binding description. This requires coordination with the Device
Tree maintainers and with the architecture maintainers (typically the
arm-soc tree in our case). This explains the increase in changes to
include/dt-bindings/... and to
Documentation/devicetree/bindings/clock/... coming from the clk tree.
The same commits can be expected to come through those trees on
occasion, through the use of shared, immutable branches.
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Merge tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk framework updates from Michael Turquette:
"The clk framework and driver changes for 4.5 look pretty typical. The
bulk of the changes are to clk controller drivers, though some
improvements to the core and some re-usable blocks/templates also
received some love.
In this past cycle the clk maintainers developed a good workflow for
handling the common case of patch submissions containing a new
drivers, new shared Device Tree header and a new Device Tree binding
description. This requires coordination with the Device Tree
maintainers and with the architecture maintainers (typically the
arm-soc tree in our case).
This explains the increase in changes to include/dt-bindings/... and
to Documentation/devicetree/bindings/clock/... coming from the clk
tree. The same commits can be expected to come through those trees on
occasion, through the use of shared, immutable branches"
* tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: remove duplicated COMMON_CLK_NXP record from clk/Kconfig
clk: fix clk-gpio.c with optional clock= DT property
clk: rockchip: fix section mismatches with new child-clocks
clk: gpio: handle error codes for of_clk_get_parent_count()
clk: gpio: fix memory leak
clk: shmobile: r8a7795: Add SATA0 clock
clk: bcm2835: Add PWM clock support
clk: bcm2835: Support for clock parent selection
clk: bcm2835: add a round up ability to the clock divisor
clk: lpc32xx: add common clock framework driver
clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol
dt-bindings: clock: add NXP LPC32xx clock list for consumers
dt-bindings: clock: add description of LPC32xx USB clock controller
dt-bindings: clock: add description of LPC32xx clock controller
clk: rockchip: rk3036: include downstream muxes into fractional dividers
clk: add flag for clocks that need to be enabled on rate changes
clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
clk: rockchip: include downstream muxes into fractional dividers
clk: rockchip: handle mux dependency of fractional dividers
clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
...
Bindings for Samsung S2M and S5M family PMICs are in mess. They are
spread over different files and subdirectories in a non-consistent way.
The devices and respective drivers for them share a lot in common so
everything could be organized in a more readable way.
Reorganize the S2MPS11/13/14/15 Device Tree bindings to match the
drivers for this family of devices:
- move mfd/s2mps11.txt to mfd/samsung,sec-core.txt for the main MFD
driver (common for entire family),
- split clock block to clock/samsung,s2mps11.txt,
- split regulator block to regulator/samsung,s2mps11.txt.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
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Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.5-rc1
This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
NXP LPC32xx USB controller has a subdevice, which controls USB AHB
slave, USB OTG, USB OHCI, USB device and I2C controller to USB phy
clocks, this change adds description of the clock controller, for more
details reference LPC32xx User's Manual, namely USB control, OTG clock
control and OTG clock status registers.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
of system control block (SCB). CPC is supplied by two external
oscillators and it manages core and most of peripheral
clocks, the change adds description of DT bindings for clock
controller found on LPC32xx SoC series.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Clock patches for the Allwinner SoCs:
- H3 clocks
- A10/A20 Video Engine clocks
- DRAM gates
- A80 special CPU clock
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Merge tag 'sunxi-clocks-for-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clocks changes for 4.5
Clock patches for the Allwinner SoCs:
- H3 clocks
- A10/A20 Video Engine clocks
- DRAM gates
- A80 special CPU clock
These will be used for enabling UART1, SPI1, and SPI2.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
support.
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Merge tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Merge "Realview DT files" from Linus Walleij:
The device tree changes for the continued RealView DT
support.
* tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: realview: add device tree for PB11MPCore
clk: add ARM syscon ICST device tree bindings
ARM: add DT bindings for the ARM11MPCore CPU cluster
Pull "Broadcom devicetree changes for v4.5¨ from Florian Fainelli:
This pull request contains the Broadcom ARM-based Device Tree changes for 4.5:
- Jon Mason enables the following for Broadcom Northstar Plus SoCs: PCI (using
iProc PCI), NAND flash controller (BRCMNAND), TWD Timer and Watchdog
(Cortex-A9), I2C (iProc), clock providers, does some Device Tree cleanups
(re-parenting, fixing register sizes and hierarchy)
- Jon Mason also adds support for some reference Broadcom Northstar reference
designs like the BCM5301X SVK reference boards, updates the existing binding
documentation to cover the Northstar chips: 4708, 4709 and 53012.
- Pramod Kumar adds the GPIO to pinctrl mapping for the Broadcom Northstar Plus
SoCs
- Yendapally Reddy Dhananjaya Reddy adds pinctrl Device Tree nodes for the
Broadcom Northstar Plus SoCs device tree nodes
- Ray Jui adds Cygnus PCIe PHY Device Tree nodes and enables MSI for the iProc
PCI controller on Cygnus platforms
- Kapil Hali adds SMP binding documentation and Device Tree nodes for the
Northstar Plus SoCs
- Florian Fainelli adds clock provider support for the Broadcom BCM63138 DSL
SoCs by utilizing the existing iProc ARM PLL controller, this includes a
stable topic branch from Stephen Boyd to be merged
- Rafal Milecki adds missing LEDs for the Netgear R8000 router
* tag 'arm-soc/for-4.5/devicetree' of http://github.com/Broadcom/stblinux:
ARM: dts: Enable MSI support for Broadcom Cygnus
ARM: dts: Add SMP support for Broadcom NSP
dt-bindings: add SMP enable-method for Broadcom NSP
ARM: dts: enable pinctrl for Broadcom NSP
ARM: dts: enable PCIe PHY support for Cygnus
ARM: dts: Cygnus: define ngpios property in gpio controller's node
ARM: BCM5301X: Add missing Netgear R8000 LEDs
ARM: dts: BCM63xx: Add ARMPLL device tree nodes
clk: bcm: Add BCM63138 clock support
clk: iproc: Extend binding to cover BCM63138
ARM: dts: enable clock support for Broadcom NSP
ARM: dts: enable clock support for BCM5301X
ARM: dts: NSP: Add I2C support to the DT
ARM: dts: NSP: Device Tree clean-ups
dts: pinctrl: Add GPIO to Pinctrl pin mapping in DT
ARM: dts: bcm5301x: Add BCM SVK DT files
dt-bindings: Add new SoCs to bcm4708 DT bindings
ARM: dts: NSP: Add TWD Support to DT
ARM: dts: NSP: Add NAND Support to DT
ARM: dts: NSP: Add PCI support
This adds the device tree bindings for the ARM Syscon ICST
oscillators, which is a register-level interface to the
Integrated Device Technology (IDT) ICS525 and ICS307
serially programmable oscillators.
Cc: devicetree@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the devicetree binding for the cru on the rk3228 which quite similar
structured as previous clock controllers.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Renesas DIV6 clocks provide a single clock output. Hence make the
"clock-output-names" DT property optional instead of mandatory. In case
the DT property is omitted the DT node name will be used.
Rename the variable "name" to "clk_name" to make the code more similar
with fixed-factor-clock.c, and to avoid a conflict with a nested local
variable while we're at it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.
On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.
It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add documentation for the Marvell clock divider driver, which is used
to source clocks for the AXI bus, video decoder, GPU and LCD blocks.
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.
On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.
On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure
as the Cygnus and iProc chips, add a dedicated compatible string and
document that the ARMPLL node is a valid node for this chip.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Broadcom BCM63138 DSL SoCs have the same ARMPLL clocking infrastructure
as the Cygnus and iProc chips, add a dedicated compatible string and
document that the ARMPLL node is a valid node for this chip.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The H3 has a usb-phy clk register which is similar to that of earlier
SoCs, but with support for a larger number of phys. So we can simply add
a new set of clk-data and a new compatible and be done with it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Provide support for Sigma Designs Tango4 clock generator.
NOTE: This driver is incompatible with Tango3 clkgen.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[sboyd@codeaurora.org: Add kernel.h include for panic/sprintf]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a header file that defines the clock numbers for Tegra210. It is
meant to be included by device trees so that they can refer to the
clocks by symbolic name instead of numeric value.
Also add the device tree binding documentation which is largely the
same as for earlier generations of Tegra.
Extracted from a larger patch by Rhyland Klein <rklein@nvidia.com>.
Signed-off-by: Thierry Reding <treding@nvidia.com>
As usual, this is the massive branch we have for each release. Lots of
various updates and additions of hardware descriptions on existing hardware,
as well as the usual additions of new boards and SoCs.
This is also the first release where we've started mixing 64- and 32-bit
DT updates in one branch.
(Specific details on what's actually here and new is pretty easy to tell
from the diffstat, so there's little point in duplicating listing it here.)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As usual, this is the massive branch we have for each release. Lots
of various updates and additions of hardware descriptions on existing
hardware, as well as the usual additions of new boards and SoCs.
This is also the first release where we've started mixing 64- and
32-bit DT updates in one branch.
(Specific details on what's actually here and new is pretty easy to
tell from the diffstat, so there's little point in duplicating listing
it here)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
ARM: dts: uniphier: add system-bus-controller nodes
ARM64: juno: disable NOR flash node by default
ARM: dts: uniphier: add outer cache controller nodes
arm64: defconfig: Enable PCI generic host bridge by default
arm64: Juno: Add support for the PCIe host bridge on Juno R1
Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
dts/ls2080a: Update Simulator DTS to add support of various peripherals
dts/ls2080a: Remove text about writing to Free Software Foundation
dts/ls2080a: Update DTSI to add support of various peripherals
doc: DTS: Update DWC3 binding to provide reference to generic bindings
doc/bindings: Update GPIO devicetree binding documentation for LS2080A
Documentation/dts: Move FSL board-specific bindings out of /powerpc
Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
arm64: Rename FSL LS2085A SoC support code to LS2080A
arm64: Use generic Layerscape SoC family naming
ARM: dts: uniphier: add ProXstream2 Vodka board support
ARM: dts: uniphier: add ProXstream2 Gentil board support
...
- Kconfig: remove BE-only platforms from LE kernel build from Boqun Feng
- Refresh ps3_defconfig from Geoff Levand
- Emit GNU & SysV hashes for the vdso from Michael Ellerman
- Define an enum for the bolted SLB indexes from Anshuman Khandual
- Use a local to avoid multiple calls to get_slb_shadow() from Michael Ellerman
- Add gettimeofday() benchmark from Michael Neuling
- Avoid link stack corruption in __get_datapage() from Michael Neuling
- Add virt_to_pfn and use this instead of opencoding from Aneesh Kumar K.V
- Add ppc64le_defconfig from Michael Ellerman
- pseries: extract of_helpers module from Andy Shevchenko
- Correct string length in pseries_of_derive_parent() from Nathan Fontenot
- Free the MSI bitmap if it was slab allocated from Denis Kirjanov
- Shorten irq_chip name for the SIU from Christophe Leroy
- Wait 1s for secondaries to enter OPAL during kexec from Samuel Mendoza-Jonas
- Fix _ALIGN_* errors due to type difference. from Aneesh Kumar K.V
- powerpc/pseries/hvcserver: don't memset pi_buff if it is null from Colin Ian King
- Disable hugepd for 64K page size. from Aneesh Kumar K.V
- Differentiate between hugetlb and THP during page walk from Aneesh Kumar K.V
- Make PCI non-optional for pseries from Michael Ellerman
- Individual System V IPC system calls from Sam bobroff
- Add selftest of unmuxed IPC calls from Michael Ellerman
- discard .exit.data at runtime from Stephen Rothwell
- Delete old orphaned PrPMC 280/2800 DTS and boot file. from Paul Gortmaker
- Use of_get_next_parent to simplify code from Christophe Jaillet
- Paginate some xmon output from Sam bobroff
- Add some more elements to the xmon PACA dump from Michael Ellerman
- Allow the tm-syscall selftest to build with old headers from Michael Ellerman
- Run EBB selftests only on POWER8 from Denis Kirjanov
- Drop CONFIG_TUNE_CELL in favour of CONFIG_CELL_CPU from Michael Ellerman
- Avoid reference to potentially freed memory in prom.c from Christophe Jaillet
- Quieten boot wrapper output with run_cmd from Geoff Levand
- EEH fixes and cleanups from Gavin Shan
- Fix recursive fenced PHB on Broadcom shiner adapter from Gavin Shan
- Use of_get_next_parent() in of_get_ibm_chip_id() from Michael Ellerman
- Fix section mismatch warning in msi_bitmap_alloc() from Denis Kirjanov
- Fix ps3-lpm white space from Rudhresh Kumar J
- Fix ps3-vuart null dereference from Colin King
- nvram: Add missing kfree in error path from Christophe Jaillet
- nvram: Fix function name in some errors messages. from Christophe Jaillet
- drivers/macintosh: adb: fix misleading Kconfig help text from Aaro Koskinen
- agp/uninorth: fix a memleak in create_gatt_table from Denis Kirjanov
- cxl: Free virtual PHB when removing from Andrew Donnellan
- scripts/kconfig/Makefile: Allow KBUILD_DEFCONFIG to be a target from Michael Ellerman
- scripts/kconfig/Makefile: Fix KBUILD_DEFCONFIG check when building with O= from Michael Ellerman
- Freescale updates from Scott: Highlights include 64-bit book3e kexec/kdump
support, a rework of the qoriq clock driver, device tree changes including
qoriq fman nodes, support for a new 85xx board, and some fixes.
- MPC5xxx updates from Anatolij: Highlights include a driver for MPC512x
LocalPlus Bus FIFO with its device tree binding documentation, mpc512x
device tree updates and some minor fixes.
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Merge tag 'powerpc-4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
- Kconfig: remove BE-only platforms from LE kernel build from Boqun
Feng
- Refresh ps3_defconfig from Geoff Levand
- Emit GNU & SysV hashes for the vdso from Michael Ellerman
- Define an enum for the bolted SLB indexes from Anshuman Khandual
- Use a local to avoid multiple calls to get_slb_shadow() from Michael
Ellerman
- Add gettimeofday() benchmark from Michael Neuling
- Avoid link stack corruption in __get_datapage() from Michael Neuling
- Add virt_to_pfn and use this instead of opencoding from Aneesh Kumar
K.V
- Add ppc64le_defconfig from Michael Ellerman
- pseries: extract of_helpers module from Andy Shevchenko
- Correct string length in pseries_of_derive_parent() from Nathan
Fontenot
- Free the MSI bitmap if it was slab allocated from Denis Kirjanov
- Shorten irq_chip name for the SIU from Christophe Leroy
- Wait 1s for secondaries to enter OPAL during kexec from Samuel
Mendoza-Jonas
- Fix _ALIGN_* errors due to type difference, from Aneesh Kumar K.V
- powerpc/pseries/hvcserver: don't memset pi_buff if it is null from
Colin Ian King
- Disable hugepd for 64K page size, from Aneesh Kumar K.V
- Differentiate between hugetlb and THP during page walk from Aneesh
Kumar K.V
- Make PCI non-optional for pseries from Michael Ellerman
- Individual System V IPC system calls from Sam bobroff
- Add selftest of unmuxed IPC calls from Michael Ellerman
- discard .exit.data at runtime from Stephen Rothwell
- Delete old orphaned PrPMC 280/2800 DTS and boot file, from Paul
Gortmaker
- Use of_get_next_parent to simplify code from Christophe Jaillet
- Paginate some xmon output from Sam bobroff
- Add some more elements to the xmon PACA dump from Michael Ellerman
- Allow the tm-syscall selftest to build with old headers from Michael
Ellerman
- Run EBB selftests only on POWER8 from Denis Kirjanov
- Drop CONFIG_TUNE_CELL in favour of CONFIG_CELL_CPU from Michael
Ellerman
- Avoid reference to potentially freed memory in prom.c from Christophe
Jaillet
- Quieten boot wrapper output with run_cmd from Geoff Levand
- EEH fixes and cleanups from Gavin Shan
- Fix recursive fenced PHB on Broadcom shiner adapter from Gavin Shan
- Use of_get_next_parent() in of_get_ibm_chip_id() from Michael
Ellerman
- Fix section mismatch warning in msi_bitmap_alloc() from Denis
Kirjanov
- Fix ps3-lpm white space from Rudhresh Kumar J
- Fix ps3-vuart null dereference from Colin King
- nvram: Add missing kfree in error path from Christophe Jaillet
- nvram: Fix function name in some errors messages, from Christophe
Jaillet
- drivers/macintosh: adb: fix misleading Kconfig help text from Aaro
Koskinen
- agp/uninorth: fix a memleak in create_gatt_table from Denis Kirjanov
- cxl: Free virtual PHB when removing from Andrew Donnellan
- scripts/kconfig/Makefile: Allow KBUILD_DEFCONFIG to be a target from
Michael Ellerman
- scripts/kconfig/Makefile: Fix KBUILD_DEFCONFIG check when building
with O= from Michael Ellerman
- Freescale updates from Scott: Highlights include 64-bit book3e
kexec/kdump support, a rework of the qoriq clock driver, device tree
changes including qoriq fman nodes, support for a new 85xx board, and
some fixes.
- MPC5xxx updates from Anatolij: Highlights include a driver for
MPC512x LocalPlus Bus FIFO with its device tree binding
documentation, mpc512x device tree updates and some minor fixes.
* tag 'powerpc-4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (106 commits)
powerpc/msi: Fix section mismatch warning in msi_bitmap_alloc()
powerpc/prom: Use of_get_next_parent() in of_get_ibm_chip_id()
powerpc/pseries: Correct string length in pseries_of_derive_parent()
powerpc/e6500: hw tablewalk: make sure we invalidate and write to the same tlb entry
powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s)
powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA FMan
powerpc/fsl: Add #clock-cells and clockgen label to clockgen nodes
powerpc: handle error case in cpm_muram_alloc()
powerpc: mpic: use IRQCHIP_SKIP_SET_WAKE instead of redundant mpic_irq_set_wake
powerpc/book3e-64: Enable kexec
powerpc/book3e-64/kexec: Set "r4 = 0" when entering spinloop
powerpc/booke: Only use VIRT_PHYS_OFFSET on booke32
powerpc/book3e-64/kexec: Enable SMP release
powerpc/book3e-64/kexec: create an identity TLB mapping
powerpc/book3e-64: Don't limit paca to 256 MiB
powerpc/book3e/kdump: Enable crash_kexec_wait_realmode
powerpc/book3e: support CONFIG_RELOCATABLE
powerpc/booke64: Fix args to copy_and_flush
powerpc/book3e-64: rename interrupt_end_book3e with __end_interrupts
powerpc/e6500: kexec: Handle hardware threads
...
This pull request contains the DT changes for BCM2835 in 4.4. It
pulls in clk/clk-bcm2835 (which Stephen Boyd has said would be stable)
because the DT changes to enable the clock driver need the driver
itself to be present. These changes include the following:
- Eric Anholt, moves the bcm2835 clock driver under bcm/ where it belongs with
other Broadcom clock providers drivers, defines the binding for new clock
driver, adds support for programming the BCM2835 audio domain, adds the DDC I2C
controller to Device Tree, and finally migrates the Device Tree to use the new
clock driver binding
- Lubomir Rintel adds support for the Raspberry Pi Model A+ and B revision 2, and
remove the I2S controller which is non-existent on Raspberry Pi Model B
- Stefan Wahren adds an uart0 label for referencing the UART adapter
* tag 'arm/soc/for-4.4/rpi-dt-v2' of https://github.com/Broadcom/stblinux:
ARM: bcm2835: Add the DDC I2C controller to the device tree.
ARM: bcm2835: Switch to using the new clock driver support.
ARM: bcm2835: dt: Add Raspberry Pi Model A+
ARM: bcm2835: dt: Add Raspberry Pi Model B rev2
ARM: bcm2835: dt: Raspberry Pi Model B had no I2S
ARM: bcm2835: add label for uart0
clk: bcm2835: Add support for programming the audio domain clocks
clk: bcm2835: Add binding docs for the new platform clock driver.
clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.
Signed-off-by: Olof Johansson <olof@lixom.net>
* clk-iproc:
clk: iproc: define Broadcom NS2 iProc clock binding
clk: iproc: define Broadcom NSP iProc clock binding
clk: ns2: add clock support for Broadcom Northstar 2 SoC
clk: iproc: Separate status and control variables
clk: iproc: Split off dig_filter
clk: iproc: Add PLL base write function
clk: nsp: add clock support for Broadcom Northstar Plus SoC
clk: iproc: Add PWRCTRL support
clk: cygnus: Convert all macros to all caps
ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
Document the device tree bindings for Broadcom Northstar 2 architecture
based clock controller
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Document the device tree bindings for Broadcom Northstar Plus
architecture based clock controller
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The device tree should describe the chips (or chip-like subblocks) in
the system, but it generally does not describe individual registers --
it should identify, rather than describe, a programming interface.
This has not been the case with the QorIQ clockgen nodes. The
knowledge of what each bit setting of CLKCnCSR means is encoded in
three places (binding, pll node, and mux node), and the last also needs
to know which options are valid on a particular chip. All three of
these locations are considered stable ABI, making it difficult to fix
mistakes (of which I have found several), much less refactor the
abstraction to be able to address problems, limitations, or new chips.
Under the current binding, a pll clock specifier of 2 means that the
PLL is divided by 4 -- and the driver implements this, unless there
happen to be four clock-output-names rather than 3, in which case it
interprets it as PLL divided by 3. This does not appear in the binding
documentation at all. That hack is now considered stable ABI.
The current device tree nodes contain errors, such as saying that
T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
The current binding also ignores some restrictions on clock selection,
such as p5020's requirement that if a core uses the "wrong" PLL, that
PLL must be clocked lower than the "correct" PLL and be at most 80% of
the rated CPU frequency.
Possibly because of the lack of the ability to express such nuance in
the binding, some valid options are omitted from the device trees, such
as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
PLL1 (again, only if they are at most 80% of rated CPU frequency).
This omission, combined with excessive caution in the cpufreq driver
(addressed in a subsequent patch), means that currently on a 1500 MHz
p4080 with typical PLL configuration, cpufreq can lower the frequency
to 1200 MHz on half the CPUs and do nothing on the others. With this
patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
rev3 p4080 half can be lowered to 750 MHz and the other half to 600
MHz.
The current binding only deals with CPU clocks. To describe FMan in
the device tree, we need to describe its clock. Some chips have
additional muxes that work like the CPU muxes, but are not described in
the device tree. Others require inspecting the Reset Control Word to
determine which PLL is used. Rather than continue to extend this mess,
replace it. Have the driver bind to the chip-specific clockgen
compatible, and keep the detailed description of quirky chip variations
in the driver, where it can be easily fixed, refactored, and extended.
Older device trees will continue to work (including a workaround for
old ls1021a device trees that are missing compatible and reg in the
clockgen node, which even the old binding required). The pll/mux
details in old device trees will be ignored, but "clocks" properties
pointing at the old nodes will still work, and be directed at the
corresponding new clock.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse
Generator) and MSSR (Module Standby and Software Reset) blocks are
intimately connected, and share the same register block.
Hence it makes sense to describe these two blocks using a
single device node in DT, instead of using a hierarchical structure with
multiple nodes, using a mix of generic and SoC-specific bindings.
These new DT bindings are intended to replace the existing DT bindings
for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock")
and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs.
This will make it easier to add module reset support later, which is
currently not implemented, and difficult to achieve using the existing
bindings due to the intertwined register layout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Magnus Damm <damm+renesas@opensource.se>
clock controller nodes which also support power domains (gdscs') need
to have a #power-domain-cells property. Add these for gcc and mmcc
nodes of msm8974, gcc of apq8084 and msm8916.
Also update gcc and mmcc bindings for it.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
* clk-bcm2835:
clk: bcm2835: Add support for programming the audio domain clocks
clk: bcm2835: Add binding docs for the new platform clock driver.
clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Drop clk.h include, remove some casts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Previously we've only supported a few fixed clocks based on
assumptions about how the firmware sets up the clocks, but this
binding will let us control the actual (audio power domain) clock
manager.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents can generate divided rates.
This would allow a peripheral to have finer grained clocks for generating
a baud rate, clocking an asynchronous part or having more
options in frequency.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[sboyd@codeaurora.org: Transition to new clk_hw provider APIs]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- ACPICA update to upstream revision 20150818 including method
tracing extensions to allow more in-depth AML debugging in the
kernel and a number of assorted fixes and cleanups (Bob Moore,
Lv Zheng, Markus Elfring).
- ACPI sysfs code updates and a documentation update related to
AML method tracing (Lv Zheng).
- ACPI EC driver fix related to serialized evaluations of _Qxx
methods and ACPI tools updates allowing the EC userspace tool
to be built from the kernel source (Lv Zheng).
- ACPI processor driver updates preparing it for future
introduction of CPPC support and ACPI PCC mailbox driver
updates (Ashwin Chaugule).
- ACPI interrupts enumeration fix for a regression related
to the handling of IRQ attribute conflicts between MADT
and the ACPI namespace (Jiang Liu).
- Fixes related to ACPI device PM (Mika Westerberg, Srinidhi Kasagar).
- ACPI device registration code reorganization to separate the
sysfs-related code and bus type operations from the rest (Rafael
J Wysocki).
- Assorted cleanups in the ACPI core (Jarkko Nikula, Mathias Krause,
Andy Shevchenko, Rafael J Wysocki, Nicolas Iooss).
- ACPI cpufreq driver and ia64 cpufreq driver fixes and cleanups
(Pan Xinhui, Rafael J Wysocki).
- cpufreq core cleanups on top of the previous changes allowing it
to preseve its sysfs directories over system suspend/resume (Viresh
Kumar, Rafael J Wysocki, Sebastian Andrzej Siewior).
- cpufreq fixes and cleanups related to governors (Viresh Kumar).
- cpufreq updates (core and the cpufreq-dt driver) related to the
turbo/boost mode support (Viresh Kumar, Bartlomiej Zolnierkiewicz).
- New DT bindings for Operating Performance Points (OPP), support
for them in the OPP framework and in the cpufreq-dt driver plus
related OPP framework fixes and cleanups (Viresh Kumar).
- cpufreq powernv driver updates (Shilpasri G Bhat).
- New cpufreq driver for Mediatek MT8173 (Pi-Cheng Chen).
- Assorted cpufreq driver (speedstep-lib, sfi, integrator) cleanups
and fixes (Abhilash Jindal, Andrzej Hajda, Cristian Ardelean).
- intel_pstate driver updates including Skylake-S support, support
for enabling HW P-states per CPU and an additional vendor bypass
list entry (Kristen Carlson Accardi, Chen Yu, Ethan Zhao).
- cpuidle core fixes related to the handling of coupled idle states
(Xunlei Pang).
- intel_idle driver updates including Skylake Client support and
support for freeze-mode-specific idle states (Len Brown).
- Driver core updates related to power management (Andy Shevchenko,
Rafael J Wysocki).
- Generic power domains framework fixes and cleanups (Jon Hunter,
Geert Uytterhoeven, Rajendra Nayak, Ulf Hansson).
- Device PM QoS framework update to allow the latency tolerance
setting to be exposed to user space via sysfs (Mika Westerberg).
- devfreq support for PPMUv2 in Exynos5433 and a fix for an incorrect
exynos-ppmu DT binding (Chanwoo Choi, Javier Martinez Canillas).
- System sleep support updates (Alan Stern, Len Brown, SungEun Kim).
- rockchip-io AVS support updates (Heiko Stuebner).
- PM core clocks support fixup (Colin Ian King).
- Power capping RAPL driver update including support for Skylake H/S
and Broadwell-H (Radivoje Jovanovic, Seiichi Ikarashi).
- Generic device properties framework fixes related to the handling
of static (driver-provided) property sets (Andy Shevchenko).
- turbostat and cpupower updates (Len Brown, Shilpasri G Bhat,
Shreyas B Prabhu).
/
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Merge tag 'pm+acpi-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management and ACPI updates from Rafael Wysocki:
"From the number of commits perspective, the biggest items are ACPICA
and cpufreq changes with the latter taking the lead (over 50 commits).
On the cpufreq front, there are many cleanups and minor fixes in the
core and governors, driver updates etc. We also have a new cpufreq
driver for Mediatek MT8173 chips.
ACPICA mostly updates its debug infrastructure and adds a number of
fixes and cleanups for a good measure.
The Operating Performance Points (OPP) framework is updated with new
DT bindings and support for them among other things.
We have a few updates of the generic power domains framework and a
reorganization of the ACPI device enumeration code and bus type
operations.
And a lot of fixes and cleanups all over.
Included is one branch from the MFD tree as it contains some
PM-related driver core and ACPI PM changes a few other commits are
based on.
Specifics:
- ACPICA update to upstream revision 20150818 including method
tracing extensions to allow more in-depth AML debugging in the
kernel and a number of assorted fixes and cleanups (Bob Moore, Lv
Zheng, Markus Elfring).
- ACPI sysfs code updates and a documentation update related to AML
method tracing (Lv Zheng).
- ACPI EC driver fix related to serialized evaluations of _Qxx
methods and ACPI tools updates allowing the EC userspace tool to be
built from the kernel source (Lv Zheng).
- ACPI processor driver updates preparing it for future introduction
of CPPC support and ACPI PCC mailbox driver updates (Ashwin
Chaugule).
- ACPI interrupts enumeration fix for a regression related to the
handling of IRQ attribute conflicts between MADT and the ACPI
namespace (Jiang Liu).
- Fixes related to ACPI device PM (Mika Westerberg, Srinidhi
Kasagar).
- ACPI device registration code reorganization to separate the
sysfs-related code and bus type operations from the rest (Rafael J
Wysocki).
- Assorted cleanups in the ACPI core (Jarkko Nikula, Mathias Krause,
Andy Shevchenko, Rafael J Wysocki, Nicolas Iooss).
- ACPI cpufreq driver and ia64 cpufreq driver fixes and cleanups (Pan
Xinhui, Rafael J Wysocki).
- cpufreq core cleanups on top of the previous changes allowing it to
preseve its sysfs directories over system suspend/resume (Viresh
Kumar, Rafael J Wysocki, Sebastian Andrzej Siewior).
- cpufreq fixes and cleanups related to governors (Viresh Kumar).
- cpufreq updates (core and the cpufreq-dt driver) related to the
turbo/boost mode support (Viresh Kumar, Bartlomiej Zolnierkiewicz).
- New DT bindings for Operating Performance Points (OPP), support for
them in the OPP framework and in the cpufreq-dt driver plus related
OPP framework fixes and cleanups (Viresh Kumar).
- cpufreq powernv driver updates (Shilpasri G Bhat).
- New cpufreq driver for Mediatek MT8173 (Pi-Cheng Chen).
- Assorted cpufreq driver (speedstep-lib, sfi, integrator) cleanups
and fixes (Abhilash Jindal, Andrzej Hajda, Cristian Ardelean).
- intel_pstate driver updates including Skylake-S support, support
for enabling HW P-states per CPU and an additional vendor bypass
list entry (Kristen Carlson Accardi, Chen Yu, Ethan Zhao).
- cpuidle core fixes related to the handling of coupled idle states
(Xunlei Pang).
- intel_idle driver updates including Skylake Client support and
support for freeze-mode-specific idle states (Len Brown).
- Driver core updates related to power management (Andy Shevchenko,
Rafael J Wysocki).
- Generic power domains framework fixes and cleanups (Jon Hunter,
Geert Uytterhoeven, Rajendra Nayak, Ulf Hansson).
- Device PM QoS framework update to allow the latency tolerance
setting to be exposed to user space via sysfs (Mika Westerberg).
- devfreq support for PPMUv2 in Exynos5433 and a fix for an incorrect
exynos-ppmu DT binding (Chanwoo Choi, Javier Martinez Canillas).
- System sleep support updates (Alan Stern, Len Brown, SungEun Kim).
- rockchip-io AVS support updates (Heiko Stuebner).
- PM core clocks support fixup (Colin Ian King).
- Power capping RAPL driver update including support for Skylake H/S
and Broadwell-H (Radivoje Jovanovic, Seiichi Ikarashi).
- Generic device properties framework fixes related to the handling
of static (driver-provided) property sets (Andy Shevchenko).
- turbostat and cpupower updates (Len Brown, Shilpasri G Bhat,
Shreyas B Prabhu)"
* tag 'pm+acpi-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (180 commits)
cpufreq: speedstep-lib: Use monotonic clock
cpufreq: powernv: Increase the verbosity of OCC console messages
cpufreq: sfi: use kmemdup rather than duplicating its implementation
cpufreq: drop !cpufreq_driver check from cpufreq_parse_governor()
cpufreq: rename cpufreq_real_policy as cpufreq_user_policy
cpufreq: remove redundant 'policy' field from user_policy
cpufreq: remove redundant 'governor' field from user_policy
cpufreq: update user_policy.* on success
cpufreq: use memcpy() to copy policy
cpufreq: remove redundant CPUFREQ_INCOMPATIBLE notifier event
cpufreq: mediatek: Add MT8173 cpufreq driver
dt-bindings: mediatek: Add MT8173 CPU DVFS clock bindings
PM / Domains: Fix typo in description of genpd_dev_pm_detach()
PM / Domains: Remove unusable governor dummies
PM / Domains: Make pm_genpd_init() available to modules
PM / domains: Align column headers and data in pm_genpd_summary output
powercap / RAPL: disable the 2nd power limit properly
tools: cpupower: Fix error when running cpupower monitor
PM / OPP: Drop unlikely before IS_ERR(_OR_NULL)
PM / OPP: Fix static checker warning (broken 64bit big endian systems)
...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- Cleanups for Renesas shmobile platforms
- Lots of added devices on LPC18xx
- Lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some branches
that are primarily merged through the clock tree.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"Ladies and gentlemen, we proudly announce to you the latest branch of
ARM device tree contents for the mainline kernel. Come and see, come
and see!
No less than twentythree thousand lines of additions! Just imagine the
joy you will have of using your mainline kernel on newly supported
hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
UniPhier hardware!
For those of you feeling less adventurous, added hardware support on
platforms such as TI DM814x and Gumstix Overo platforms might be more
of your liking.
We've got something for everyone here!
Ahem. Cough. So, anyway...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- cleanups for Renesas shmobile platforms
- lots of added devices on LPC18xx
- lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some
branches that are primarily merged through the clock tree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: rockchip: correct regulator power states for suspend
ARM: dts: rockchip: correct regulator PM properties
ARM: dts: vexpress: Use assigned-clock-parents for sp810
pinctrl: tegra: Only set the gpio range if needed
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
...
Some releases this branch is nearly empty, others we have more stuff. It
tends to gather drivers that need SoC modification or dependencies such
that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- Memory controller work for ARM's PL172 memory controller
- Reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some releases this branch is nearly empty, others we have more stuff.
It tends to gather drivers that need SoC modification or dependencies
such that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- memory controller work for ARM's PL172 memory controller
- reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller
per-SoC support"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
ARM: tegra: Disable cpuidle if PSCI is available
soc/tegra: pmc: Use existing pclk reference
soc/tegra: pmc: Remove unnecessary return statement
soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
memory: tegra: Add Tegra210 support
memory: tegra: Add support for a variable-size client ID bitfield
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: Add CPG/MSTP Clock Domain support
ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
MIPS: ath79: Add the reset controller to the AR9132 dtsi
reset: Add a driver for the reset controller on the AR71XX/AR9XXX
devicetree: Add bindings for the ATH79 reset controller
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
doc: dt: add documentation for lpc1850-rgu reset driver
...
This patch adds the clock and regulator consumer properties part of
document for CPU DVFS clocks on Mediatek MT8173 SoC.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
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Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.3-rc1
This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
These Ux500 clocks have been around for years and were never
properly documented. Add the proper binding documentation.
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Document the new compatible for stub clock driver which is used for CPU
and DDR's dynamic frequency scaling.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
Venice2 and Jetson TK1. This also enables support for the PMU hardware
found on Tegra124, which among other things, can be used for performance
measurements.
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Merge tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
ARM: tegra: Devicetree changes for v4.3-rc1
Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
Venice2 and Jetson TK1. This also enables support for the PMU hardware
found on Tegra124, which among other things, can be used for performance
measurements.
* tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
pinctrl: tegra: Only set the gpio range if needed
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
clk: tegra: Add Tegra124 DFLL clocksource platform driver
clk: tegra: Add DFLL DVCO reset control for Tegra124
clk: tegra: Introduce ability for SoC-specific reset control callbacks
clk: tegra: Add functions for parsing CVB tables
clk: tegra: Add closed loop support for the DFLL
clk: tegra: Add library for the DFLL clock source (open-loop mode)
clk: tegra: Add binding for the Tegra124 DFLL clocksource
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add audio and eTSEC device support and update dspi node for LS1021A.
- Add initial i.MX6UL and imx6ul-14x14-evk board support, and enable
a bunch of device support for i.MX6UL, including RTC, power key, USB,
QSPI, and dual FEC.
- Enable HDMI and LVDS dual display support for a few imx6qdl boards.
- Support of imx6sl-warp board rev1.12, the version which will be
publicly available for the customers.
- A few i.MX7D device additions, watchdog, cortex-a7 coresight
components, RTC, power key, power off.
- Some Vybrid updates: add device support for I2C, QSPI, eSDHC etc.,
update ADC node, and define stdout-path property.
- A few random updates for i.MX27 and i.MX53 devices.
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Merge tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
The i.MX device tree updates for 4.3:
- Add audio and eTSEC device support and update dspi node for LS1021A.
- Add initial i.MX6UL and imx6ul-14x14-evk board support, and enable
a bunch of device support for i.MX6UL, including RTC, power key, USB,
QSPI, and dual FEC.
- Enable HDMI and LVDS dual display support for a few imx6qdl boards.
- Support of imx6sl-warp board rev1.12, the version which will be
publicly available for the customers.
- A few i.MX7D device additions, watchdog, cortex-a7 coresight
components, RTC, power key, power off.
- Some Vybrid updates: add device support for I2C, QSPI, eSDHC etc.,
update ADC node, and define stdout-path property.
- A few random updates for i.MX27 and i.MX53 devices.
* tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
ARM: dts: imx6ul: add snvs power key support
ARM: dts: imx6ul: add RTC support
ARM: dts: imx6ul: enable GPC as extended interrupt controller
ARM: dts: imx6sx: correct property name for wakeup source
ARM: dts: add property for maximum ADC clock frequencies
ARM: dts: imx7d: enable snvs rtc, onoffkey and power off
ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support
ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL
ARM: dts: imx27: add support of internal rtc
ARM: dts: vf-colibri: define stdout-path property
ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
ARM: dts: ls1021a: Add the eTSEC controller nodes
ARM: dts: imx6ul: add qspi support
ARM: dts: imx6ul: fix low case define in imx6ul-pinfunc.h
ARM: dts: imx6ul: add usb host and function support
ARM: dts: vfxxx: Add io-channel-cells property for ADC node
ARM: dts: ls1021a: Add dts nodes for audio on LS1021A
ARM: imx6qdl-sabreauto.dtsi: enable USB support
ARM: dts: imx: update snvs to use syscon access register
ARM: dts: imx: add imx6ul and imx6ul evk board support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This part just add necessary change to boot imx6ul.
Update clock and pinctrl for imx6ul
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a common clock driver for basic gpio controlled clock multiplexers.
This driver can be used for devices like 5V41068A or 831721I from IDT
or for discrete multiplexer circuits. The 'select' pin selects one of
two parent clocks.
Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
[sboyd@codeaurora.org: Fix error paths to free memory and do it
in the correct order]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the devicetree binding for the cru on the rk3368 which quite similar
structured as previous clock controllers.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers and updates to existing ones, as usual. There are some fixes to
the framework itself and several cleanups for sparse warnings, etc.
Please consider pulling.
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Merge tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clock framework updates from Michael Turquette:
"The changes to the common clock framework for 4.2 are dominated by new
drivers and updates to existing ones, as usual.
There are some fixes to the framework itself and several cleanups for
sparse warnings, etc"
* tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
clk: stm32: Add clock driver for STM32F4[23]xxx devices
dt-bindings: Document the STM32F4 clock bindings
cpufreq: exynos: remove Exynos4210 specific cpufreq driver support
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210
clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock
clk: samsung: add infrastructure to register cpu clocks
clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support
doc: dt: add documentation for lpc1850-ccu clk driver
clk: add lpc18xx ccu clk driver
doc: dt: add documentation for lpc1850-cgu clk driver
clk: add lpc18xx cgu clk driver
clk: keystone: add support for post divider register for main pll
clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED
clk: cygnus: remove Cygnus dummy clock binding
clk: cygnus: add clock support for Broadcom Cygnus
clk: Change bcm clocks build dependency
clk: iproc: add initial common clock support
clk: iproc: define Broadcom iProc clock binding
MAINTAINERS: update email for Michael Turquette
clk: meson: add some error handling in meson_clk_register_cpu()
...
Pull MIPS updates from Ralf Baechle:
- Improvements to the tlb_dump code
- KVM fixes
- Add support for appended DTB
- Minor improvements to the R12000 support
- Minor improvements to the R12000 support
- Various platform improvments for BCM47xx
- The usual pile of minor cleanups
- A number of BPF fixes and improvments
- Some improvments to the support for R3000 and DECstations
- Some improvments to the ATH79 platform support
- A major patchset for the JZ4740 SOC adding support for the CI20 platform
- Add support for the Pistachio SOC
- Minor BMIPS/BCM63xx platform support improvments.
- Avoid "SYNC 0" as memory barrier when unlocking spinlocks
- Add support for the XWR-1750 board.
- Paul's __cpuinit/__cpuinitdata cleanups.
- New Malta CPU board support large memory so enable ZONE_DMA32.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
MIPS: spinlock: Adjust arch_spin_lock back-off time
MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
MIPS: BCM47xx: Simplify handling SPROM revisions
MIPS: Cobalt Don't use module_init in non-modular MTD registration.
MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
MIPS: use for_each_sg()
MIPS: BCM47xx: Don't select BCMA_HOST_PCI
MIPS: BCM47xx: Add helper variable for storing NVRAM length
MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
MIPS: Replace smp_mb with release barrier function in unlocks.
MIPS: i8259: DT support
MIPS: Malta: Basic DT plumbing
MIPS: include errno.h for ENODEV in mips-cm.h
MIPS: Define GCR_GIC_STATUS register fields
MIPS: BPF: Introduce BPF ASM helpers
MIPS: BPF: Use BPF register names to describe the ABI
MIPS: BPF: Move register definition to the BPF header
MIPS: net: BPF: Replace RSIZE with SZREG
MIPS: BPF: Free up some callee-saved registers
MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
...
As usual, quite a few device-tree updates in ARM land. There was ome
minor churn in DTs due to relicensing under a dual-license, and lots
of little additions of new peripherals, features etc, but nothing
really exciting to call to your attention. Some higlights, focsuing
on support for new SoCs and boards:
- AT91: new boards: Overkiz, Acme Systems' Arietta G25
- tegra: HDA support
- bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U
- mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
boards, DLink DNS-327L
- OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50
- ARM: added support for Juno r1 board
- sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G
- imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
Gateworks GW5510, and aristainetos2 boards
- hisilicon: hi6220 SoC support; new boards: 96boards hikey
Conflicts: None
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Kevin Hilman:
"As usual, quite a few device-tree updates in ARM land. There was one
minor churn in DTs due to relicensing under a dual-license, and lots
of little additions of new peripherals, features etc, but nothing
really exciting to call to your attention. Some higlights, focsuing
on support for new SoCs and boards:
- AT91: new boards: Overkiz, Acme Systems' Arietta G25
- tegra: HDA support
- bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS
RT-AC87U
- mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
boards, DLink DNS-327L
- OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill
SL50
- ARM: added support for Juno r1 board
- sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33,
Mele A1000G
- imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
Gateworks GW5510, and aristainetos2 boards
- hisilicon: hi6220 SoC support; new boards: 96boards hikey"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits)
ARM: hisi: revert changes from hisi/hip04-dt branch
ARM: nomadik: set proper compatible for accelerometer
ARM64: juno: add GPIO keys
ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes
ARM: dts: Introduce STM32F429 MCU
ARM: socfpga: dts: enable ethernet for Arria10 devkit
ARM: dts: k2l: fix the netcp range size
ARM: dts: k2e: fix the netcp range size
ARM: dts: k2hk: fix the netcp range size
ARM: dts: k2l-evm: Add device bindings for netcp driver
ARM: dts: k2e-evm: Add device bindings for netcp driver
ARM: dts: k2hk-evm: Add device bindings for netcp driver
ARM: BCM5301X: Add DT for Asus RT-AC87U
ARM: BCM5301X: add IRQ numbers for PCIe controller
ARM: BCM5301X: add NAND flash chip description
arm64: dts: Add dts files for Hisilicon Hi6220 SoC
clk: hi6220: Document devicetree bindings for hi6220 clock
arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
ARM: at91/dt: sama5d4ek: mci0 uses slot 0
ARM: at91/dt: kizbox: fix mismatch LED PWM device
...
Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC
Conflicts:
arch/arm/mach-socfpga/core.h
Trivial remove/remove conflict with our cleanup branch.
Resolution: remove both sides
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform support updates from Kevin Hilman:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. Some highlights from this round:
- sunxi: SMP support for A23 SoC
- socpga: big-endian support
- pxa: conversion to common clock framework
- bcm: SMP support for BCM63138
- imx: support new I.MX7D SoC
- zte: basic support for ZX296702 SoC"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
ARM: zx: Add basic defconfig support for ZX296702
ARM: dts: zx: add an initial zx296702 dts and doc
clk: zx: add clock support to zx296702
dt-bindings: Add #defines for ZTE ZX296702 clocks
ARM: socfpga: fix build error due to secondary_startup
MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
ARM: ep93xx: simone: support for SPI-based MMC/SD cards
MAINTAINERS: update Shawn's email to use kernel.org one
ARM: socfpga: support suspend to ram
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
ARM: EXYNOS: register power domain driver from core_initcall
ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
ARM: SAMSUNG: Constify platform_device_id
ARM: EXYNOS: Constify irq_domain_ops
ARM: EXYNOS: add coupled cpuidle support for Exynos3250
ARM: EXYNOS: add exynos_get_boot_addr() helper
ARM: EXYNOS: add exynos_set_boot_addr() helper
ARM: EXYNOS: make exynos_core_restart() less verbose
ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
...
This adds documentation of device tree bindings for the clock related
portions of the STM32 RCC block.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This contains the EMC clock driver that's been exhaustively reviewed and
tested. It also includes a change to the clock core that allows a clock
provider to perform low-level reparenting of clocks. This is required by
the EMC clock driver because the reparenting needs to be done at a very
specific point in time during the EMC frequency switch.
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Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.2-rc1
This contains the EMC clock driver that's been exhaustively reviewed and
tested. It also includes a change to the clock core that allows a clock
provider to perform low-level reparenting of clocks. This is required by
the EMC clock driver because the reparenting needs to be done at a very
specific point in time during the EMC frequency switch.
Add DT binding documentation for lpc1850-cgu driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
One error fix, and one patch to add support for the USB clock found on the
Allwinner A23 and A33
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Merge tag 'sunxi-clocks-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clocks additions for 4.2
One error fix, and one patch to add support for the USB clock found on the
Allwinner A23 and A33
Remove old Cygnus dummy clock binding document, as it's replaced by
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Document the device tree binding for Broadcom iProc architecture based
clock controller
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Add initial dts file and document for ZX296702 and board ZX296702-AD1.
More peripherals will be added later.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Merge tag 'v4.1-rc6' into next/dt
Linux 4.1-rc6
Conflicts:
arch/arm/boot/dts/zynq-7000.dtsi
Resolution summary:
Mainline had an earlier version of the commit, resolve in favor of the
newer patch in next/dt branch.
- Add device tree for i.MX7D SoC and imx7d-sdb board
- New i.MX6 board support: Armadeus Systems APF6, Gateworks GW5510,
and aristainetos2 boards
- Change LVDS to use simple-panel for nitrogen6x and sabrelite boards
- Add Wifi/Bluetooth devices support for cubox-i board
- Remove unused regulators and correct OTG roles setting for
imx6sl-warp board
- Add I2C support for imx23-olinuxino board
- Move imx6qdl HDMI device to a better place
- Add power-domain for imx6qdl CODA device
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Merge tag 'imx-dt-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
The i.MX device tree changes for 4.2:
- Add device tree for i.MX7D SoC and imx7d-sdb board
- New i.MX6 board support: Armadeus Systems APF6, Gateworks GW5510,
and aristainetos2 boards
- Change LVDS to use simple-panel for nitrogen6x and sabrelite boards
- Add Wifi/Bluetooth devices support for cubox-i board
- Remove unused regulators and correct OTG roles setting for
imx6sl-warp board
- Add I2C support for imx23-olinuxino board
- Move imx6qdl HDMI device to a better place
- Add power-domain for imx6qdl CODA device
* tag 'imx-dt-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
ARM: dts: imx6dl: add imx6dl gpt specific compatible string
ARM: dts: imx6: add DT for aristainetos2 board
ARM: dts: cubox-i/hummingboard: Fix the license text
ARM: dts: sabrelite: use simple-panel instead of display-timings for LVDS0
ARM: dts: nitrogen6x: use simple-panel instead of display-timings for LVDS0
ARM: dts: add imx7d-sdb support
ARM: dts: add imx7d soc dtsi file
ARM: dts: Armadeus Systems APF6 family support (i.MX6)
ARM: dts: vf610: Nomenclature fixup for PTC12 pin used in RMII mode.
ARM: dts: cubox-i: add support for Broadcom Wifi/Bluetooth devices
Document: dt: binding: imx: update document for imx7d support
ARM: dts: imx6qdl: Add power-domain phandle to CODA device node
ARM: dts: Gateworks GW5510 support (i.MX6)
ARM: dts: imx6sl-warp: Fix OTG roles
ARM: dts: imx6sl-warp: Remove USB regulators
ARM: dts: imx6sl-warp: Remove unused regulator
ARM: dts: add pinfunc include file to support imx7d
ARM: mxs: fix in tree users of ssd1306
ARM: dts: imx6qdl-hummingboard: Add PCIe support
ARM: dts: imx23-olinuxino: Add i2c support
...
* clk-meson8b:
clk: meson8b: Add support for Meson8b clocks
clk: meson: Document bindings for Meson8b clock controller
clk: meson: Add support for Meson clock controller
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Even if not documented in the datasheet, the Armada 370 SoC can actually
gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA
gateclk in the crypto node.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This part just add necessary change to boot imx7d.
Update clock, pinctrl and gpt for imx7d
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found
on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic
interface which gets enabled by almost the same bits as used on
the a31 for the 3rd phy, but not exactly the same bits so we need
a new compatible for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The generic RZ CPG compatible value is mandatory, as the driver uses
only this value for matching. Document that this is a fallback that
must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic R-Car Gen2 CPG compatible value is mandatory, as the driver
uses only this value for matching. Document that this is a fallback
that must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic MSTP gate clocks compatible value is mandatory, as the
driver uses only this value for matching. Document that this is a
fallback that must be present.
Also fix a typo (missing plural "s") in the compatible value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The generic CPG DIV6 clock compatible value is mandatory, as the driver
uses only this value for matching. Document that this is a fallback
that must be present.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
the hardware node includes both clock and reset support, so it
is named as "car".
this patch implements Flexible clocks(mux, divider, gate), Selectable
clock(mux, divider, gate), root clock(gate),leaf clock(gate), others.
it also implements the reset controller functionality.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The Berlin clock documentation was part of the Marvell Berlin SoC
documentation because the Berlin clock configuration was inside the
chip controller. With the recent rework of the chip and system
controller handling (now all sub-devices of the soc and system
controller nodes are registred with simple-mfd, and each device has its
own sub-node), the documentation of the Berlin clock driver can be moved
to the generic clock documentation directory.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This adds the clock binding documentation for the Marvell PXA1928 SOC.
The PXA1928 has 3 clock control blocks for different subsystems of the
chip.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The binding uses assigned-clock-parents when it should use
assigned-clock-rates. Furthermore, the part that describes how
they relate to the assigned-clocks property is not clear about
what is related. Correct and clarify this part of the binding.
Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This property contains a phandle to the EMC driver that is needed by the
EMC clock to request the EMC driver to do its part of the clock change
sequence.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The EMC clock needs some extra information for changing its rate.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Since the introduction of clk-si5351 the way we should deal with DT provided
clocks has changed from indexed to named clock phandles. Amend the binding
documentation to reflect named clock phandles by clock-names property.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
uart -> serial
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The changes here belong to two main platforms:
- Atmel At91 is flipping the bit and going multiplatform. This includes some
cleanups and removal of code, and the final flip of config dependencies
- Shmobile has several platforms that are going multiplatform, but this
branch also contains a bunch of cleanups that they weren't able to keep
separate in a good way. THere's also a removal of one of their SoCs and the
corresponding boards (sh7372 and mackerel).
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Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform code changes from Olof Johansson:
"The changes here belong to two main platforms:
- Atmel At91 is flipping the bit and going multiplatform. This
includes some cleanups and removal of code, and the final flip of
config dependencies
- Shmobile has several platforms that are going multiplatform, but
this branch also contains a bunch of cleanups that they weren't
able to keep separate in a good way. THere's also a removal of one
of their SoCs and the corresponding boards (sh7372 and mackerel)"
* tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (67 commits)
ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
ARM: at91/pm: move the standby functions to pm.c
ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected
ARM: at91: add a Kconfig dependency on multi-platform
ARM: at91: drop AT91_TIMER_HZ
ARM: at91: remove hardware.h
ARM: at91: remove SoC headers
ARM: at91: remove useless mach/cpu.h
ARM: at91: remove unused headers
ARM: at91: switch at91_dt_defconfig to multiplatform
ARM: at91: switch to multiplatform
ARM: shmobile: r8a7778: enable multiplatform target
ARM: shmobile: bockw: add sound to DT
ARM: shmobile: r8a7778: add sound to DT
ARM: shmobile: bockw: add devices hooked up to i2c0 to DT
DT: i2c: add trivial binding for OKI ML86V7667 video decoder
ARM: shmobile: r8a7778: common clock framework CPG driver
ARM: shmobile: bockw dts: set extal clock frequency
ARM: shmobile: bockw dts: Move Ethernet node to BSC
ARM: shmobile: r8a73a4: Remove legacy code
...
drivers and updates to existing ones for feature enhancements and bug
fixes. There is more churn than usual in the framework core due to the
change to introduce per-user unique struct clk pointers in 4.0. This
caused several regressions to surface, some of which were sent as fixes
to 4.0. New generic clock drivers were added for GPIO- and PWM-based
clock controllers. Additionally the common clk-divider code recieved
several fixes to the way it rounds rates.
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Merge tag 'clk-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clock framework updates from Michael Turquette:
"The changes to the common clock framework for 4.0 are mostly new clock
drivers and updates to existing ones for feature enhancements and bug
fixes.
There is more churn than usual in the framework core due to the change
to introduce per-user unique struct clk pointers in 4.0. This caused
several regressions to surface, some of which were sent as fixes to
4.0. New generic clock drivers were added for GPIO- and PWM-based
clock controllers.
Additionally the common clk-divider code recieved several fixes to the
way it rounds rates"
* tag 'clk-for-linus-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (91 commits)
clk: check ->determine/round_rate() return value in clk_calc_new_rates
clk: at91: usb: propagate rate modification to the parent clk
clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC
clk: don't use __initconst for non-const arrays
clk: at91: change to using endian agnositc IO
clk: clk-gpio-gate: Fix active low
clk: Add PWM clock driver
clk: Add clock driver for mb86s7x
clk: pxa: pxa3xx: add missing os timer clock
clk: tegra: Use the proper parent for plld_dsi
clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
clk: tegra: Model oscillator as clock
clk: tegra: Add peripheral registers for bank Y
clk: tegra: Register the proper number of resets
clk: tegra: Remove needless initializations
clk: tegra: Use consistent indentation
clk: tegra: Various whitespace cleanups
clk: tegra: Enable HDA to HDMI clocks on Tegra124
clk: tegra: Fix a bunch of sparse warnings
clk: tegra: Fix typo tabel -> table
...
devicetree changes queued up for v4.1. Here are the highlights:
- Lots of unittest cleanup from Frank Rowand
- Bugfixes and updates to the of_graph code
- Tighten up of_get_mac_address() code
- Documentation updates
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Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux
Pull devicetree changes from Grant Likely:
"Here are the devicetree changes queued up for v4.1. Nothing really
exciting here. Rob has another few commits for big-endian attached
UARTs, but those will be sent in a separate merge request since they
haven't been as thoroughly tested as this batch.
Here are the highlights:
- lots of unittest cleanup from Frank Rowand
- bugfixes and updates to the of_graph code
- tighten up of_get_mac_address() code
- documentation updates"
* tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux:
of/unittest: Fix of_platform_depopulate test case
of/unittest: early return from test skips tests
of/unittest: breadcrumbs to reduce pain of future maintainers
of/unittest: reduce checkpatch noise - line after declarations
of/unittest: typo in error string
of/unittest: add const where needed
of_net: factor out repetitive code from of_get_mac_address()
drivers/of: Add empty ranges quirk for PA-Semi
of: Allow selection of OF_DYNAMIC and OF_OVERLAY if OF_UNITTEST
of: Empty node & property flag accessors when !OF
of: Explicitly include linux/types.h in of_graph.h
dt-bindings: brcm: rationalize Broadcom documentation naming
of/unittest: replace 'selftest' with 'unittest'
Documentation: rename of_selftest.txt to of_unittest.txt
Documentation: update the of_selftest.txt
dt: OF_UNITTEST make dependency broken
MAINTAINERS: Pantelis Antoniou device tree overlay maintainer
of: Add of_graph_get_port_by_id function
of: Add for_each_endpoint_of_node helper macro
of: Decrement refcount of previous endpoint in of_graph_get_next_endpoint
Some board designers, when running out of clock output pads, decide to
(mis)use PWM output pads to provide a clock to external components.
This driver supports this practice by providing an adapter between the
PWM and clock bindings in the device tree. As the PWM bindings specify
the period in the device tree, this is a fixed clock.
Tested-by: Janusz Uzycki <j.uzycki@elproma.com.pl>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Add clock controller for CMU ISP clock domain on Exynos3250,
providing clocks for FIMC-IS subsystem.
[b.michalska: use samsung_cmu_register_one to register
the provider; updated DT binding documentation]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Beata Michalska <b.michalska@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
[s.nawrocki: added __init attribute which was missing in function
exynos3250_cmu_platform_init() in function, which has been]
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This patchset attempts to standardize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the dt-bindings document the "vendor,binding.txt" style is in use by
some of the other vendors.
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The usual round of clock changes for the Allwinner SoCs.
There is nothing really standing out here, but a few changes and fixes, most
notably to allow the AHB clock to be parented to a PLL, instead of the CPU
clock to avoid any AHB rate change due to cpufreq.
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Merge tag 'sunxi-clocks-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clocks changes for 4.1
The usual round of clock changes for the Allwinner SoCs.
There is nothing really standing out here, but a few changes and fixes, most
notably to allow the AHB clock to be parented to a PLL, instead of the CPU
clock to avoid any AHB rate change due to cpufreq.
Add clocks/resets defines for the global clock controller
found on Qualcomm MSM8916 SoCs.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The AHB clock on sun5i and sun7i are muxable divider clocks.
Use a factors clock to support them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Driver for the r8a7778's clocks that depend on the mode bits.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.
Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
