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SoCFPGA dts updates for v5.18, part 1

Browse Source 
- Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings
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Merge tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA dts updates for v5.18, part 1
- Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings

* tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (22 commits)
  ARM: dts: socfpga: cyclone5: align regulator node with dtschema
  ARM: dts: socfpga: arria10: align regulator node with dtschema
  arm64: dts: agilex: align pl330 node name with dtschema
  arm64: dts: stratix10: align pl330 node name with dtschema
  arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema
  arm64: dts: agilex: align mmc node names with dtschema
  arm64: dts: agilex: add board compatible for N5X DK
  arm64: dts: agilex: add board compatible for SoCFPGA DK
  arm64: dts: stratix10: align regulator node names with dtschema
  arm64: dts: stratix10: align mmc node names with dtschema
  arm64: dts: stratix10: move ARM timer out of SoC node
  arm64: dts: stratix10: add board compatible for SoCFPGA DK
  ARM: dts: arria10: add board compatible for SoCFPGA DK
  ARM: dts: arria10: add board compatible for Mercury AA1
  ARM: dts: arria5: add board compatible for SoCFPGA DK
  dt-bindings: clock: intel,stratix10: convert to dtschema
  dt-bindings: intel: document Agilex based board compatibles
  dt-bindings: altera: document Stratix 10 based board compatibles
  dt-bindings: altera: document VT compatibles
  dt-bindings: altera: document Arria 10 based board compatibles
  ...

Link: https://lore.kernel.org/r/20220211112556.98940-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-02-25 15:19:06 +01:00
commit ab2dad6f9e
19 changed files with 134 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
Documentation/devicetree/bindings/arm/altera.yaml
View File

@ -13,12 +13,46 @@ properties:
$nodename:
const: "/"
compatible:
items:
- enum:
- altr,socfpga-cyclone5
- altr,socfpga-arria5
- altr,socfpga-arria10
- const: altr,socfpga
oneOf:
- description: Arria 5 boards
items:
- enum:
- altr,socfpga-arria5-socdk
- const: altr,socfpga-arria5
- const: altr,socfpga
- description: Arria 10 boards
items:
- enum:
- altr,socfpga-arria10-socdk
- enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Cyclone 5 boards
items:
- enum:
- altr,socfpga-cyclone5-socdk
- denx,mcvevk
- ebv,socrates
- macnica,sodia
- novtech,chameleon96
- samtec,vining
- terasic,de0-atlas
- terasic,socfpga-cyclone5-sockit
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Stratix 10 boards
items:
- enum:
- altr,socfpga-stratix10-socdk
- const: altr,socfpga-stratix10
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt
- const: altr,socfpga
additionalProperties: true

26
Documentation/devicetree/bindings/arm/intel,socfpga.yaml Normal file
View File

@ -0,0 +1,26 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA platform device tree bindings
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: AgileX boards
items:
- enum:
- intel,n5x-socdk
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
additionalProperties: true
...

20
Documentation/devicetree/bindings/clock/intc_stratix10.txt
View File

@ -1,20 +0,0 @@
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be
"intel,stratix10-clkmgr"
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- #clock-cells : from common clock binding, shall be set to 1.
Example:
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

35
Documentation/devicetree/bindings/clock/intel,stratix10.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Stratix10 platform clock controller binding
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
compatible:
const: intel,stratix10-clkmgr
'#clock-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

2
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
View File

@ -6,7 +6,7 @@
/ {
model = "Enclustra Mercury AA1";
compatible = "altr,socfpga-arria10", "altr,socfpga";
compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
aliases {
ethernet0 = &gmac0;

2
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
View File

@ -6,7 +6,7 @@
/ {
model = "Altera SOCFPGA Arria 10";
compatible = "altr,socfpga-arria10", "altr,socfpga";
compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
aliases {
ethernet0 = &gmac0;

4
arch/arm/boot/dts/socfpga_arria5_socdk.dts
View File

@ -7,7 +7,7 @@
/ {
model = "Altera SOCFPGA Arria V SoC Development Kit";
compatible = "altr,socfpga-arria5", "altr,socfpga";
compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
@ -50,7 +50,7 @@ hps3 {
};
};
regulator_3_3v: 3-3-v-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts
View File

@ -24,7 +24,7 @@ memory@0 {
reg = <0x0 0x20000000>; /* 512MB */
};
regulator_3_3v: 3-3-v-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
View File

@ -24,7 +24,7 @@ aliases {
ethernet0 = &gmac1;
};
regulator_3_3v: 3-3-v-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
View File

@ -50,7 +50,7 @@ hps3 {
};
};
regulator_3_3v: 3-3-v-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
View File

@ -111,7 +111,7 @@ hps_hkey3 {
};
};
regulator_3_3v: vcc3p3-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "VCC3P3";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
View File

@ -26,7 +26,7 @@ aliases {
ethernet0 = &gmac1;
};
regulator_3_3v: 3-3-v-regulator {
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;

23
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -77,6 +77,16 @@ psci {
method = "smc";
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
interrupt-parent = <&intc>;
};
intc: interrupt-controller@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@ -286,7 +296,7 @@ i2c4: i2c@ffc02c00 {
status = "disabled";
};
mmc: dwmmc0@ff808000 {
mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
@ -323,7 +333,7 @@ ocram: sram@ffe00000 {
reg = <0xffe00000 0x100000>;
};
pdma: pdma@ffda0000 {
pdma: dma-controller@ffda0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda0000 0x1000>;
interrupts = <0 81 4>,
@ -406,15 +416,6 @@ sysmgr: sysmgr@ffd12000 {
reg = <0xffd12000 0x228>;
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;

3
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@ -7,6 +7,7 @@
/ {
model = "SoCFPGA Stratix 10 SoCDK";
compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
aliases {
serial0 = &uart0;
@ -43,7 +44,7 @@ memory {
reg = <0 0 0 0>;
};
ref_033v: 033-v-ref {
ref_033v: regulator-v-ref {
compatible = "regulator-fixed";
regulator-name = "0.33V";
regulator-min-microvolt = <330000>;

3
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
View File

@ -7,6 +7,7 @@
/ {
model = "SoCFPGA Stratix 10 SoCDK";
compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
aliases {
serial0 = &uart0;
@ -43,7 +44,7 @@ memory {
reg = <0 0 0 0>;
};
ref_033v: 033-v-ref {
ref_033v: regulator-v-ref {
compatible = "regulator-fixed";
regulator-name = "0.33V";
regulator-min-microvolt = <330000>;

4
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -300,7 +300,7 @@ i2c4: i2c@ffc02c00 {
status = "disabled";
};
mmc: dwmmc0@ff808000 {
mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
@ -337,7 +337,7 @@ ocram: sram@ffe00000 {
reg = <0xffe00000 0x40000>;
};
pdma: pdma@ffda0000 {
pdma: dma-controller@ffda0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda0000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,

7
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View File

@ -6,6 +6,7 @@
/ {
model = "SoCFPGA Agilex SoCDK";
compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
aliases {
serial0 = &uart0;
@ -20,17 +21,17 @@ chosen {
leds {
compatible = "gpio-leds";
hps0 {
led0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
hps1 {
led1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
hps2 {
led2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};

1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
View File

@ -6,6 +6,7 @@
/ {
model = "SoCFPGA Agilex SoCDK";
compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
aliases {
serial0 = &uart0;

1
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
View File

@ -6,6 +6,7 @@
/ {
model = "eASIC N5X SoCDK";
compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
aliases {
serial0 = &uart0;