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ARM: 9482/5: decompressor: always set endianess on xscale

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In BE32 configurations, endianess is always set to BE in Control
Register C1, originally to allow booting BE kernels from a LE bootloader
on IXP12xx.

To also allow the opposite and allow booting LE kernels from a BE
IXP4xx bootloader, moving this code into head-xscale.S along with the
recommended serialization sequence and flip the B bit into the correct
position regardless of its original state.

Note that both the endianess switch sequence and the cp15wait I add
here should be harmless on all supported ARMv4/v4t/v5 CPUs, but the
existing cache flush code is not actually defined on ARM720 and may
cause problems in multiplatform kernels that include both Xscale
and CLPS711x.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Linus Walleij 2026-09-10 21:05:39 +01:00 committed by Russell King
parent cee9395acd
commit f8ebc827f2
3 changed files with 18 additions and 22 deletions
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8
arch/arm/boot/compressed/Makefile
View File

@ -41,14 +41,6 @@ ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y)
OBJS += head-sharpsl.o
endif
ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
ifeq ($(CONFIG_CPU_CP15),y)
OBJS += big-endian.o
else
# The endian should be set by h/w design.
endif
endif
#
# We now have a PIC decompressor implementation. Decompressors running
# from RAM should not define ZTEXTADDR. Decompressors running directly

14
arch/arm/boot/compressed/big-endian.S
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/boot/compressed/big-endian.S
*
* Switch CPU into big endian mode.
* Author: Nicolas Pitre
*/
.section ".start", "ax"
mrc p15, 0, r0, c1, c0, 0 @ read control reg
orr r0, r0, #(1 << 7) @ enable big endian mode
mcr p15, 0, r0, c1, c0, 0 @ write control reg

18
arch/arm/boot/compressed/head-xscale.S
View File

@ -7,6 +7,7 @@
*/
#include <linux/linkage.h>
#include <asm/cp15.h>
.section ".start", "ax"
@ -14,6 +15,23 @@ __XScale_start:
@ Preserve r8/r7 i.e. kernel entry values
@ set correct endianness for ixp4xx regardless of bootloader
mrc p15, 0, r0, c1, c0, 0
#ifdef CONFIG_CPU_BIG_ENDIAN
orr r0, r0, #CR_B @ enable big endian mode
#else
bic r0, r0, #CR_B
#endif
mcr p15, 0, r0, c1, c0, 0
0: mrc p15, 0, r0, c1, c0, 0
tst r0, #0x80
#ifdef CONFIG_CPU_BIG_ENDIAN
beq 0b
#else
bne 0b
#endif
sub pc, pc, #4 @ flush instruction pipeline
@ Data cache might be active.
@ Be sure to flush kernel binary out of the cache,
@ whatever state it is, before it is turned off.