From f8ebc827f2b0aed23295886543c0823c908dcee1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 10 Sep 2026 21:05:39 +0100 Subject: [PATCH] ARM: 9482/5: decompressor: always set endianess on xscale In BE32 configurations, endianess is always set to BE in Control Register C1, originally to allow booting BE kernels from a LE bootloader on IXP12xx. To also allow the opposite and allow booting LE kernels from a BE IXP4xx bootloader, moving this code into head-xscale.S along with the recommended serialization sequence and flip the B bit into the correct position regardless of its original state. Note that both the endianess switch sequence and the cp15wait I add here should be harmless on all supported ARMv4/v4t/v5 CPUs, but the existing cache flush code is not actually defined on ARM720 and may cause problems in multiplatform kernels that include both Xscale and CLPS711x. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/compressed/Makefile | 8 -------- arch/arm/boot/compressed/big-endian.S | 14 -------------- arch/arm/boot/compressed/head-xscale.S | 18 ++++++++++++++++++ 3 files changed, 18 insertions(+), 22 deletions(-) delete mode 100644 arch/arm/boot/compressed/big-endian.S diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e3f550d62857..5993dd1d0ee9 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -41,14 +41,6 @@ ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y) OBJS += head-sharpsl.o endif -ifeq ($(CONFIG_CPU_ENDIAN_BE32),y) -ifeq ($(CONFIG_CPU_CP15),y) -OBJS += big-endian.o -else -# The endian should be set by h/w design. -endif -endif - # # We now have a PIC decompressor implementation. Decompressors running # from RAM should not define ZTEXTADDR. Decompressors running directly diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S deleted file mode 100644 index 0e092c36da2f..000000000000 --- a/arch/arm/boot/compressed/big-endian.S +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/arm/boot/compressed/big-endian.S - * - * Switch CPU into big endian mode. - * Author: Nicolas Pitre - */ - - .section ".start", "ax" - - mrc p15, 0, r0, c1, c0, 0 @ read control reg - orr r0, r0, #(1 << 7) @ enable big endian mode - mcr p15, 0, r0, c1, c0, 0 @ write control reg - diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 20fa44d59f82..d6c3d0a76550 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -7,6 +7,7 @@ */ #include +#include .section ".start", "ax" @@ -14,6 +15,23 @@ __XScale_start: @ Preserve r8/r7 i.e. kernel entry values + @ set correct endianness for ixp4xx regardless of bootloader + mrc p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_CPU_BIG_ENDIAN + orr r0, r0, #CR_B @ enable big endian mode +#else + bic r0, r0, #CR_B +#endif + mcr p15, 0, r0, c1, c0, 0 +0: mrc p15, 0, r0, c1, c0, 0 + tst r0, #0x80 +#ifdef CONFIG_CPU_BIG_ENDIAN + beq 0b +#else + bne 0b +#endif + sub pc, pc, #4 @ flush instruction pipeline + @ Data cache might be active. @ Be sure to flush kernel binary out of the cache, @ whatever state it is, before it is turned off.