diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e3f550d62857..5993dd1d0ee9 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -41,14 +41,6 @@ ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y) OBJS += head-sharpsl.o endif -ifeq ($(CONFIG_CPU_ENDIAN_BE32),y) -ifeq ($(CONFIG_CPU_CP15),y) -OBJS += big-endian.o -else -# The endian should be set by h/w design. -endif -endif - # # We now have a PIC decompressor implementation. Decompressors running # from RAM should not define ZTEXTADDR. Decompressors running directly diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S deleted file mode 100644 index 0e092c36da2f..000000000000 --- a/arch/arm/boot/compressed/big-endian.S +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/arm/boot/compressed/big-endian.S - * - * Switch CPU into big endian mode. - * Author: Nicolas Pitre - */ - - .section ".start", "ax" - - mrc p15, 0, r0, c1, c0, 0 @ read control reg - orr r0, r0, #(1 << 7) @ enable big endian mode - mcr p15, 0, r0, c1, c0, 0 @ write control reg - diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 20fa44d59f82..d6c3d0a76550 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -7,6 +7,7 @@ */ #include +#include .section ".start", "ax" @@ -14,6 +15,23 @@ __XScale_start: @ Preserve r8/r7 i.e. kernel entry values + @ set correct endianness for ixp4xx regardless of bootloader + mrc p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_CPU_BIG_ENDIAN + orr r0, r0, #CR_B @ enable big endian mode +#else + bic r0, r0, #CR_B +#endif + mcr p15, 0, r0, c1, c0, 0 +0: mrc p15, 0, r0, c1, c0, 0 + tst r0, #0x80 +#ifdef CONFIG_CPU_BIG_ENDIAN + beq 0b +#else + bne 0b +#endif + sub pc, pc, #4 @ flush instruction pipeline + @ Data cache might be active. @ Be sure to flush kernel binary out of the cache, @ whatever state it is, before it is turned off.