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ARM: dts: zte: zx297520v3 device tree for 7.2
This pull request adds board bindings and DTS files for ZTE zx297520v3 boards as well as one initial device (D-Link DWR 932M) based on this board. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEQxb0tqoFWyeVMl1sPRO8yFRPGiIFAmoE5xIbFIAAAAAABAAO bWFudTIsMi41KzEuMTIsMiwyAAoJED0TvMhUTxoidE4P/1mFb3l21g0lYAGxCZPC 27k4XgZ+j+wH/x210XI/5ghgU0YLcNuXd/ydDk3GhRFdPZR7HDGiGpGjwF/RVgAQ 5zubGhQDOr7qZyBIzgDUXvYYXyF7NymEFgPCbRxCspeTF0+GNS6eKxYo8vhHgque 74m+F+BcBFmxs8hRu+pkC/jrmihD/PfmyLa/w9PK5kysNhByt5CLnvwhEqAQ/sHV JY5M1mwvvQuvRMZsrYVojx9dGbaE7NnoXkIJr1gr8OngnVSHN8eTtlbXMuYVXX6a U3eUbUJnpB2R4hJy+rZNmReAyYO/HQLh9BMYr0maXjZAAYCzBmL7xDLgFeua8zse qWfrGFK1eraVSyfhsHbUSbBkYrEkwadRMzFV+QheRaNucU5/DK0G+RoiOeE4f/uB xUMYY+FCqEyjf5wLatmQ4i/ogqX13etSHUZwzPz24Ny/bPuKwiNFj2+qlHiDYGwJ tOuei/Ib4DJXKpRYVmTVv/xH4oIGLQLNeYV9d49cqVu5GqqCHU/4uXCS0El/WIfV ihxoy+gSyLdLY7QghlicZM3R+5mLLh0FsBI6lQJU/I0lzJJOEFe+KLCk3hFl5F71 GzL8tkxB9VBkqJRJ2MRmjOTejpGaI6agHH0gVUkB+7B2CnA/e0nTyDLnDTcvtWS6 lfrEleo+RT9YS9gGOLOOxSo7 =leHo -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmoOCWEACgkQmmx57+YA GNkkzw/7B+GQBxkkwp8Y9AXLMRsHw0XbHTNuzGsqrbG98mNqXV7V/PqajNwV1QGp 7uzV+rYjI5bP0hMRKUaLuQ4y1iKkxaJUaiRmWmDGVOxBYwvqLH/J++H2Al5Xd7Br HiAvZaLsGQcE7D0qUFnqs3HnhdkiD5o+tO43tnxx9MDkupY0IKtEvOuWZhBcNNVC i+qkDploaGMkWrGiRopFdJlHlQil/Yn2TrDUMtHDP3zT4QAqpdS85ogd2b/YvP3D BLOnbwsKSTbd1iU7OUvvxKTgNH4S7N1TDvg8Ei40EU122dw3gDajM97r9e1uxmdC u/x0NnwAmDQ3bUAfaoTSzOPx8CJOVrPG2+ef7cHnfSIUBD1l+hpymr37USfi0ioL Jz5AKivDpaIHKQLzlqYJhjhs0TJSphtaDEpxbNzksVnqfxq7MX4d2lakjBF86846 oo1ITGpdkhV/IDtFi7Z5hklk7D4UY+UiDFdBJuoR/sIUVtysoktMkqxawoXGwNMz nEbnE8mISQZn5q1A+tX0RAcpdB3tQAMepl020SCz6BkFg/sW3lkw9V+Cov8WI7M9 sgRObKjqBmFCzivkbZhMXILXJErY0re68VA48LE241BD+YpcpOweOFiMabduRmvs AwyAwyJ1/UK64d1CH8v7T+HsmuUJA5mHGpuAuYPMks99QjhP0no= =A0MX -----END PGP SIGNATURE----- Merge tag 'zx29-dts-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel into soc/dt ARM: dts: zte: zx297520v3 device tree for 7.2 This pull request adds board bindings and DTS files for ZTE zx297520v3 boards as well as one initial device (D-Link DWR 932M) based on this board. * tag 'zx29-dts-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel: ARM: dts: zte: Add D-Link DWR-932M support dt-bindings: arm: zte: Add D-Link DWR932M board based on zx297520v3 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
e8a53f2d9c
26
Documentation/devicetree/bindings/arm/zte.yaml
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26
Documentation/devicetree/bindings/arm/zte.yaml
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@ -0,0 +1,26 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/zte.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ZTE zx platforms
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maintainers:
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- Stefan Dösinger <stefandoesinger@gmail.com>
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description: |
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ARM platforms using SoCs designed by ZTE. Currently this supports devices
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based on the zx297520v3 SoC which is found in LTE routers.
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properties:
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$nodename:
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const: "/"
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compatible:
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oneOf:
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- items:
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- enum:
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- dlink,dwr932m
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- const: zte,zx297520v3
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additionalProperties: true
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@ -39,3 +39,4 @@ subdir-y += unisoc
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subdir-y += vt8500
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subdir-y += xen
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subdir-y += xilinx
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subdir-y += zte
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3
arch/arm/boot/dts/zte/Makefile
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arch/arm/boot/dts/zte/Makefile
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_SOC_ZX297520V3) += \
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zx297520v3-dlink-dwr932m.dtb
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22
arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts
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22
arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
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*/
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/dts-v1/;
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#include "zx297520v3.dtsi"
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/ {
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model = "D-Link DWR-932M";
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compatible = "dlink,dwr932m", "zte,zx297520v3";
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x04000000>;
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};
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};
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&uart1 {
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status = "okay";
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};
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103
arch/arm/boot/dts/zte/zx297520v3.dtsi
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arch/arm/boot/dts/zte/zx297520v3.dtsi
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@ -0,0 +1,103 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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};
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/* Base bus clock and default for the UART. It will be replaced once a clock driver has
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* been added.
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*/
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uartclk: uartclk-26000000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <26000000>;
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interrupt-parent = <&gic>;
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/* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
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* arm timer at all. Since this is a single CPU system I don't think it
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* really matters that the offset is random though.
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*/
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arm,cpu-registers-not-fw-configured;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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/* The GIC has a non-standard way of configuring ints between level-low/level
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* high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE
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* and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source
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* seem wrong.
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*
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* Everything defaults to active-high/rising edge, but the timer is active-low. We
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* currently rely on the boot loader to change timer IRQs to active-low for us for
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* now.
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*/
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gic: interrupt-controller@f2000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf2000000 0x10000>,
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<0xf2040000 0x20000>;
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};
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uart0: serial@131000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x00131000 0x1000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@1408000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x01408000 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@140d000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x0140d000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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