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Renesas DTS updates for v7.2

Browse Source 
- Add GPU support for R-Car M3-W(+)-based ULCB and Salvator-X(S)
     development boards,
   - Add Ethernet, OPP table, interrupt, pin control, and watchdog
     support for the RZ/G3L SoC and the RZ/G3L SMARC SoM board,
   - Add Coresight support for the R-Mobile A1 and APE6 SoCs, and the
     Armadillo-800 EVA and APE6EVM development boards,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.2

  - Add GPU support for R-Car M3-W(+)-based ULCB and Salvator-X(S)
    development boards,
  - Add Ethernet, OPP table, interrupt, pin control, and watchdog
    support for the RZ/G3L SoC and the RZ/G3L SMARC SoM board,
  - Add Coresight support for the R-Mobile A1 and APE6 SoCs, and the
    Armadillo-800 EVA and APE6EVM development boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (40 commits)
  ARM: dts: renesas: r8a73a4: Describe coresight on R-Mobile APE6
  ARM: dts: renesas: r8a73a4: Add ZT/ZTR trace clock on R-Mobile APE6
  dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
  arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog
  arm64: dts: renesas: r9a08g046: Add wdt device node
  arm64: dts: renesas: salvator-common: Sort sound node
  arm64: dts: renesas: ebisu: Sort sound node
  arm64: dts: renesas: gray-hawk-single: Fix AVB0 PHY node alignment
  arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface
  arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0
  arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol
  arm64: dts: renesas: r9a08g046: Add pincontrol node
  arm64: dts: renesas: r9a08g046: Add ICU node
  arm64: dts: renesas: r9a08g046: Add OPP table
  arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs
  ARM: dts: renesas: r8a7740: Describe coresight
  ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clocks
  arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH0) interface
  arm64: dts: renesas: r9a08g046: Add GBETH nodes
  arm64: dts: renesas: r8a77961-salvator-xs: Enable GPU support
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-05-20 12:12:33 +02:00
commit ae6bbc1ef5
36 changed files with 945 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
View File

@ -41,7 +41,7 @@ properties:
clock-output-names:
minItems: 3
maxItems: 17
maxItems: 19
renesas,mode:
description: Board-specific settings of the MD_CK* bits on R-Mobile A1
@ -90,6 +90,8 @@ allOf:
- const: zx
- const: zs
- const: hp
- const: ztr
- const: zt
- if:
properties:
@ -123,6 +125,8 @@ allOf:
- const: zb
- const: m3
- const: cp
- const: ztr
- const: zt
required:
- renesas,mode
@ -240,6 +244,6 @@ examples:
#clock-cells = <1>;
clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
"usbp", "s", "zb", "m3", "cp";
"usbp", "s", "zb", "m3", "cp", "ztr", "zt";
renesas,mode = <0x05>;
};

35
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
- renesas,r9a08g046-pinctrl # RZ/G3L
- renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g056-pinctrl # RZ/V2N
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
@ -78,6 +79,26 @@ properties:
- description: PFC main reset
- description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
reset-names:
oneOf:
- items:
- const: rstn
- const: port
- const: spare
- items:
- const: main
- const: error
renesas,clonech:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to system controller
- description: offset of clone channel control register
description:
Phandle and offset to the system controller containing the clone channel
control values.
additionalProperties:
anyOf:
- type: object
@ -140,6 +161,15 @@ additionalProperties:
allOf:
- $ref: pinctrl.yaml#
- if:
properties:
compatible:
contains:
const: renesas,r9a08g046-pinctrl
then:
required:
- renesas,clonech
- if:
properties:
compatible:
@ -152,10 +182,14 @@ allOf:
properties:
resets:
maxItems: 2
reset-names:
maxItems: 2
else:
properties:
resets:
minItems: 3
reset-names:
minItems: 3
required:
- compatible
@ -187,6 +221,7 @@ examples:
resets = <&cpg R9A07G044_GPIO_RSTN>,
<&cpg R9A07G044_GPIO_PORT_RESETN>,
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
power-domains = <&cpg>;
scif0_pins: serial0 {

3
arch/arm/boot/dts/renesas/r7s72100-genmai.dts
View File

@ -34,9 +34,6 @@ flash@18000000 {
clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

2
arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
View File

@ -36,8 +36,6 @@ flash@18000000 {
power-domains = <&cpg_clocks>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";

2
arch/arm/boot/dts/renesas/r7s72100.dtsi
View File

@ -37,7 +37,7 @@ b_clk: b {
clock-div = <3>;
};
bsc: bus {
bsc: bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

114
arch/arm/boot/dts/renesas/r8a73a4.dtsi
View File

@ -47,9 +47,117 @@ L2_CA7: cache-controller-1 {
};
};
ptm {
compatible = "arm,coresight-etm3x";
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&cpg_clocks R8A73A4_CLK_ZTR>;
clock-names = "atclk";
power-domains = <&pd_d4>;
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
};
in-ports {
/* replicator input port */
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port>;
};
};
};
};
etb@e6f81000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe6f81000 0 0x1000>;
clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
power-domains = <&pd_d4>;
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
tpiu@e6f83000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0xe6f83000 0 0x1000>;
clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
power-domains = <&pd_d4>;
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
funnel {
compatible = "arm,coresight-static-funnel";
/* funnel output ports */
out-ports {
port {
funnel_out_port: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
funnel0_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
};
};
ptm@e6fbc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe6fbc000 0 0x1000>;
clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
cpu = <&cpu0>;
power-domains = <&pd_d4>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
timer {
@ -512,7 +620,7 @@ cpg_clocks: cpg_clocks@e6150000 {
clock-output-names = "main", "pll0", "pll1", "pll2",
"pll2s", "pll2h", "z", "z2",
"i", "m3", "b", "m1", "m2",
"zx", "zs", "hp";
"zx", "zs", "hp", "ztr", "zt";
};
/* Variable factor clocks (DIV6) */

116
arch/arm/boot/dts/renesas/r8a7740.dtsi
View File

@ -18,7 +18,7 @@ / {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
@ -59,9 +59,117 @@ pmu {
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
};
ptm {
compatible = "arm,coresight-etm3x";
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&cpg_clocks R8A7740_CLK_ZTR>;
clock-names = "atclk";
power-domains = <&pd_d4>;
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
};
in-ports {
/* replicator input port */
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port>;
};
};
};
};
etb@e6fa1000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0xe6fa1000 0x1000>;
clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
power-domains = <&pd_d4>;
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
tpiu@e6fa3000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xe6fa3000 0x1000>;
clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
power-domains = <&pd_d4>;
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
funnel {
compatible = "arm,coresight-static-funnel";
/* funnel output ports */
out-ports {
port {
funnel_out_port: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
funnel0_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
};
};
ptm@e6fbc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xe6fbc000 0x1000>;
clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>;
clock-names = "apb_pclk", "atclk";
cpu = <&cpu0>;
power-domains = <&pd_d4>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ceu0: ceu@fe910000 {
@ -553,7 +661,7 @@ cpg_clocks: cpg_clocks@e6150000 {
"usb24s",
"i", "zg", "b", "m1", "hp",
"hpp", "usbp", "s", "zb", "m3",
"cp";
"cp", "ztr", "zt";
};
/* Variable factor clocks (DIV6) */

2
arch/arm/boot/dts/renesas/r8a7778.dtsi
View File

@ -40,7 +40,7 @@ aliases {
spi2 = &hspi2;
};
lbsc: bus {
lbsc: bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/renesas/r8a7779.dtsi
View File

@ -704,7 +704,7 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
};
};
lbsc: bus {
lbsc: bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/renesas/r8a7792.dtsi
View File

@ -86,7 +86,7 @@ extal_clk: extal {
bootph-all;
};
lbsc: bus {
lbsc: bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

5
arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso
View File

@ -27,7 +27,12 @@ &lvds1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds1_out: endpoint {
remote-endpoint = <&panel_in>;
};

34
arch/arm64/boot/dts/renesas/ebisu.dtsi
View File

@ -186,23 +186,6 @@ reg_12p0v: regulator-12p0v {
regulator-always-on;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
@ -260,6 +243,23 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
states = <3300000 1>, <1800000 0>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vga {
compatible = "vga-connector";

10
arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi
View File

@ -208,11 +208,11 @@ mdio {
avb0_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
};
};
};

4
arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts
View File

@ -35,3 +35,7 @@ &du {
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts
View File

@ -35,3 +35,7 @@ &du {
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts
View File

@ -36,3 +36,7 @@ &du {
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
View File

@ -40,3 +40,7 @@ &du {
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts
View File

@ -40,3 +40,7 @@ &du {
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&gpu {
status = "okay";
};

8
arch/arm64/boot/dts/renesas/r8a78000.dtsi
View File

@ -699,7 +699,7 @@ scif0: serial@c0700000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0700000 0 0x40>;
interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@ -709,7 +709,7 @@ scif1: serial@c0704000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0704000 0 0x40>;
interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@ -719,7 +719,7 @@ scif3: serial@c0708000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0708000 0 0x40>;
interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};
@ -729,7 +729,7 @@ scif4: serial@c070c000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc070c000 0 0x40>;
interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
};

1
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@ -604,6 +604,7 @@ pinctrl: pinctrl@11030000 {
resets = <&cpg R9A07G043_GPIO_RSTN>,
<&cpg R9A07G043_GPIO_PORT_RESETN>,
<&cpg R9A07G043_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
};
dmac: dma-controller@11820000 {

1
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -1017,6 +1017,7 @@ pinctrl: pinctrl@11030000 {
resets = <&cpg R9A07G044_GPIO_RSTN>,
<&cpg R9A07G044_GPIO_PORT_RESETN>,
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
};
irqc: interrupt-controller@110a0000 {

1
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -1025,6 +1025,7 @@ pinctrl: pinctrl@11030000 {
resets = <&cpg R9A07G054_GPIO_RSTN>,
<&cpg R9A07G054_GPIO_PORT_RESETN>,
<&cpg R9A07G054_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
};
irqc: interrupt-controller@110a0000 {

1
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@ -533,6 +533,7 @@ pinctrl: pinctrl@11030000 {
resets = <&cpg R9A08G045_GPIO_RSTN>,
<&cpg R9A08G045_GPIO_PORT_RESETN>,
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
};
irqc: interrupt-controller@11050000 {

402
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
View File

@ -14,6 +14,42 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-37500000 {
opp-hz = /bits/ 64 <37500000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -24,6 +60,8 @@ cpu0: cpu@0 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@ -32,6 +70,8 @@ cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
@ -40,6 +80,8 @@ cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
@ -48,6 +90,8 @@ cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
@ -160,10 +204,111 @@ sysc: system-controller@11020000 {
};
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a08g046-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
/* placeholder */
gpio-ranges = <&pinctrl 0 0 232>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&icu>;
clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A08G046_GPIO_RSTN>,
<&cpg R9A08G046_GPIO_PORT_RESETN>,
<&cpg R9A08G046_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
renesas,clonech = <&sysc 0xe2c>;
};
icu: interrupt-controller@11050000 {
compatible = "renesas,r9a08g046-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x11050000 0 0x10000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"irq8", "irq9", "irq10", "irq11",
"irq12", "irq13", "irq14", "irq15",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0",
"ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3",
"ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7";
clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>,
<&cpg CPG_MOD R9A08G046_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_IA55_RESETN>;
};
sdhi1: mmc@11c10000 {
@ -171,6 +316,240 @@ sdhi1: mmc@11c10000 {
/* placeholder */
};
eth0: ethernet@11c30000 {
compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 88 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3", "ptp-pps-0",
"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180",
"rmii", "rmii_tx", "rmii_rx";
resets = <&cpg R9A08G046_ETH0_ARESET_N>;
power-domains = <&cpg>;
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup0>;
snps,mtl-tx-config = <&mtl_tx_setup0>;
snps,txpbl = <32>;
snps,rxpbl = <32>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup0: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
};
mtl_tx_setup0: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,weight = <0x14>;
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,weight = <0x18>;
snps,dcb-algorithm;
snps,priority = <0x8>;
};
};
};
eth1: ethernet@11c40000 {
compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
reg = <0 0x11c40000 0 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3", "ptp-pps-0",
"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180",
"rmii", "rmii_tx", "rmii_rx";
resets = <&cpg R9A08G046_ETH1_ARESET_N>;
power-domains = <&cpg>;
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,txpbl = <32>;
snps,rxpbl = <32>;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,weight = <0x14>;
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,weight = <0x18>;
snps,dcb-algorithm;
snps,priority = <0x8>;
};
};
};
pcie: pcie@11e40000 {
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
@ -198,6 +577,27 @@ gic: interrupt-controller@12400000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>,
<&cpg CPG_MOD R9A08G046_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G046_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
};
stmmac_axi_setup: stmmac-axi-config {
snps,lpi_en;
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <16 8 4 0 0 0 0>;
};
timer {

13
arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
View File

@ -14,6 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
#include "r9a08g046l48.dtsi"
#include "rzg3l-smarc-som.dtsi"
#include "renesas-smarc2.dtsi"
@ -35,3 +36,15 @@ &keys {
/delete-node/ key-2;
/delete-node/ key-3;
};
&pinctrl {
scif0_pins: scif0 {
pins = "SCIF0_TXD", "SCIF0_RXD";
power-source = <1800>;
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
};

1
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -265,6 +265,7 @@ pinctrl: pinctrl@10410000 {
interrupt-parent = <&icu>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
reset-names = "main", "error";
};
cpg: clock-controller@10420000 {

2
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@ -288,6 +288,7 @@ pinctrl: pinctrl@10410000 {
gpio-ranges = <&pinctrl 0 0 96>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
reset-names = "main", "error";
};
cpg: clock-controller@10420000 {
@ -1327,6 +1328,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
#mux-state-cells = <1>;
status = "disabled";
};

3
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@ -270,6 +270,7 @@ pinctrl: pinctrl@10410000 {
interrupt-parent = <&icu>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
reset-names = "main", "error";
};
cpg: clock-controller@10420000 {
@ -1345,6 +1346,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
#mux-state-cells = <1>;
status = "disabled";
};
@ -1355,6 +1357,7 @@ usb21phyrst: usb21phy-reset@15840000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
#mux-state-cells = <1>;
status = "disabled";
};

5
arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi
View File

@ -46,7 +46,12 @@ &csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi2_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;

5
arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi
View File

@ -26,7 +26,12 @@ &du {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
remote-endpoint = <&adv7513_in>;
};

132
arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
View File

@ -8,6 +8,11 @@
/ {
compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
};
memory@48000000 {
device_type = "memory";
/* First 128MiB is reserved for secure area. */
@ -15,6 +20,133 @@ memory@48000000 {
};
};
&eth0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
status = "okay";
};
&eth0_rxc_rx_clk {
clock-frequency = <125000000>;
};
&eth1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
status = "okay";
};
&eth1_rxc_rx_clk {
clock-frequency = <125000000>;
};
&extal_clk {
clock-frequency = <24000000>;
};
&mdio0 {
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <1400>;
txc-skew-psec = <1400>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&mdio1 {
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <1400>;
txc-skew-psec = <1400>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&pinctrl {
eth0_pins: eth0 {
txc {
pinmux = <RZG3L_PORT_PINMUX(B, 1, 1)>; /* ETH0_TXC_REF_CLK */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
ctrl {
pinmux = <RZG3L_PORT_PINMUX(A, 0, 1)>, /* MDIO */
<RZG3L_PORT_PINMUX(A, 1, 1)>, /* MDC */
<RZG3L_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
<RZG3L_PORT_PINMUX(A, 3, 1)>, /* TX_CTL */
<RZG3L_PORT_PINMUX(B, 0, 1)>, /* RXC */
<RZG3L_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
<RZG3L_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
<RZG3L_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
<RZG3L_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
<RZG3L_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
<RZG3L_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
<RZG3L_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
<RZG3L_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
<RZG3L_PORT_PINMUX(C, 2, 15)>; /* PHY_INTR */
power-source = <1800>;
};
};
eth1_pins: eth1 {
txc {
pinmux = <RZG3L_PORT_PINMUX(E, 1, 1)>; /* ETH1_TXC_REF_CLK */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
ctrl {
pinmux = <RZG3L_PORT_PINMUX(D, 0, 1)>, /* MDIO */
<RZG3L_PORT_PINMUX(D, 1, 1)>, /* MDC */
<RZG3L_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
<RZG3L_PORT_PINMUX(D, 3, 1)>, /* TX_CTL */
<RZG3L_PORT_PINMUX(E, 0, 1)>, /* RXC */
<RZG3L_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
<RZG3L_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
<RZG3L_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
<RZG3L_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
<RZG3L_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
<RZG3L_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
<RZG3L_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
<RZG3L_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
<RZG3L_PORT_PINMUX(F, 2, 15)>; /* PHY_INTR */
power-source = <1800>;
};
};
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

26
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -211,19 +211,6 @@ reg_12v: regulator-12v {
regulator-always-on;
};
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
#ifdef SOC_HAS_HDMI1
&rsnd_port2 /* HDMI1 */
#endif
>;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
@ -281,6 +268,19 @@ vccq_sdhi3: regulator-vccq-sdhi3 {
states = <3300000 1>, <1800000 0>;
};
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
#ifdef SOC_HAS_HDMI1
&rsnd_port2 /* HDMI1 */
#endif
>;
};
vga {
compatible = "vga-connector";

5
arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso
View File

@ -27,7 +27,12 @@ &lvds0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};

2
include/dt-bindings/clock/r8a73a4-clock.h
View File

@ -23,6 +23,8 @@
#define R8A73A4_CLK_ZX 13
#define R8A73A4_CLK_ZS 14
#define R8A73A4_CLK_HP 15
#define R8A73A4_CLK_ZTR 16
#define R8A73A4_CLK_ZT 17
/* MSTP1 */
#define R8A73A4_CLK_TMU0 25

2
include/dt-bindings/clock/r8a7740-clock.h
View File

@ -24,6 +24,8 @@
#define R8A7740_CLK_ZB 14
#define R8A7740_CLK_M3 15
#define R8A7740_CLK_CP 16
#define R8A7740_CLK_ZTR 17
#define R8A7740_CLK_ZT 18
/* MSTP1 */
#define R8A7740_CLK_CEU21 28

38
include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h Normal file
View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/G3L family pinctrl bindings.
*
* Copyright (C) 2026 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */
#define RZG3L_P2 2
#define RZG3L_P3 3
#define RZG3L_P5 5
#define RZG3L_P6 6
#define RZG3L_P7 7
#define RZG3L_P8 8
#define RZG3L_PA 10
#define RZG3L_PB 11
#define RZG3L_PC 12
#define RZG3L_PD 13
#define RZG3L_PE 14
#define RZG3L_PF 15
#define RZG3L_PG 16
#define RZG3L_PH 17
#define RZG3L_PJ 19
#define RZG3L_PK 20
#define RZG3L_PL 21
#define RZG3L_PM 22
#define RZG3L_PS 28
#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f)
#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin)
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */