From 86637727c11a105499e9faa38f3422dfcf4d211d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2026 18:09:51 +0100 Subject: [PATCH 01/40] arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the documentation, the internal clock input for the BRG is SGASYNCD4_PERW_BUSĪ†. Fixes: c13a643e2c491f5b ("arm64: dts: renesas: Add R8A78000 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/459d360a8332f92b3766b30814e7e1c76169aaf7.1767719254.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 3e1c98903cea..3ec1b53d2782 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -699,7 +699,7 @@ scif0: serial@c0700000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0700000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -709,7 +709,7 @@ scif1: serial@c0704000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0704000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -719,7 +719,7 @@ scif3: serial@c0708000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0708000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -729,7 +729,7 @@ scif4: serial@c070c000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc070c000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; From d289b5f56ab7fe939dc5bfc87c856b46fe5def38 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Mar 2026 05:23:58 +0100 Subject: [PATCH 02/40] arm64: dts: renesas: draak/ebisu-panel: Fix missing cells and reg in DTO Add missing cells and reg DT property in the Draak/Ebisu panel DTO to fix the following DTC W=1 warning: arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso:30.10-34.5: Warning (unit_address_vs_reg): /fragment@2/__overlay__/ports/port@1: node has a unit name, but no reg or ranges property Signed-off-by: Marek Vasut Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326042411.215241-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso index 258f8668ca36..90767d74e21b 100644 --- a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso @@ -27,7 +27,12 @@ &lvds1 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + lvds1_out: endpoint { remote-endpoint = <&panel_in>; }; From 2016dde0685a091002851df8005757150a0e9350 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Mar 2026 05:23:59 +0100 Subject: [PATCH 03/40] arm64: dts: renesas: salvator-panel: Fix missing cells and reg in DTO Add missing cells and reg DT property in the Salvator-X panel DTO to fix the following DTC W=1 warning: arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso:30.10-34.5: Warning (unit_address_vs_reg): /fragment@2/__overlay__/ports/port@1: node has a unit name, but no reg or ranges property Signed-off-by: Marek Vasut Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326042411.215241-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso index c83a30adc6ad..7807c3f80409 100644 --- a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso @@ -27,7 +27,12 @@ &lvds0 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + lvds0_out: endpoint { remote-endpoint = <&panel_in>; }; From 25b113f187bf07f8caa3f40a96e7ec6de850767e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Mar 2026 05:24:00 +0100 Subject: [PATCH 04/40] arm64: dts: renesas: rz-smarc-cru-csi-ov5645: Fix missing cells and reg in CSI2 subnode Add missing cells and reg DT property in the CSI2 subnode to fix the following DTC W=1 warning: arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi:49.10-55.5: Warning (unit_address_vs_reg): /fragment@2/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/20260326042411.215241-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi index 4d2b0655859a..3feffa4f16a9 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -46,7 +46,12 @@ &csi2 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; From ca743e8ac2b41c295d5ee12ed231fccb52161a0b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Mar 2026 05:24:01 +0100 Subject: [PATCH 05/40] arm64: dts: renesas: rz-smarc-du-adv7513-smarc: Fix missing cells and reg in DU subnode Add missing cells and reg DT property in the DU subnode to fix the following DTC W=1 warning: arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi:29.10-33.5: Warning (unit_address_vs_reg): /fragment@1/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Marek Vasut Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326042411.215241-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi index 36707576030d..f5412578ee65 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi @@ -26,7 +26,12 @@ &du { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + du_out_rgb: endpoint { remote-endpoint = <&adv7513_in>; }; From 1ca2d1af3826a6de6fd300f9b122d10d21a64266 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:06 +0100 Subject: [PATCH 06/40] ARM: dts: renesas: r8a7778: Add missing unit address to bus node Add missing unit address to bus node to fix the following DTC W=1 warning: arch/arm/boot/dts/renesas/r8a7778.dtsi:43.12-48.4: Warning (unit_address_vs_reg): /bus: node has a reg or ranges property, but no unit name Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7778.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi index 859dd29dfce3..7db456b19795 100644 --- a/arch/arm/boot/dts/renesas/r8a7778.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7778.dtsi @@ -40,7 +40,7 @@ aliases { spi2 = &hspi2; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From fd62c046cdc8fb8b1b3e358e791317b70bbc1269 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:07 +0100 Subject: [PATCH 07/40] ARM: dts: renesas: r8a7779: Add missing unit address to bus node Add missing unit address to bus node to fix the following DTC W=1 warning: arch/arm/boot/dts/renesas/r8a7779.dtsi:707.12-712.4: Warning (unit_address_vs_reg): /bus: node has a reg or ranges property, but no unit name Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi index e437c22f452d..9e8a7e190c89 100644 --- a/arch/arm/boot/dts/renesas/r8a7779.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -704,7 +704,7 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 }; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 78c459d057e970401f59781c73e1523bc1dec51f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:08 +0100 Subject: [PATCH 08/40] ARM: dts: renesas: r8a7792: Add missing unit address to bus node Add missing unit address to bus node to fix the following DTC W=1 warning: arch/arm/boot/dts/renesas/r8a7792.dtsi:89.12-94.4: Warning (unit_address_vs_reg): /bus: node has a reg or ranges property, but no unit name Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7792.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 9e0de69ac3a3..fbdbcff1cbed 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -86,7 +86,7 @@ extal_clk: extal { bootph-all; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From c5f21e57e7582572dbb2eed4eaa041cad5694c90 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:09 +0100 Subject: [PATCH 09/40] ARM: dts: renesas: r7s72100: Add missing unit address to bus node Add missing unit address to bus node to fix the following DTC W=1 warning: arch/arm/boot/dts/renesas/r7s72100.dtsi:40.11-46.4: Warning (unit_address_vs_reg): /bus: node has a reg or ranges property, but no unit name Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r7s72100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index 245c26bb8e03..6ec57ffa72e8 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -37,7 +37,7 @@ b_clk: b { clock-div = <3>; }; - bsc: bus { + bsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 714e1d6bba0e0abe5c87c8e189a35fa690540df4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:10 +0100 Subject: [PATCH 10/40] ARM: dts: renesas: genmai: Drop superfluous cells Drop superfluous address-cells and size-cells to fix DTC W=1 warning: arch/arm/boot/dts/renesas/r7s72100-genmai.dts:28.17-55.4: Warning (avoid_unnecessary_addr_size): /flash@18000000: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" or "ranges" property Signed-off-by: Marek Vasut Fixes: 30e0a8cf886cb459 ("ARM: dts: renesas: genmai: Add FLASH nodes") Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-6-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts index 3c3756509714..da552a66615e 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -34,9 +34,6 @@ flash@18000000 { clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <1>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; From ab83176d3cf1cf1c1f6e604432905bda4515d17f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 28 Mar 2026 00:42:11 +0100 Subject: [PATCH 11/40] ARM: dts: renesas: rskrza1: Drop superfluous cells Drop superfluous address-cells and size-cells to fix DTC W=1 warning: arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts:32.17-72.4: Warning (avoid_unnecessary_addr_size): /flash@18000000: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" or "ranges" property Signed-off-by: Marek Vasut Fixes: 98537eb77d3ef185 ("ARM: dts: renesas: rskrza1: Add FLASH nodes") Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260327234244.91707-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts index 91178fb9e721..3306bc9b7bc3 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -36,8 +36,6 @@ flash@18000000 { power-domains = <&cpg_clocks>; bank-width = <4>; device-width = <1>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "fixed-partitions"; From d6cdab742c0548b5ce3309da108bbf7a1fc6f68e Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Tue, 7 Apr 2026 17:34:28 +0200 Subject: [PATCH 12/40] arm64: dts: renesas: r9a09g057: Add #mux-state-cells to usb2{0,1}phyrst The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells as a required property. Add it to the usb20phyrst and usb21phyrst nodes to fix the following warnings: arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property") Signed-off-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/22fb9a500cdbc3272dc23cd5e36bca5fbbec75fc.1775575276.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 9581af58024e..6f6fe5f36bef 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1345,6 +1345,7 @@ usb20phyrst: usb20phy-reset@15830000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; @@ -1355,6 +1356,7 @@ usb21phyrst: usb21phy-reset@15840000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; From 7e070a14beaf036588f164575bbaf7011dd26285 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Tue, 7 Apr 2026 17:34:29 +0200 Subject: [PATCH 13/40] arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells as a required property. Add it to the usb20phyrst node to fix the following warnings: arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property") Signed-off-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/31210e05f7189b466b30eedbdda3d11726dac279.1775575276.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 40525470194e..7ccddd6a4a9a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -1327,6 +1327,7 @@ usb20phyrst: usb20phy-reset@15830000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; From c9c008754abd66d48cb04a9045cc12714ce2d720 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:27 +0200 Subject: [PATCH 14/40] dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile A1 Document the ZT trace bus and ZTR trace clocks on R-Mobile A1. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,cpg-clocks.yaml | 6 ++++-- include/dt-bindings/clock/r8a7740-clock.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f0..925ed35d6658 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -123,6 +123,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt required: - renesas,mode @@ -240,6 +242,6 @@ examples: #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", "m1", "hp", "hpp", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; renesas,mode = <0x05>; }; diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h index 1b3fdb39cc42..8a8816b2ff6a 100644 --- a/include/dt-bindings/clock/r8a7740-clock.h +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -24,6 +24,8 @@ #define R8A7740_CLK_ZB 14 #define R8A7740_CLK_M3 15 #define R8A7740_CLK_CP 16 +#define R8A7740_CLK_ZTR 17 +#define R8A7740_CLK_ZT 18 /* MSTP1 */ #define R8A7740_CLK_CEU21 28 From 9c45ef9a84bd18cbd2052d5e64b2144018f5bb32 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 17 Mar 2026 10:16:14 +0000 Subject: [PATCH 15/40] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names All SoCs have multiple resets. Document the reset-names property. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260317101627.174491-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a4..1a94e396b1b0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -78,6 +78,16 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + additionalProperties: anyOf: - type: object @@ -152,10 +162,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +201,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { From 43d2cd6f61ffc04be19f4c7542554e4d28786a17 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 10:34:06 +0100 Subject: [PATCH 16/40] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Add documentation for the pin controller found on the Renesas RZ/G3L (R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has more pins. Also add header file similar to RZ/G3E and RZ/V2H as it has alpha numeric ports. Document renesas,clonech property for controlling clone channel control register located on SYSC IP block on RZ/G3L SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430093422.74812-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 ++++++++++ .../pinctrl/renesas,r9a08g046-pinctrl.h | 38 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 1a94e396b1b0..fb1fe1ea759f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -88,6 +89,16 @@ properties: - const: main - const: error + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -150,6 +161,15 @@ additionalProperties: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + - if: properties: compatible: diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 000000000000..5ec5bfc27c7d --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindings. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include + +/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */ From 3bee9d4854f2ce24d0a8febed6de94271b135c60 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:17 +0100 Subject: [PATCH 17/40] arm64: dts: renesas: r8a77960-ulcb: Enable GPU support Enable GPU on M3ULCB with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts index 4bfeb1df0488..c3282593346b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts @@ -36,3 +36,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 1f07cd3bcc57f87c33ce89e50f7a310834009a3e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:18 +0100 Subject: [PATCH 18/40] arm64: dts: renesas: r8a77960-salvator-x: Enable GPU support Enable GPU on Salvator-X with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts index d5543f26c472..0d5c754a7f0e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts @@ -35,3 +35,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 27f6150e18c97d9aeb50c805f45377b9865bd08b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:19 +0100 Subject: [PATCH 19/40] arm64: dts: renesas: r8a77960-salvator-xs: Enable GPU support Enable GPU on Salvator-X 2nd version with R-Car M3-W. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts index 9ebb47b6bf2d..115cc47bb072 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts @@ -35,3 +35,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 5de368c91cb58f9f984ecbcde5145431d1a5adcc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:20 +0100 Subject: [PATCH 20/40] arm64: dts: renesas: r8a77961-ulcb: Enable GPU support Enable GPU on M3ULCB with R-Car M3-W+. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts index 70cf926667a6..0c0806cec698 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts @@ -40,3 +40,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From 96da5423288904f50c97e48e1d31a39d21c00ecb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 22:12:21 +0100 Subject: [PATCH 21/40] arm64: dts: renesas: r8a77961-salvator-xs: Enable GPU support Enable GPU on Salvator-X 2nd version with R-Car M3-W+. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251027211249.95826-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index c7f14177f7b9..b35de49406a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -40,3 +40,7 @@ &du { clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; + +&gpu { + status = "okay"; +}; From a357a31c3436ee90a991f1111e7c1ae93ed84f75 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 26 Mar 2026 11:19:49 +0000 Subject: [PATCH 22/40] arm64: dts: renesas: r9a08g046: Add GBETH nodes Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet (10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes to R9A08G046 RZ/G3L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326111953.31024-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 241 +++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 28b0c7558748..236a675231e5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -171,6 +171,240 @@ sdhi1: mmc@11c10000 { /* placeholder */ }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH0_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup0>; + snps,mtl-tx-config = <&mtl_tx_setup0>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets = <&cpg R9A08G046_ETH1_ARESET_N>; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,weight = <0x14>; + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,weight = <0x18>; + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + }; + }; + pcie: pcie@11e40000 { reg = <0 0x11e40000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; @@ -200,6 +434,13 @@ gic: interrupt-controller@12400000 { }; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From ab47929332551a4b2a9d38f5e31e1d9ab6a99c1a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 26 Mar 2026 11:19:50 +0000 Subject: [PATCH 23/40] arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH0) interface Enable the Gigabit Ethernet Interfaces (GBETH0) populated on the RZ/G3L SMARC EVK. The eth1, pincontrol definitions and hotplug support will be added later. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326111953.31024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index ab4950671c7c..fb781d9035aa 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -8,6 +8,10 @@ / { compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; + aliases { + ethernet0 = ð0; + }; + memory@48000000 { device_type = "memory"; /* First 128MiB is reserved for secure area. */ @@ -15,6 +19,36 @@ memory@48000000 { }; }; +ð0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +ð0_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; + +&mdio0 { + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; From 1d4bed0d9cb25ea40852a782973b821af520f73a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:29 +0200 Subject: [PATCH 24/40] ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clocks Add ZT trace bus and ZTR trace clocks on R-Mobile A1. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, coresight tracing can not be operated. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index d13ab86c3ab4..f7136db7a2ea 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -553,7 +553,7 @@ cpg_clocks: cpg_clocks@e6150000 { "usb24s", "i", "zg", "b", "m1", "hp", "hpp", "usbp", "s", "zb", "m3", - "cp"; + "cp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ From dfe6b60d5898730b2ea99e61564d17feedee25ad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Apr 2026 01:36:30 +0200 Subject: [PATCH 25/40] ARM: dts: renesas: r8a7740: Describe coresight Describe the coresight topology on R-Mobile A1. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. Coresight on this hardware is clocked from the ZT/ZTR trace clocks. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260422233744.149872-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 114 ++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index f7136db7a2ea..c7056b96ec0b 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -18,7 +18,7 @@ / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -59,9 +59,117 @@ pmu { interrupts = ; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6fa1000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xe6fa1000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6fa3000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe6fa3000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xe6fbc000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; ceu0: ceu@fe910000 { From 998dd840cc7a54df214bc1a3751d5ad334e7dad1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 17 Mar 2026 10:16:16 +0000 Subject: [PATCH 26/40] arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs Add reset-names properties to the pin control nodes for RZ/{G2L,G2UL,G3E,G3S} and RZ/{V2H,V2L,V2N} SoCs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260317101627.174491-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad1..ded4f1f11d60 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -604,6 +604,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; dmac: dma-controller@11820000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 29273da81995..cb0c9550aa03 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1017,6 +1017,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0dee48c4f1e4..7a3e5b6a685f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1025,6 +1025,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 997e6cf0bb82..3a69bb246bab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -533,6 +533,7 @@ pinctrl: pinctrl@11030000 { resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; }; irqc: interrupt-controller@11050000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 95a4e30a064d..4267b10937f3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -265,6 +265,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 7ccddd6a4a9a..dc5b116679c0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -288,6 +288,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 6f6fe5f36bef..1e94366bb7ee 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -270,6 +270,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; + reset-names = "main", "error"; }; cpg: clock-controller@10420000 { From 60f8dfd33c1c7daade9846207be735c7f4fd802d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:05 +0100 Subject: [PATCH 27/40] arm64: dts: renesas: r9a08g046: Add OPP table Add OPP table for RZ/G3L SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 236a675231e5..e52498b3a745 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -14,6 +14,42 @@ / { #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +60,8 @@ cpu0: cpu@0 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +70,8 @@ cpu1: cpu@100 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +80,8 @@ cpu2: cpu@200 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +90,8 @@ cpu3: cpu@300 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From b3eea87822b799051745fff61b2e8d0313901ea1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:06 +0100 Subject: [PATCH 28/40] arm64: dts: renesas: r9a08g046: Add ICU node Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index e52498b3a745..232a0e299df7 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -210,6 +210,96 @@ pinctrl: pinctrl@11030000 { /* placeholder */ }; + icu: interrupt-controller@11050000 { + compatible = "renesas,r9a08g046-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0", + "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3", + "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7"; + clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>, + <&cpg CPG_MOD R9A08G046_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_IA55_RESETN>; + }; + sdhi1: mmc@11c10000 { reg = <0x0 0x11c10000 0 0x10000>; /* placeholder */ From ea82a68bb33691ea16188b6b9bef15cde874a193 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:07 +0100 Subject: [PATCH 29/40] arm64: dts: renesas: r9a08g046: Add pincontrol node Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI and set the icu as the interrupt-parent of the pin controller to route GPIO interrupts through the IA55 interrupt controller. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 232a0e299df7..0cedf5a38291 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -204,10 +204,21 @@ sysc: system-controller@11020000 { }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g046-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* placeholder */ + gpio-ranges = <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; + clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; + renesas,clonech = <&sysc 0xe2c>; }; icu: interrupt-controller@11050000 { From cdc8ef62ae6d04d2ba6a9226bc432168d06ad9a5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:08 +0100 Subject: [PATCH 30/40] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Add device node for SCIF0 pincontrol. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 86db86335d5e..acead2b1c842 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -35,3 +35,15 @@ &keys { /delete-node/ key-2; /delete-node/ key-3; }; + +&pinctrl { + scif0_pins: scif0 { + pins = "SCIF0_TXD", "SCIF0_RXD"; + power-source = <1800>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; +}; From 72411a23c3942a2d5462f1695f0bceaf1c018bf7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:09 +0100 Subject: [PATCH 31/40] arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 Add pin control configuration for the ETH0 Ethernet interface on the RZ/G3L SMARC SoM board and also enable hotplug support. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index acead2b1c842..0ae052238b3b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ #include #include +#include #include "r9a08g046l48.dtsi" #include "rzg3l-smarc-som.dtsi" #include "renesas-smarc2.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index fb781d9035aa..c7227a865fa4 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -23,6 +23,8 @@ ð0 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; status = "okay"; }; @@ -38,6 +40,7 @@ &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640"; reg = <7>; + interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <1400>; txc-skew-psec = <1400>; rxdv-skew-psec = <0>; @@ -52,3 +55,32 @@ phy0: ethernet-phy@7 { txd3-skew-psec = <0>; }; }; + +&pinctrl { + eth0_pins: eth0 { + txc { + pinmux = ; /* ETH0_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = , /* MDIO */ + , /* MDC */ + , /* RX_CTL */ + , /* TX_CTL */ + , /* RXC */ + , /* TXD0 */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR */ + power-source = <1800>; + }; + }; +}; From 8a59e4f535a876fe94034f3a1e44b371d1fe363f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 30 Apr 2026 13:53:10 +0100 Subject: [PATCH 32/40] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Enable the Gigabit Ethernet Interface (GBETH1) populated on the RZ/G3L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260430125342.439755-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index c7227a865fa4..f53e6332e2f4 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -10,6 +10,7 @@ / { aliases { ethernet0 = ð0; + ethernet1 = ð1; }; memory@48000000 { @@ -32,6 +33,19 @@ ð0_rxc_rx_clk { clock-frequency = <125000000>; }; +ð1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +ð1_rxc_rx_clk { + clock-frequency = <125000000>; +}; + &extal_clk { clock-frequency = <24000000>; }; @@ -56,6 +70,26 @@ phy0: ethernet-phy@7 { }; }; +&mdio1 { + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640"; + reg = <7>; + interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <1400>; + txc-skew-psec = <1400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &pinctrl { eth0_pins: eth0 { txc { @@ -83,4 +117,31 @@ ctrl { power-source = <1800>; }; }; + + eth1_pins: eth1 { + txc { + pinmux = ; /* ETH1_TXC_REF_CLK */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + ctrl { + pinmux = , /* MDIO */ + , /* MDC */ + , /* RX_CTL */ + , /* TX_CTL */ + , /* RXC */ + , /* TXD0 */ + , /* TXD1 */ + , /* TXD2 */ + , /* TXD3 */ + , /* RXD0 */ + , /* RXD1 */ + , /* RXD2 */ + , /* RXD3 */ + ; /* PHY_INTR */ + power-source = <1800>; + }; + }; }; From 7f951abdd4274fedf1b011ff5e7d97fcdab20f03 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:11 +0200 Subject: [PATCH 33/40] arm64: dts: renesas: gray-hawk-single: Fix AVB0 PHY node alignment Trivially fix PHY node alignment. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225428.114959-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi index 2edb5cb3407b..792a4aa8f4a9 100644 --- a/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi +++ b/arch/arm64/boot/dts/renesas/gray-hawk-single.dtsi @@ -208,11 +208,11 @@ mdio { avb0_phy: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; }; }; }; From 3065cc03532fc218d290f5812b24408425ad8a28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:42 +0200 Subject: [PATCH 34/40] arm64: dts: renesas: ebisu: Sort sound node Sort /sound {} node in the correct order alphabetically. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225515.114986-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 34 +++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index aaedb1fb51ae..ba564aa09866 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -186,23 +186,6 @@ reg_12p0v: regulator-12p0v { regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4613"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -260,6 +243,23 @@ vccq_sdhi1: regulator-vccq-sdhi1 { states = <3300000 1>, <1800000 0>; }; + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4613"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + }; + vga { compatible = "vga-connector"; From 89b67a16a59b66b0dfb26307c5858e9cddcbb242 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 May 2026 00:54:43 +0200 Subject: [PATCH 35/40] arm64: dts: renesas: salvator-common: Sort sound node Sort /sound {} node in the correct order alphabetically. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260504225515.114986-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/salvator-common.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index e505161caa67..0b29bf9564eb 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -211,19 +211,6 @@ reg_12v: regulator-12v { regulator-always-on; }; - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ -#ifdef SOC_HAS_HDMI1 - &rsnd_port2 /* HDMI1 */ -#endif - >; - }; - vbus0_usb2: regulator-vbus0-usb2 { compatible = "regulator-fixed"; @@ -281,6 +268,19 @@ vccq_sdhi3: regulator-vccq-sdhi3 { states = <3300000 1>, <1800000 0>; }; + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ +#ifdef SOC_HAS_HDMI1 + &rsnd_port2 /* HDMI1 */ +#endif + >; + }; + vga { compatible = "vga-connector"; From 8e46bc6370d08a21cc43bb747aef8ffae45df7d7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:59:16 +0100 Subject: [PATCH 36/40] arm64: dts: renesas: r9a08g046: Add wdt device node The RZ/G3L SOC has 3 watchdog timer channels: - channel0 (wdt0) for Cortex-A55-CPU Non-Secure, - channel1 (wdt1) for Cortex-A55 CPU Secure, - channel2 (wdt2) for Cortex-M33 CPU. Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505125921.149682-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 0cedf5a38291..02a3029c058e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -577,6 +577,20 @@ gic: interrupt-controller@12400000 { interrupt-controller; interrupts = ; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G046_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G046_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; stmmac_axi_setup: stmmac-axi-config { From 5a5dcb6a52feeef07bc6ad4e32f8276b1093b8f6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 5 May 2026 13:59:17 +0100 Subject: [PATCH 37/40] arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog Enable watchdog timer channel0 on RZ/G3L SoM DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505125921.149682-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi index f53e6332e2f4..b28e59a65259 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -145,3 +145,8 @@ ctrl { }; }; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; From 2abdc3dcf9780d070e55a99fdf8f93440c798b84 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:42 +0200 Subject: [PATCH 38/40] dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 Document the ZT trace bus and ZTR trace clocks on R-Mobile APE6. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml | 2 ++ include/dt-bindings/clock/r8a73a4-clock.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index 925ed35d6658..703b5bf26717 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -90,6 +90,8 @@ allOf: - const: zx - const: zs - const: hp + - const: ztr + - const: zt - if: properties: diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h index 655440a3e7c6..028ecef81451 100644 --- a/include/dt-bindings/clock/r8a73a4-clock.h +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -23,6 +23,8 @@ #define R8A73A4_CLK_ZX 13 #define R8A73A4_CLK_ZS 14 #define R8A73A4_CLK_HP 15 +#define R8A73A4_CLK_ZTR 16 +#define R8A73A4_CLK_ZT 17 /* MSTP1 */ #define R8A73A4_CLK_TMU0 25 From dde06a5a809141c6c304241a0f78ff6e60191b87 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:44 +0200 Subject: [PATCH 39/40] ARM: dts: renesas: r8a73a4: Add ZT/ZTR trace clock on R-Mobile APE6 Add ZT trace bus and ZTR trace clock on the R-Mobile APE6. These clock supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, the coresight tracing can not be operated. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index 2e19ebf9e2ba..a70a0dc402a5 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -512,7 +512,7 @@ cpg_clocks: cpg_clocks@e6150000 { clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; + "zx", "zs", "hp", "ztr", "zt"; }; /* Variable factor clocks (DIV6) */ From 44f1ef06ceec55b7704c7d773d6136ca8b90f8b7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 2 May 2026 20:55:45 +0200 Subject: [PATCH 40/40] ARM: dts: renesas: r8a73a4: Describe coresight on R-Mobile APE6 Describe coresight topology on R-Mobile APE6. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. The coresight on this hardware is clocked from the ZT/ZTR trace clock. Note that only core 0 part of the topology is described, because the other cores are still not present in the DT. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260502185557.93061-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 112 ++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index a70a0dc402a5..c3427dc7cf7d 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -47,9 +47,117 @@ L2_CA7: cache-controller-1 { }; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6f81000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe6f81000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6f83000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xe6f83000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe6fbc000 0 0x1000>; + clocks = <&cpg_clocks R8A73A4_CLK_ZT>, <&cpg_clocks R8A73A4_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; timer {