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Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' into clk-next

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* clk-ti:
  clk: keystone: sci-clk: fix application of sizeof to pointer
  clk: keystone: don't cache clock rate

* clk-samsung:
  clk: samsung: exynos990: Fix PERIC0/1 USI clock types
  clk: samsung: exynos850: mark APM I3C clocks as critical

* clk-rockchip:
  clk: rockchip: allow COMPILE_TEST builds
  clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO
  soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset
  clk: rockchip: add helper to register auxiliary GRFs
  clk: rockchip: allow grf_type_sys lookup in aux_grf_table
  dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs

* clk-spacemit:
  clk: spacemit: k3: Add PCIe DBI clock
  dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
  clk: spacemit: k3: Fix PCIe clock register offset
  clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
This commit is contained in:
Stephen Boyd 2026-06-25 07:55:38 -07:00
commit db810874e5
No known key found for this signature in database
GPG Key ID: AD028897C6E49525
13 changed files with 230 additions and 185 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/Makefile
View File

@ -142,7 +142,7 @@ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-y += ralink/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-y += socfpga/

10
drivers/clk/keystone/sci-clk.c
View File

@ -333,6 +333,14 @@ static int _sci_clk_build(struct sci_clk_provider *provider,
init.ops = &sci_clk_ops;
init.num_parents = sci_clk->num_parents;
/*
* A clock rate query to the SCI firmware will return 0 if either the
* clock itself is disabled or the attached device/consumer is disabled.
* This makes it inherently unsuitable for the caching of the clk
* framework.
*/
init.flags = CLK_GET_RATE_NOCACHE;
sci_clk->hw.init = &init;
ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
@ -388,7 +396,7 @@ static struct clk_hw *sci_clk_get(struct of_phandle_args *clkspec, void *data)
key.clk_id = clkspec->args[1];
clk = bsearch(&key, provider->clocks, provider->num_clocks,
sizeof(clk), _cmp_sci_clk);
sizeof(*clk), _cmp_sci_clk);
if (!clk)
return ERR_PTR(-ENODEV);

2
drivers/clk/rockchip/Kconfig
View File

@ -3,7 +3,7 @@
config COMMON_CLK_ROCKCHIP
bool "Rockchip clock controller common support"
depends on ARCH_ROCKCHIP
depends on ARCH_ROCKCHIP || COMPILE_TEST
default ARCH_ROCKCHIP
help
Say y here to enable common clock controller for Rockchip platforms.

16
drivers/clk/rockchip/clk-rk3588.c
View File

@ -5,11 +5,13 @@
*/
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <soc/rockchip/rk3588_grf.h>
#include "clk.h"
#define RK3588_GRF_SOC_STATUS0 0x600
@ -892,6 +894,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(8), 0, GFLAGS),
MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
GATE_GRF(I2S2_2CH_MCLKOUT_TO_IO, "i2s2_2ch_mclkout_to_io", "i2s2_2ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 2, GFLAGS, grf_type_sys),
COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
@ -907,6 +911,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(8), 4, GFLAGS),
MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
GATE_GRF(I2S3_2CH_MCLKOUT_TO_IO, "i2s3_2ch_mclkout_to_io", "i2s3_2ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 7, GFLAGS, grf_type_sys),
GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 11, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
@ -935,6 +941,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(7), 10, GFLAGS),
MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
GATE_GRF(I2S0_8CH_MCLKOUT_TO_IO, "i2s0_8ch_mclkout_to_io", "i2s0_8ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 0, GFLAGS, grf_type_sys),
GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(9), 6, GFLAGS),
@ -2220,6 +2228,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
GATE_GRF(I2S1_8CH_MCLKOUT_TO_IO, "i2s1_8ch_mclkout_to_io", "i2s1_8ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 1, GFLAGS, grf_type_sys),
GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
@ -2439,6 +2449,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] = {
static void __init rk3588_clk_early_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
struct regmap *sys_grf;
unsigned long clk_nr_clks, max_clk_id1, max_clk_id2;
void __iomem *reg_base;
@ -2479,6 +2490,11 @@ static void __init rk3588_clk_early_init(struct device_node *np)
&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
ARRAY_SIZE(rk3588_cpub1clk_rates));
/* Register SYS_GRF for I2S MCLK output to IO gate clocks */
sys_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3588-sys-grf");
if (!IS_ERR(sys_grf))
rockchip_clk_add_grf(ctx, sys_grf, grf_type_sys);
rockchip_clk_register_branches(ctx, rk3588_early_clk_branches,
ARRAY_SIZE(rk3588_early_clk_branches));

25
drivers/clk/rockchip/clk.c
View File

@ -429,6 +429,24 @@ void rockchip_clk_of_add_provider(struct device_node *np,
}
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
int rockchip_clk_add_grf(struct rockchip_clk_provider *ctx,
struct regmap *grf,
enum rockchip_grf_type type)
{
struct rockchip_aux_grf *aux_grf;
aux_grf = kzalloc_obj(*aux_grf);
if (!aux_grf)
return -ENOMEM;
aux_grf->grf = grf;
aux_grf->type = type;
hash_add(ctx->aux_grf_table, &aux_grf->node, type);
return 0;
}
EXPORT_SYMBOL_GPL(rockchip_clk_add_grf);
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
@ -509,10 +527,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
clk = NULL;
/* for GRF-dependent branches, choose the right grf first */
if ((list->branch_type == branch_grf_mux ||
list->branch_type == branch_grf_gate ||
list->branch_type == branch_grf_mmc) &&
list->grf_type != grf_type_sys) {
if (list->branch_type == branch_grf_mux ||
list->branch_type == branch_grf_gate ||
list->branch_type == branch_grf_mmc) {
hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
if (agrf->type == list->grf_type) {
grf = agrf->grf;

3
drivers/clk/rockchip/clk.h
View File

@ -1329,6 +1329,9 @@ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
void rockchip_clk_of_add_provider(struct device_node *np,
struct rockchip_clk_provider *ctx);
int rockchip_clk_add_grf(struct rockchip_clk_provider *ctx,
struct regmap *grf,
enum rockchip_grf_type type);
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
unsigned int nr_clk);
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,

5
drivers/clk/samsung/clk-exynos850.c
View File

@ -686,10 +686,11 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
/* TODO: Should be dealt with or enabled in PMIC ACPM driver */
GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */

307
drivers/clk/samsung/clk-exynos990.c
View File

@ -1546,54 +1546,44 @@ static const unsigned long peric0_clk_regs[] __initconst = {
/* Parent clock list for CMU_PERIC0 muxes */
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_nonbususer_p) = { "oscclk", "dout_cmu_peric0_ip" };
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
4, 1),
MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user",
mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
4, 1),
};
@ -1602,42 +1592,42 @@ static const struct samsung_div_clock peric0_div_clks[] __initconst = {
"mout_peric0_uart_dbg",
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
0, 4),
DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
"mout_peric0_usi00_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
"mout_peric0_usi01_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
"mout_peric0_usi02_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
"mout_peric0_usi03_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
"mout_peric0_usi04_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
"mout_peric0_usi05_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
"mout_peric0_usi13_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
"mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
"mout_peric0_usi15_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
0, 4),
DIV_F(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
"mout_peric0_usi00_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
"mout_peric0_usi01_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
"mout_peric0_usi02_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
"mout_peric0_usi03_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
"mout_peric0_usi04_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
"mout_peric0_usi05_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
"mout_peric0_usi13_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
"mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
"mout_peric0_usi15_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
"mout_peric0_usi_i2c_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
@ -2107,58 +2097,47 @@ static const unsigned long peric1_clk_regs[] __initconst = {
/* Parent clock list for CMU_PERIC1 muxes */
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user",
mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
4, 1),
};
@ -2167,46 +2146,46 @@ static const struct samsung_div_clock peric1_div_clks[] __initconst = {
"mout_peric1_uart_bt_user",
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
0, 4),
DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
"mout_peric1_usi06_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
"mout_peric1_usi07_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
"mout_peric1_usi08_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
"mout_peric1_usi18_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
"mout_peric1_usi12_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
"mout_peric1_usi16_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
"mout_peric1_usi17_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
0, 4),
DIV_F(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
"mout_peric1_usi06_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
"mout_peric1_usi07_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
"mout_peric1_usi08_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
"mout_peric1_usi18_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
"mout_peric1_usi12_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
"mout_peric1_usi16_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
"mout_peric1_usi17_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
"mout_peric1_usi_i2c_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,

30
drivers/clk/spacemit/ccu-k3.c
View File

@ -947,16 +947,21 @@ static const struct clk_parent_data edp1_pclk_parents[] = {
};
CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0);
CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
static const struct clk_parent_data emac_1588_parents[] = {
CCU_PARENT_NAME(vctcxo_24m),
@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw,
[CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw,
[CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw,
[CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw,
[CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw,
[CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw,
[CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw,
[CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw,
[CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw,

4
include/dt-bindings/clock/rockchip,rk3588-cru.h
View File

@ -734,6 +734,10 @@
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
#define PCLK_VO1GRF 721
#define I2S0_8CH_MCLKOUT_TO_IO 722
#define I2S1_8CH_MCLKOUT_TO_IO 723
#define I2S2_2CH_MCLKOUT_TO_IO 724
#define I2S3_2CH_MCLKOUT_TO_IO 725
/* scmi-clocks indices */

5
include/dt-bindings/clock/spacemit,k3-clocks.h
View File

@ -380,6 +380,11 @@
#define CLK_APMU_ISIM_VCLK1 86
#define CLK_APMU_ISIM_VCLK2 87
#define CLK_APMU_ISIM_VCLK3 88
#define CLK_APMU_PCIE_PORTA_DBI 89
#define CLK_APMU_PCIE_PORTB_DBI 90
#define CLK_APMU_PCIE_PORTC_DBI 91
#define CLK_APMU_PCIE_PORTD_DBI 92
#define CLK_APMU_PCIE_PORTE_DBI 93
/* DCIU clocks */
#define CLK_DCIU_HDMA 0

2
include/soc/rockchip/rk3588_grf.h
View File

@ -19,4 +19,6 @@
/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0)
#define RK3588_SYSGRF_SOC_CON6 0x0318
#endif /* __SOC_RK3588_GRF_H */

4
include/soc/spacemit/k3-syscon.h
View File

@ -168,8 +168,8 @@
#define APMU_CPU_C2_CLK_CTRL 0x394
#define APMU_CPU_C3_CLK_CTRL 0x208
#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0
#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0
#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0
#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0
#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4