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gate-clocks for i2s outputs on rk3588 and allowing compile-tests

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for the whole clock driver.
 The sparse warning when the Rockchip clock is compiled on M68K gets
 fixed by:
 https://lore.kernel.org/lkml/b55e9bd0532c0cad519809c86e0a8400060d75a1.1780559561.git.geert@linux-m68k.org/
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Merge tag 'v7.2-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Add gate-clocks for i2s outputs on Rockchip rk3588
 - Allow compile-tests for the whole clock driver

* tag 'v7.2-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: allow COMPILE_TEST builds
  clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO
  soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset
  clk: rockchip: add helper to register auxiliary GRFs
  clk: rockchip: allow grf_type_sys lookup in aux_grf_table
  dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs
This commit is contained in:
Stephen Boyd 2026-06-13 14:04:36 -07:00
commit 0f92f188c8
7 changed files with 48 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/Makefile
View File

@ -141,7 +141,7 @@ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-y += ralink/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-y += socfpga/

2
drivers/clk/rockchip/Kconfig
View File

@ -3,7 +3,7 @@
config COMMON_CLK_ROCKCHIP
bool "Rockchip clock controller common support"
depends on ARCH_ROCKCHIP
depends on ARCH_ROCKCHIP || COMPILE_TEST
default ARCH_ROCKCHIP
help
Say y here to enable common clock controller for Rockchip platforms.

16
drivers/clk/rockchip/clk-rk3588.c
View File

@ -5,11 +5,13 @@
*/
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <soc/rockchip/rk3588_grf.h>
#include "clk.h"
#define RK3588_GRF_SOC_STATUS0 0x600
@ -892,6 +894,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(8), 0, GFLAGS),
MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
GATE_GRF(I2S2_2CH_MCLKOUT_TO_IO, "i2s2_2ch_mclkout_to_io", "i2s2_2ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 2, GFLAGS, grf_type_sys),
COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
@ -907,6 +911,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(8), 4, GFLAGS),
MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
GATE_GRF(I2S3_2CH_MCLKOUT_TO_IO, "i2s3_2ch_mclkout_to_io", "i2s3_2ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 7, GFLAGS, grf_type_sys),
GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 11, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
@ -935,6 +941,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(7), 10, GFLAGS),
MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
GATE_GRF(I2S0_8CH_MCLKOUT_TO_IO, "i2s0_8ch_mclkout_to_io", "i2s0_8ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 0, GFLAGS, grf_type_sys),
GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(9), 6, GFLAGS),
@ -2220,6 +2228,8 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
GATE_GRF(I2S1_8CH_MCLKOUT_TO_IO, "i2s1_8ch_mclkout_to_io", "i2s1_8ch_mclkout",
0, RK3588_SYSGRF_SOC_CON6, 1, GFLAGS, grf_type_sys),
GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
@ -2439,6 +2449,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] = {
static void __init rk3588_clk_early_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
struct regmap *sys_grf;
unsigned long clk_nr_clks, max_clk_id1, max_clk_id2;
void __iomem *reg_base;
@ -2479,6 +2490,11 @@ static void __init rk3588_clk_early_init(struct device_node *np)
&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
ARRAY_SIZE(rk3588_cpub1clk_rates));
/* Register SYS_GRF for I2S MCLK output to IO gate clocks */
sys_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3588-sys-grf");
if (!IS_ERR(sys_grf))
rockchip_clk_add_grf(ctx, sys_grf, grf_type_sys);
rockchip_clk_register_branches(ctx, rk3588_early_clk_branches,
ARRAY_SIZE(rk3588_early_clk_branches));

25
drivers/clk/rockchip/clk.c
View File

@ -429,6 +429,24 @@ void rockchip_clk_of_add_provider(struct device_node *np,
}
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
int rockchip_clk_add_grf(struct rockchip_clk_provider *ctx,
struct regmap *grf,
enum rockchip_grf_type type)
{
struct rockchip_aux_grf *aux_grf;
aux_grf = kzalloc_obj(*aux_grf);
if (!aux_grf)
return -ENOMEM;
aux_grf->grf = grf;
aux_grf->type = type;
hash_add(ctx->aux_grf_table, &aux_grf->node, type);
return 0;
}
EXPORT_SYMBOL_GPL(rockchip_clk_add_grf);
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
@ -509,10 +527,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
clk = NULL;
/* for GRF-dependent branches, choose the right grf first */
if ((list->branch_type == branch_grf_mux ||
list->branch_type == branch_grf_gate ||
list->branch_type == branch_grf_mmc) &&
list->grf_type != grf_type_sys) {
if (list->branch_type == branch_grf_mux ||
list->branch_type == branch_grf_gate ||
list->branch_type == branch_grf_mmc) {
hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
if (agrf->type == list->grf_type) {
grf = agrf->grf;

3
drivers/clk/rockchip/clk.h
View File

@ -1329,6 +1329,9 @@ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
void rockchip_clk_of_add_provider(struct device_node *np,
struct rockchip_clk_provider *ctx);
int rockchip_clk_add_grf(struct rockchip_clk_provider *ctx,
struct regmap *grf,
enum rockchip_grf_type type);
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
unsigned int nr_clk);
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,

4
include/dt-bindings/clock/rockchip,rk3588-cru.h
View File

@ -734,6 +734,10 @@
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
#define PCLK_VO1GRF 721
#define I2S0_8CH_MCLKOUT_TO_IO 722
#define I2S1_8CH_MCLKOUT_TO_IO 723
#define I2S2_2CH_MCLKOUT_TO_IO 724
#define I2S3_2CH_MCLKOUT_TO_IO 725
/* scmi-clocks indices */

2
include/soc/rockchip/rk3588_grf.h
View File

@ -19,4 +19,6 @@
/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0)
#define RK3588_SYSGRF_SOC_CON6 0x0318
#endif /* __SOC_RK3588_GRF_H */