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Samsung SoC clock drivers changes for v7.2

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1. Exynos850: Mark APM (Active Power Management) I3C clocks as critical,
    because they are necessary for communication with firmware but we do
    not have any consumer of them so far.
 
 2. Exynos990: Correct the parents of a few muxes and propagate rate
    requests up.
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Merge tag 'samsung-clk-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:

 - Exynos850: Mark APM (Active Power Management) I3C clocks as
   critical, because they are necessary for communication with
   firmware but we do not have any consumer of them so far.
 - Exynos990: Correct the parents of a few muxes and propagate
   rate requests up.

* tag 'samsung-clk-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: exynos990: Fix PERIC0/1 USI clock types
  clk: samsung: exynos850: mark APM I3C clocks as critical
This commit is contained in:
Stephen Boyd 2026-06-13 14:03:02 -07:00
commit 3bb620aefb
2 changed files with 146 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/samsung/clk-exynos850.c
View File

@ -686,10 +686,11 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
/* TODO: Should be dealt with or enabled in PMIC ACPM driver */
GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */

307
drivers/clk/samsung/clk-exynos990.c
View File

@ -1546,54 +1546,44 @@ static const unsigned long peric0_clk_regs[] __initconst = {
/* Parent clock list for CMU_PERIC0 muxes */
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
PNAME(mout_peric0_nonbususer_p) = { "oscclk", "dout_cmu_peric0_ip" };
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
4, 1),
MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user",
mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
mout_peric0_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
4, 1),
};
@ -1602,42 +1592,42 @@ static const struct samsung_div_clock peric0_div_clks[] __initconst = {
"mout_peric0_uart_dbg",
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
0, 4),
DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
"mout_peric0_usi00_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
"mout_peric0_usi01_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
"mout_peric0_usi02_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
"mout_peric0_usi03_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
"mout_peric0_usi04_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
"mout_peric0_usi05_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
"mout_peric0_usi13_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
"mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
"mout_peric0_usi15_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
0, 4),
DIV_F(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
"mout_peric0_usi00_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
"mout_peric0_usi01_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
"mout_peric0_usi02_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
"mout_peric0_usi03_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
"mout_peric0_usi04_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
"mout_peric0_usi05_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
"mout_peric0_usi13_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
"mout_peric0_usi14_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
"mout_peric0_usi15_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
"mout_peric0_usi_i2c_user",
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
@ -2107,58 +2097,47 @@ static const unsigned long peric1_clk_regs[] __initconst = {
/* Parent clock list for CMU_PERIC1 muxes */
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
4, 1),
nMUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
4, 1),
MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user",
mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
4, 1),
};
@ -2167,46 +2146,46 @@ static const struct samsung_div_clock peric1_div_clks[] __initconst = {
"mout_peric1_uart_bt_user",
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
0, 4),
DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
"mout_peric1_usi06_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
"mout_peric1_usi07_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
"mout_peric1_usi08_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
"mout_peric1_usi18_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
"mout_peric1_usi12_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
"mout_peric1_usi16_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
"mout_peric1_usi17_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
0, 4),
DIV_F(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
"mout_peric1_usi06_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
"mout_peric1_usi07_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
"mout_peric1_usi08_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
"mout_peric1_usi18_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
"mout_peric1_usi12_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
"mout_peric1_usi16_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
"mout_peric1_usi17_usi_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 0, 4,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
"mout_peric1_usi_i2c_user",
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,