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PCI: mediatek-gen3: Add 100 ms delay after link up

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The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after
link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0
sec 6.6.1.

The driver already stores max_link_speed (from the device tree). After
mtk_pcie_startup_port() successfully brings up the link, call
pci_host_common_link_train_delay() to comply with the specification.

Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260518004246.1384532-7-18255117159@163.com
This commit is contained in:
Hans Zhang 2026-05-18 08:42:45 +08:00 committed by Bjorn Helgaas
parent 6bba1de54c
commit d24e3fab6e
1 changed files with 3 additions and 0 deletions
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3
drivers/pci/controller/pcie-mediatek-gen3.c
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@ -30,6 +30,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include "pci-host-common.h"
#include "../pci.h"
#define PCIE_BASE_CFG_REG 0x14
@ -570,6 +571,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
goto err_power_down_device;
}
pci_host_common_link_train_delay(pcie->max_link_speed);
return 0;
err_power_down_device: