From d24e3fab6ee23c2d7076b0e5ffe5c7210cc9dae3 Mon Sep 17 00:00:00 2001 From: Hans Zhang <18255117159@163.com> Date: Mon, 18 May 2026 08:42:45 +0800 Subject: [PATCH] PCI: mediatek-gen3: Add 100 ms delay after link up The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0 sec 6.6.1. The driver already stores max_link_speed (from the device tree). After mtk_pcie_startup_port() successfully brings up the link, call pci_host_common_link_train_delay() to comply with the specification. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20260518004246.1384532-7-18255117159@163.com --- drivers/pci/controller/pcie-mediatek-gen3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index b0accd828589..5abddec4e9be 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -30,6 +30,7 @@ #include #include +#include "pci-host-common.h" #include "../pci.h" #define PCIE_BASE_CFG_REG 0x14 @@ -570,6 +571,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) goto err_power_down_device; } + pci_host_common_link_train_delay(pcie->max_link_speed); + return 0; err_power_down_device: