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PCI: aardvark: Add 100 ms delay after link training

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The Aardvark PCIe controller driver waits for the link to come up but
does not implement the mandatory 100 ms delay after link training
completes for speeds greater than 5.0 GT/s (PCIe r6.0 sec 6.6.1).

The driver already maintains a 'link_gen' field that holds the negotiated
link speed. Use it together with pci_host_common_link_train_delay() to
insert the required delay immediately after confirming that the link
is up.

Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260518004246.1384532-6-18255117159@163.com
This commit is contained in:
Hans Zhang 2026-05-18 08:42:44 +08:00 committed by Bjorn Helgaas
parent 0a46957df4
commit 6bba1de54c
1 changed files with 4 additions and 1 deletions
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5
drivers/pci/controller/pci-aardvark.c
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@ -26,6 +26,7 @@
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include "pci-host-common.h"
#include "../pci.h"
#include "../pci-bridge-emul.h"
@ -350,8 +351,10 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
/* check if the link is up or not */
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
if (advk_pcie_link_up(pcie))
if (advk_pcie_link_up(pcie)) {
pci_host_common_link_train_delay(pcie->link_gen);
return 0;
}
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
}