arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes

Add vspd{0,1} nodes to the RZ/G3E SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://patch.msgid.link/46547aaff3cdb8ea6e17cf1fdec699d83a1cd71b.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tommaso Merciai 2026-04-08 12:37:04 +02:00 committed by Geert Uytterhoeven
parent 1e25ddddfa
commit b6f8dd27e9

View File

@ -1609,6 +1609,34 @@ fcpvd1: fcp@164a0000 {
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
};
vspd0: vsp@16480000 {
compatible = "renesas,r9a09g047-vsp2",
"renesas,r9a07g044-vsp2";
reg = <0 0x16480000 0 0x10000>;
interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xed>,
<&cpg CPG_MOD 0xee>,
<&cpg CPG_MOD 0xef>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0xdc>;
power-domains = <&cpg>;
renesas,fcp = <&fcpvd0>;
};
vspd1: vsp@164b0000 {
compatible = "renesas,r9a09g047-vsp2",
"renesas,r9a07g044-vsp2";
reg = <0 0x164b0000 0 0x10000>;
interrupts = <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0x1a8>,
<&cpg CPG_MOD 0x1a9>,
<&cpg CPG_MOD 0x1aa>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
renesas,fcp = <&fcpvd1>;
};
};
stmmac_axi_setup: stmmac-axi-config {