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arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes

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Add fcpvd{0,1} nodes to the RZ/G3E SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://patch.msgid.link/1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tommaso Merciai 2026-04-08 12:37:03 +02:00 committed by Geert Uytterhoeven
parent 44f1ef06ce
commit 1e25ddddfa
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
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@ -1585,6 +1585,30 @@ csi2cru: endpoint@0 {
};
};
};
fcpvd0: fcp@16470000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
reg = <0 0x16470000 0 0x10000>;
clocks = <&cpg CPG_MOD 0xed>,
<&cpg CPG_MOD 0xee>,
<&cpg CPG_MOD 0xef>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0xdc>;
power-domains = <&cpg>;
};
fcpvd1: fcp@164a0000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
reg = <0 0x164a0000 0 0x10000>;
clocks = <&cpg CPG_MOD 0x1a8>,
<&cpg CPG_MOD 0x1a9>,
<&cpg CPG_MOD 0x1aa>;
clock-names = "aclk", "pclk", "vclk";
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
};
};
stmmac_axi_setup: stmmac-axi-config {