From 1e25ddddfa1e39300fa5e339275e0a469aa41899 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Wed, 8 Apr 2026 12:37:03 +0200 Subject: [PATCH] arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes Add fcpvd{0,1} nodes to the RZ/G3E SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4267b10937f3..92a3491fb7ea 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1585,6 +1585,30 @@ csi2cru: endpoint@0 { }; }; }; + + fcpvd0: fcp@16470000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0xdc>; + power-domains = <&cpg>; + }; + + fcpvd1: fcp@164a0000 { + compatible = "renesas,r9a09g047-fcpvd", + "renesas,fcpv"; + reg = <0 0x164a0000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x1a8>, + <&cpg CPG_MOD 0x1a9>, + <&cpg CPG_MOD 0x1aa>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg 0x11e>; + power-domains = <&cpg>; + }; }; stmmac_axi_setup: stmmac-axi-config {