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https://github.com/torvalds/linux.git
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arm64: tegra: Device tree changes for v6.16-rc1
Enable IOMMU support for the internal DMA controller of the QSPI controller, add aliases for the I2C controllers on Tegra234 to match hardware block names as well as the UART-D alias on Jetson TX1, and enable PWM fans on Jetson TX1 and TX2. Clean up serial port device tree nodes, add missing DMA properties, enable the GPU on Jetson TX1 and Jetson TX2. Use an extended number of address- and size-cells on Tegra186 to mirror what is done on other chip generations. Enable CEC on developer kit devices. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmgebs0ACgkQ3SOs138+ s6FaBA//fL1e+4jWhQ2NMm2HORgadgJjie+tDGZxgeDtG59fy61rlp9BYK9wCWrx cLjwFPwDDGJ48xkZYzUw3PudgflBxLrZwC2WqLEsRDFo1O3drhvHvLYPD0v+BMu7 W8+0LhHKlqjRzJM3rR9NC2ScC5bv56uu8X295iiRxYQBGTWQzuLiog+XCTuE/pF7 3IrMqS+f8rY/GybAJhF9/K4aN4QVzd0KIclC0OGccQoE6YK+vYK12avKyfg3NIeo GgfkC38j7D2pyCl9D4UWkAR44Hs2ON74Fmq8ejrYVNlZfzw48Z5onYqGFshkA0q+ SV+aXU0higipjW/YvRtf6thZVALeurtj44hJIi+FnUDjnEt+WdM/IeHqIlOzf4Xq nzkr+ZBEsqMGf2nVP42MZU3hsZ/+5NYEm+ZdqOzFWm8yjoi2y9oacqI0Ck2Kzopk S1Ap3jBZY1G7nUp1GZKC9mUyCf1JIU6EdrsFrwW9bpxhe6RjhIkNL9njqMPjFCm1 FtVfkZKVpzbzFy3Qm4Sny3/C4jcmnxaIwyGBobf6AyOpa3n/8c+V2C5tTtVSSPtb Wfo80DTmdri+pt85q5YzydS0E3S7aIn5ibCjTvf/qaEO2SK5RMnD+teTiDBN5g8n 2PaYNKCYEE61znVWoaYTv+K8Hkk5HTdsdCkB9oAjt7XnZUSZGbc= =SdCj -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmgfGDEACgkQYKtH/8kJ Uies4RAAz1KroZR/AbVCtN2H4GRSnJRriiCJwWvFcuw2eHn1VHx2nMf6sle04uy1 j2KJVPa9ebgyD4pxjpJ2iVa6397u1oYUm3URclUDsEKgCetwQ3XAzZV7fkDYwnU8 nLZ1p27/Rdb7utJHE9+ozeUo67c0ySWPOYzpLoSdzwQSfTygYLIj3ylkNY71TKZr zN3upu7JAzubMrqtVMYq/g4mlF67qZ7h0GGw8m+KMqaX8pWgSRXWk4za2xC3ez5t 7Y/QDiO//irR8D7LlDRA3ZQzpfhIU6MOkujETDpeqvChnFtOe/6KE+FTnuZspZRA n29+GFQqNW9v8CdMU9evStq7venwv2Bylc2Ou1Ic6yVUZd18J2DpI2oswLQ0oYbP QpxkrcwjeyNBxvcfXa35rUIZ1GOQRCjNyllqfianV02ZsuazcRYONDmUHqsdFUqZ Hy4W5wNl6puAPENsq87qlD+e/jvCaUx2azyOGtLjuqR9ex4FWAzvFUTvp79WCBou j0qfMqvRdx3uvtVCGJUs0q77quSE5UMU0WDctSjXNERU3j8oFr6hyKC7CNVyquZt VZsLA61wicDg2AsneiRfLzlr5JjF6kJ9Q8hw6QixsBt25uk+824rZ5y2ubyUwcLV thPTP6XoYz7Ky+qxPjsb022t0YI1cVZ7vh52DjletClpMYQe4xM= =nUi2 -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.16-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.16-rc1 Enable IOMMU support for the internal DMA controller of the QSPI controller, add aliases for the I2C controllers on Tegra234 to match hardware block names as well as the UART-D alias on Jetson TX1, and enable PWM fans on Jetson TX1 and TX2. Clean up serial port device tree nodes, add missing DMA properties, enable the GPU on Jetson TX1 and Jetson TX2. Use an extended number of address- and size-cells on Tegra186 to mirror what is done on other chip generations. Enable CEC on developer kit devices. * tag 'tegra-for-6.16-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Wire up CEC to devkits arm64: tegra: Add CEC controller on Tegra210 arm64: tegra: Add fallback CEC compatibles arm64: tegra: Add uartd serial alias for Jetson TX1 module arm64: tegra: Bump #address-cells and #size-cells on Tegra186 arm64: tegra: p2180: Explicitly enable GPU arm64: tegra: p3310: Explicitly enable GPU arm64: tegra: Add DMA properties for Tegra186 and Tegra194 UARTs arm64: tegra: Drop remaining serial clock-names and reset-names arm64: tegra: Enable PWM fan on the Jetson TX2 Devkit arm64: tegra: Enable PWM fan on the Jetson TX1 Devkit arm64: tegra: Add I2C aliases for Tegra234 arm64: tegra: Configure QSPI clocks and add DMA Link: https://lore.kernel.org/r/20250509212604.2849901-3-treding@nvidia.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
93998bc476
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@ -2394,6 +2394,12 @@ usb@3550000 {
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phy-names = "usb2-0";
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};
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cec@3960000 {
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status = "okay";
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hdmi-phandle = <&sor1>;
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};
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i2c@c250000 {
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/* carrier board ID EEPROM */
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eeprom@57 {
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@ -2409,6 +2415,10 @@ eeprom@57 {
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};
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};
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pwm@c340000 {
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status = "okay";
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};
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pcie@10003000 {
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status = "okay";
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@ -2508,6 +2518,16 @@ key-volume-up {
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};
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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pwms = <&pwm4 0 45334>;
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fan-supply = <&vdd_fan>;
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/* cooling level (0, 1, 2, 3) - pwm inverted */
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cooling-levels = <255 128 64 0>;
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#cooling-cells = <2>;
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};
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vdd_sd: regulator-vdd-sd {
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compatible = "regulator-fixed";
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regulator-name = "SD_CARD_SW_PWR";
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@ -2556,6 +2576,17 @@ vdd_usb1: regulator-vdd-usb1 {
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vin-supply = <&vdd_5v0_sys>;
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};
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vdd_fan: regulator-vdd-fan {
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compatible = "regulator-fixed";
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regulator-name = "VDD_FAN";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&exp1 4 GPIO_ACTIVE_LOW>;
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vin-supply = <&vdd_5v0_sys>;
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};
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sound {
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compatible = "nvidia,tegra186-audio-graph-card";
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status = "okay";
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@ -2621,4 +2652,88 @@ sound {
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label = "NVIDIA Jetson TX2 APE";
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};
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thermal-zones {
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cpu-thermal {
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polling-delay = <0>;
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polling-delay-passive = <500>;
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status = "okay";
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trips {
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cpu_trip_critical: critical {
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temperature = <96500>;
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hysteresis = <0>;
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type = "critical";
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};
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cpu_trip_hot: hot {
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temperature = <79000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_trip_active: active {
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temperature = <62000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_passive: passive {
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temperature = <45000>;
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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map0 {
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cooling-device = <&fan 3 3>;
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trip = <&cpu_trip_critical>;
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};
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map1 {
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cooling-device = <&fan 2 2>;
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trip = <&cpu_trip_hot>;
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};
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map2 {
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cooling-device = <&fan 1 1>;
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trip = <&cpu_trip_active>;
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};
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map3 {
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cooling-device = <&fan 0 0>;
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trip = <&cpu_trip_passive>;
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};
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};
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};
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aux-thermal {
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polling-delay = <0>;
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polling-delay-passive = <500>;
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status = "okay";
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trips {
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aux_alert0: critical {
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temperature = <90000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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gpu-thermal {
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polling-delay = <0>;
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polling-delay-passive = <500>;
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status = "okay";
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trips {
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gpu_alert0: critical {
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temperature = <99000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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};
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@ -61,6 +61,8 @@ memory-controller@2c00000 {
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};
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serial@3100000 {
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/delete-property/ dmas;
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/delete-property/ dma-names;
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status = "okay";
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};
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@ -191,6 +193,10 @@ pmc@c360000 {
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nvidia,invert-interrupt;
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};
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gpu@17000000 {
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status = "okay";
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};
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bpmp {
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i2c {
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status = "okay";
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@ -549,6 +549,8 @@ timer@3010000 {
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};
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serial@3100000 {
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/delete-property/ dmas;
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/delete-property/ dma-names;
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status = "okay";
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};
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@ -712,6 +714,12 @@ usb@3550000 {
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phy-names = "usb2-0";
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};
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cec@3960000 {
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status = "okay";
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hdmi-phandle = <&sor1>;
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};
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hsp@3c00000 {
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status = "okay";
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};
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@ -124,28 +124,28 @@ aconnect@2900000 {
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<&bpmp TEGRA186_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x02900000 0x0 0x02900000 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
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status = "disabled";
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tegra_ahub: ahub@2900800 {
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compatible = "nvidia,tegra186-ahub";
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reg = <0x02900800 0x800>;
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reg = <0x0 0x02900800 0x0 0x800>;
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clocks = <&bpmp TEGRA186_CLK_AHUB>;
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clock-names = "ahub";
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assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
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assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
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assigned-clock-rates = <81600000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x02900800 0x02900800 0x11800>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
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status = "disabled";
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tegra_i2s1: i2s@2901000 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901000 0x100>;
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reg = <0x0 0x2901000 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S1>,
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<&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -159,7 +159,7 @@ tegra_i2s1: i2s@2901000 {
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tegra_i2s2: i2s@2901100 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901100 0x100>;
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reg = <0x0 0x2901100 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S2>,
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<&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -173,7 +173,7 @@ tegra_i2s2: i2s@2901100 {
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tegra_i2s3: i2s@2901200 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901200 0x100>;
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reg = <0x0 0x2901200 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S3>,
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<&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -187,7 +187,7 @@ tegra_i2s3: i2s@2901200 {
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tegra_i2s4: i2s@2901300 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901300 0x100>;
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reg = <0x0 0x2901300 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S4>,
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<&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -201,7 +201,7 @@ tegra_i2s4: i2s@2901300 {
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tegra_i2s5: i2s@2901400 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901400 0x100>;
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reg = <0x0 0x2901400 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S5>,
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<&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -215,7 +215,7 @@ tegra_i2s5: i2s@2901400 {
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tegra_i2s6: i2s@2901500 {
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compatible = "nvidia,tegra186-i2s",
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"nvidia,tegra210-i2s";
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reg = <0x2901500 0x100>;
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reg = <0x0 0x2901500 0x0 0x100>;
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clocks = <&bpmp TEGRA186_CLK_I2S6>,
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<&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
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clock-names = "i2s", "sync_input";
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@ -229,7 +229,7 @@ tegra_i2s6: i2s@2901500 {
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tegra_sfc1: sfc@2902000 {
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compatible = "nvidia,tegra186-sfc",
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"nvidia,tegra210-sfc";
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reg = <0x2902000 0x200>;
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reg = <0x0 0x2902000 0x0 0x200>;
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sound-name-prefix = "SFC1";
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status = "disabled";
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};
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@ -237,7 +237,7 @@ tegra_sfc1: sfc@2902000 {
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tegra_sfc2: sfc@2902200 {
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compatible = "nvidia,tegra186-sfc",
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"nvidia,tegra210-sfc";
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reg = <0x2902200 0x200>;
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reg = <0x0 0x2902200 0x0 0x200>;
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sound-name-prefix = "SFC2";
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status = "disabled";
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};
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@ -245,7 +245,7 @@ tegra_sfc2: sfc@2902200 {
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tegra_sfc3: sfc@2902400 {
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compatible = "nvidia,tegra186-sfc",
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"nvidia,tegra210-sfc";
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reg = <0x2902400 0x200>;
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reg = <0x0 0x2902400 0x0 0x200>;
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sound-name-prefix = "SFC3";
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status = "disabled";
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};
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@ -253,7 +253,7 @@ tegra_sfc3: sfc@2902400 {
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tegra_sfc4: sfc@2902600 {
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compatible = "nvidia,tegra186-sfc",
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"nvidia,tegra210-sfc";
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reg = <0x2902600 0x200>;
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reg = <0x0 0x2902600 0x0 0x200>;
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sound-name-prefix = "SFC4";
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status = "disabled";
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};
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@ -261,7 +261,7 @@ tegra_sfc4: sfc@2902600 {
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tegra_amx1: amx@2903000 {
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compatible = "nvidia,tegra186-amx",
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"nvidia,tegra210-amx";
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reg = <0x2903000 0x100>;
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reg = <0x0 0x2903000 0x0 0x100>;
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sound-name-prefix = "AMX1";
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status = "disabled";
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};
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@ -269,7 +269,7 @@ tegra_amx1: amx@2903000 {
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tegra_amx2: amx@2903100 {
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compatible = "nvidia,tegra186-amx",
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"nvidia,tegra210-amx";
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reg = <0x2903100 0x100>;
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reg = <0x0 0x2903100 0x0 0x100>;
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sound-name-prefix = "AMX2";
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status = "disabled";
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};
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@ -277,7 +277,7 @@ tegra_amx2: amx@2903100 {
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tegra_amx3: amx@2903200 {
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compatible = "nvidia,tegra186-amx",
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"nvidia,tegra210-amx";
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reg = <0x2903200 0x100>;
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reg = <0x0 0x2903200 0x0 0x100>;
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||||
sound-name-prefix = "AMX3";
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||||
status = "disabled";
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||||
};
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@ -285,7 +285,7 @@ tegra_amx3: amx@2903200 {
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tegra_amx4: amx@2903300 {
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compatible = "nvidia,tegra186-amx",
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"nvidia,tegra210-amx";
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||||
reg = <0x2903300 0x100>;
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||||
reg = <0x0 0x2903300 0x0 0x100>;
|
||||
sound-name-prefix = "AMX4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -293,7 +293,7 @@ tegra_amx4: amx@2903300 {
|
|||
tegra_adx1: adx@2903800 {
|
||||
compatible = "nvidia,tegra186-adx",
|
||||
"nvidia,tegra210-adx";
|
||||
reg = <0x2903800 0x100>;
|
||||
reg = <0x0 0x2903800 0x0 0x100>;
|
||||
sound-name-prefix = "ADX1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -301,7 +301,7 @@ tegra_adx1: adx@2903800 {
|
|||
tegra_adx2: adx@2903900 {
|
||||
compatible = "nvidia,tegra186-adx",
|
||||
"nvidia,tegra210-adx";
|
||||
reg = <0x2903900 0x100>;
|
||||
reg = <0x0 0x2903900 0x0 0x100>;
|
||||
sound-name-prefix = "ADX2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -309,7 +309,7 @@ tegra_adx2: adx@2903900 {
|
|||
tegra_adx3: adx@2903a00 {
|
||||
compatible = "nvidia,tegra186-adx",
|
||||
"nvidia,tegra210-adx";
|
||||
reg = <0x2903a00 0x100>;
|
||||
reg = <0x0 0x2903a00 0x0 0x100>;
|
||||
sound-name-prefix = "ADX3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -317,14 +317,14 @@ tegra_adx3: adx@2903a00 {
|
|||
tegra_adx4: adx@2903b00 {
|
||||
compatible = "nvidia,tegra186-adx",
|
||||
"nvidia,tegra210-adx";
|
||||
reg = <0x2903b00 0x100>;
|
||||
reg = <0x0 0x2903b00 0x0 0x100>;
|
||||
sound-name-prefix = "ADX4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_dmic1: dmic@2904000 {
|
||||
compatible = "nvidia,tegra210-dmic";
|
||||
reg = <0x2904000 0x100>;
|
||||
reg = <0x0 0x2904000 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DMIC1>;
|
||||
clock-names = "dmic";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
|
||||
|
|
@ -336,7 +336,7 @@ tegra_dmic1: dmic@2904000 {
|
|||
|
||||
tegra_dmic2: dmic@2904100 {
|
||||
compatible = "nvidia,tegra210-dmic";
|
||||
reg = <0x2904100 0x100>;
|
||||
reg = <0x0 0x2904100 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DMIC2>;
|
||||
clock-names = "dmic";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
|
||||
|
|
@ -348,7 +348,7 @@ tegra_dmic2: dmic@2904100 {
|
|||
|
||||
tegra_dmic3: dmic@2904200 {
|
||||
compatible = "nvidia,tegra210-dmic";
|
||||
reg = <0x2904200 0x100>;
|
||||
reg = <0x0 0x2904200 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DMIC3>;
|
||||
clock-names = "dmic";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
|
||||
|
|
@ -360,7 +360,7 @@ tegra_dmic3: dmic@2904200 {
|
|||
|
||||
tegra_dmic4: dmic@2904300 {
|
||||
compatible = "nvidia,tegra210-dmic";
|
||||
reg = <0x2904300 0x100>;
|
||||
reg = <0x0 0x2904300 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DMIC4>;
|
||||
clock-names = "dmic";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
|
||||
|
|
@ -372,7 +372,7 @@ tegra_dmic4: dmic@2904300 {
|
|||
|
||||
tegra_dspk1: dspk@2905000 {
|
||||
compatible = "nvidia,tegra186-dspk";
|
||||
reg = <0x2905000 0x100>;
|
||||
reg = <0x0 0x2905000 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSPK1>;
|
||||
clock-names = "dspk";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
|
||||
|
|
@ -384,7 +384,7 @@ tegra_dspk1: dspk@2905000 {
|
|||
|
||||
tegra_dspk2: dspk@2905100 {
|
||||
compatible = "nvidia,tegra186-dspk";
|
||||
reg = <0x2905100 0x100>;
|
||||
reg = <0x0 0x2905100 0x0 0x100>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSPK2>;
|
||||
clock-names = "dspk";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
|
||||
|
|
@ -397,9 +397,9 @@ tegra_dspk2: dspk@2905100 {
|
|||
tegra_ope1: processing-engine@2908000 {
|
||||
compatible = "nvidia,tegra186-ope",
|
||||
"nvidia,tegra210-ope";
|
||||
reg = <0x2908000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x2908000 0x0 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
sound-name-prefix = "OPE1";
|
||||
status = "disabled";
|
||||
|
|
@ -407,20 +407,20 @@ tegra_ope1: processing-engine@2908000 {
|
|||
equalizer@2908100 {
|
||||
compatible = "nvidia,tegra186-peq",
|
||||
"nvidia,tegra210-peq";
|
||||
reg = <0x2908100 0x100>;
|
||||
reg = <0x0 0x2908100 0x0 0x100>;
|
||||
};
|
||||
|
||||
dynamic-range-compressor@2908200 {
|
||||
compatible = "nvidia,tegra186-mbdrc",
|
||||
"nvidia,tegra210-mbdrc";
|
||||
reg = <0x2908200 0x200>;
|
||||
reg = <0x0 0x2908200 0x0 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
tegra_mvc1: mvc@290a000 {
|
||||
compatible = "nvidia,tegra186-mvc",
|
||||
"nvidia,tegra210-mvc";
|
||||
reg = <0x290a000 0x200>;
|
||||
reg = <0x0 0x290a000 0x0 0x200>;
|
||||
sound-name-prefix = "MVC1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -428,7 +428,7 @@ tegra_mvc1: mvc@290a000 {
|
|||
tegra_mvc2: mvc@290a200 {
|
||||
compatible = "nvidia,tegra186-mvc",
|
||||
"nvidia,tegra210-mvc";
|
||||
reg = <0x290a200 0x200>;
|
||||
reg = <0x0 0x290a200 0x0 0x200>;
|
||||
sound-name-prefix = "MVC2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -436,14 +436,14 @@ tegra_mvc2: mvc@290a200 {
|
|||
tegra_amixer: amixer@290bb00 {
|
||||
compatible = "nvidia,tegra186-amixer",
|
||||
"nvidia,tegra210-amixer";
|
||||
reg = <0x290bb00 0x800>;
|
||||
reg = <0x0 0x290bb00 0x0 0x800>;
|
||||
sound-name-prefix = "MIXER1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_admaif: admaif@290f000 {
|
||||
compatible = "nvidia,tegra186-admaif";
|
||||
reg = <0x0290f000 0x1000>;
|
||||
reg = <0x0 0x0290f000 0x0 0x1000>;
|
||||
dmas = <&adma 1>, <&adma 1>,
|
||||
<&adma 2>, <&adma 2>,
|
||||
<&adma 3>, <&adma 3>,
|
||||
|
|
@ -489,7 +489,7 @@ tegra_admaif: admaif@290f000 {
|
|||
|
||||
tegra_asrc: asrc@2910000 {
|
||||
compatible = "nvidia,tegra186-asrc";
|
||||
reg = <0x2910000 0x2000>;
|
||||
reg = <0x0 0x2910000 0x0 0x2000>;
|
||||
sound-name-prefix = "ASRC1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -497,7 +497,7 @@ tegra_asrc: asrc@2910000 {
|
|||
|
||||
adma: dma-controller@2930000 {
|
||||
compatible = "nvidia,tegra186-adma";
|
||||
reg = <0x02930000 0x20000>;
|
||||
reg = <0x0 0x02930000 0x0 0x20000>;
|
||||
interrupt-parent = <&agic>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -542,8 +542,8 @@ agic: interrupt-controller@2a40000 {
|
|||
"nvidia,tegra210-agic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x02a41000 0x1000>,
|
||||
<0x02a42000 0x2000>;
|
||||
reg = <0x0 0x02a41000 0x0 0x1000>,
|
||||
<0x0 0x02a42000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 145
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&bpmp TEGRA186_CLK_APE>;
|
||||
|
|
@ -612,6 +612,8 @@ uarta: serial@3100000 {
|
|||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTA>;
|
||||
resets = <&bpmp TEGRA186_RESET_UARTA>;
|
||||
dmas = <&gpcdma 8>, <&gpcdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -621,9 +623,9 @@ uartb: serial@3110000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTB>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTB>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 9>, <&gpcdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -633,9 +635,9 @@ uartd: serial@3130000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTD>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTD>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 19>, <&gpcdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -645,9 +647,9 @@ uarte: serial@3140000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTE>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTE>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 20>, <&gpcdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -657,9 +659,9 @@ uartf: serial@3150000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTF>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTF>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 12>, <&gpcdma 12>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1183,7 +1185,7 @@ gic: interrupt-controller@3881000 {
|
|||
};
|
||||
|
||||
cec@3960000 {
|
||||
compatible = "nvidia,tegra186-cec";
|
||||
compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec";
|
||||
reg = <0x0 0x03960000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_CEC>;
|
||||
|
|
@ -1236,9 +1238,9 @@ uartc: serial@c280000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTC>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTC>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 3>, <&gpcdma 3>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1248,9 +1250,9 @@ uartg: serial@c290000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_UARTG>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA186_RESET_UARTG>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 2>, <&gpcdma 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1511,10 +1513,10 @@ host1x@13e00000 {
|
|||
resets = <&bpmp TEGRA186_RESET_HOST1X>;
|
||||
reset-names = "host1x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x15000000 0x0 0x15000000 0x01000000>;
|
||||
ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>;
|
||||
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
|
||||
interconnect-names = "dma-mem";
|
||||
|
|
@ -1533,7 +1535,7 @@ host1x@13e00000 {
|
|||
|
||||
dpaux1: dpaux@15040000 {
|
||||
compatible = "nvidia,tegra186-dpaux";
|
||||
reg = <0x15040000 0x10000>;
|
||||
reg = <0x0 0x15040000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
|
||||
<&bpmp TEGRA186_CLK_PLLDP>;
|
||||
|
|
@ -1567,7 +1569,7 @@ i2c-bus {
|
|||
|
||||
display-hub@15200000 {
|
||||
compatible = "nvidia,tegra186-display";
|
||||
reg = <0x15200000 0x00040000>;
|
||||
reg = <0x0 0x15200000 0x0 0x00040000>;
|
||||
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
|
||||
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
|
||||
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
|
||||
|
|
@ -1585,14 +1587,14 @@ display-hub@15200000 {
|
|||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x15200000 0x15200000 0x40000>;
|
||||
ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
|
||||
|
||||
display@15200000 {
|
||||
compatible = "nvidia,tegra186-dc";
|
||||
reg = <0x15200000 0x10000>;
|
||||
reg = <0x0 0x15200000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
|
||||
clock-names = "dc";
|
||||
|
|
@ -1611,7 +1613,7 @@ display@15200000 {
|
|||
|
||||
display@15210000 {
|
||||
compatible = "nvidia,tegra186-dc";
|
||||
reg = <0x15210000 0x10000>;
|
||||
reg = <0x0 0x15210000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
|
||||
clock-names = "dc";
|
||||
|
|
@ -1630,7 +1632,7 @@ display@15210000 {
|
|||
|
||||
display@15220000 {
|
||||
compatible = "nvidia,tegra186-dc";
|
||||
reg = <0x15220000 0x10000>;
|
||||
reg = <0x0 0x15220000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
|
||||
clock-names = "dc";
|
||||
|
|
@ -1650,7 +1652,7 @@ display@15220000 {
|
|||
|
||||
dsia: dsi@15300000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15300000 0x10000>;
|
||||
reg = <0x0 0x15300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSI>,
|
||||
<&bpmp TEGRA186_CLK_DSIA_LP>,
|
||||
|
|
@ -1665,7 +1667,7 @@ dsia: dsi@15300000 {
|
|||
|
||||
vic@15340000 {
|
||||
compatible = "nvidia,tegra186-vic";
|
||||
reg = <0x15340000 0x40000>;
|
||||
reg = <0x0 0x15340000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_VIC>;
|
||||
clock-names = "vic";
|
||||
|
|
@ -1681,7 +1683,7 @@ vic@15340000 {
|
|||
|
||||
nvjpg@15380000 {
|
||||
compatible = "nvidia,tegra186-nvjpg";
|
||||
reg = <0x15380000 0x40000>;
|
||||
reg = <0x0 0x15380000 0x0 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
|
||||
clock-names = "nvjpg";
|
||||
resets = <&bpmp TEGRA186_RESET_NVJPG>;
|
||||
|
|
@ -1696,7 +1698,7 @@ nvjpg@15380000 {
|
|||
|
||||
dsib: dsi@15400000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15400000 0x10000>;
|
||||
reg = <0x0 0x15400000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSIB>,
|
||||
<&bpmp TEGRA186_CLK_DSIB_LP>,
|
||||
|
|
@ -1711,7 +1713,7 @@ dsib: dsi@15400000 {
|
|||
|
||||
nvdec@15480000 {
|
||||
compatible = "nvidia,tegra186-nvdec";
|
||||
reg = <0x15480000 0x40000>;
|
||||
reg = <0x0 0x15480000 0x0 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
|
||||
clock-names = "nvdec";
|
||||
resets = <&bpmp TEGRA186_RESET_NVDEC>;
|
||||
|
|
@ -1727,7 +1729,7 @@ nvdec@15480000 {
|
|||
|
||||
nvenc@154c0000 {
|
||||
compatible = "nvidia,tegra186-nvenc";
|
||||
reg = <0x154c0000 0x40000>;
|
||||
reg = <0x0 0x154c0000 0x0 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVENC>;
|
||||
clock-names = "nvenc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVENC>;
|
||||
|
|
@ -1742,7 +1744,7 @@ nvenc@154c0000 {
|
|||
|
||||
sor0: sor@15540000 {
|
||||
compatible = "nvidia,tegra186-sor";
|
||||
reg = <0x15540000 0x10000>;
|
||||
reg = <0x0 0x15540000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SOR0>,
|
||||
<&bpmp TEGRA186_CLK_SOR0_OUT>,
|
||||
|
|
@ -1766,7 +1768,7 @@ sor0: sor@15540000 {
|
|||
|
||||
sor1: sor@15580000 {
|
||||
compatible = "nvidia,tegra186-sor";
|
||||
reg = <0x15580000 0x10000>;
|
||||
reg = <0x0 0x15580000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SOR1>,
|
||||
<&bpmp TEGRA186_CLK_SOR1_OUT>,
|
||||
|
|
@ -1790,7 +1792,7 @@ sor1: sor@15580000 {
|
|||
|
||||
dpaux: dpaux@155c0000 {
|
||||
compatible = "nvidia,tegra186-dpaux";
|
||||
reg = <0x155c0000 0x10000>;
|
||||
reg = <0x0 0x155c0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DPAUX>,
|
||||
<&bpmp TEGRA186_CLK_PLLDP>;
|
||||
|
|
@ -1824,7 +1826,7 @@ i2c-bus {
|
|||
|
||||
padctl@15880000 {
|
||||
compatible = "nvidia,tegra186-dsi-padctl";
|
||||
reg = <0x15880000 0x10000>;
|
||||
reg = <0x0 0x15880000 0x0 0x10000>;
|
||||
resets = <&bpmp TEGRA186_RESET_DSI>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
|
|
@ -1832,7 +1834,7 @@ padctl@15880000 {
|
|||
|
||||
dsic: dsi@15900000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15900000 0x10000>;
|
||||
reg = <0x0 0x15900000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSIC>,
|
||||
<&bpmp TEGRA186_CLK_DSIC_LP>,
|
||||
|
|
@ -1847,7 +1849,7 @@ dsic: dsi@15900000 {
|
|||
|
||||
dsid: dsi@15940000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15940000 0x10000>;
|
||||
reg = <0x0 0x15940000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSID>,
|
||||
<&bpmp TEGRA186_CLK_DSID_LP>,
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@ input@2 {
|
|||
};
|
||||
|
||||
serial@3110000 {
|
||||
/delete-property/ dmas;
|
||||
/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2121,6 +2121,12 @@ usb@3610000 {
|
|||
phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
|
||||
};
|
||||
|
||||
cec@3960000 {
|
||||
status = "okay";
|
||||
|
||||
hdmi-phandle = <&sor2>;
|
||||
};
|
||||
|
||||
i2c@c240000 {
|
||||
typec@8 {
|
||||
compatible = "cypress,cypd4226";
|
||||
|
|
|
|||
|
|
@ -2174,6 +2174,12 @@ usb@3610000 {
|
|||
phy-names = "usb2-1", "usb2-2", "usb3-2";
|
||||
};
|
||||
|
||||
cec@3960000 {
|
||||
status = "okay";
|
||||
|
||||
hdmi-phandle = <&sor1>;
|
||||
};
|
||||
|
||||
host1x@13e00000 {
|
||||
display-hub@15200000 {
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -78,6 +78,8 @@ input@2 {
|
|||
};
|
||||
|
||||
serial@3100000 {
|
||||
/delete-property/ dmas;
|
||||
/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -747,6 +747,8 @@ uarta: serial@3100000 {
|
|||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTA>;
|
||||
resets = <&bpmp TEGRA194_RESET_UARTA>;
|
||||
dmas = <&gpcdma 8>, <&gpcdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -757,6 +759,8 @@ uartb: serial@3110000 {
|
|||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTB>;
|
||||
resets = <&bpmp TEGRA194_RESET_UARTB>;
|
||||
dmas = <&gpcdma 9>, <&gpcdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -766,9 +770,9 @@ uartd: serial@3130000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTD>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTD>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 19>, <&gpcdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -778,9 +782,9 @@ uarte: serial@3140000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTE>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTE>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 20>, <&gpcdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -790,9 +794,9 @@ uartf: serial@3150000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTF>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTF>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 12>, <&gpcdma 12>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -817,9 +821,9 @@ uarth: serial@3170000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTH>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTH>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 13>, <&gpcdma 13>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1339,7 +1343,7 @@ gic: interrupt-controller@3881000 {
|
|||
};
|
||||
|
||||
cec@3960000 {
|
||||
compatible = "nvidia,tegra194-cec";
|
||||
compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec";
|
||||
reg = <0x0 0x03960000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_CEC>;
|
||||
|
|
@ -1616,9 +1620,9 @@ uartc: serial@c280000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTC>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTC>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 3>, <&gpcdma 3>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1628,9 +1632,9 @@ uartg: serial@c290000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_UARTG>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp TEGRA194_RESET_UARTG>;
|
||||
reset-names = "serial";
|
||||
dmas = <&gpcdma 2>, <&gpcdma 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ aliases {
|
|||
rtc0 = "/i2c@7000d000/pmic@3c";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -24,6 +25,7 @@ memory@80000000 {
|
|||
|
||||
gpu@57000000 {
|
||||
vdd-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* debug port */
|
||||
|
|
|
|||
|
|
@ -90,6 +90,12 @@ eeprom@57 {
|
|||
};
|
||||
};
|
||||
|
||||
cec@70015000 {
|
||||
status = "okay";
|
||||
|
||||
hdmi-phandle = <&sor1>;
|
||||
};
|
||||
|
||||
clock@70110000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -1623,6 +1623,18 @@ key-volume-up {
|
|||
};
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&pwm 3 45334>;
|
||||
fan-supply = <&vdd_fan>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(K, 7) IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
/* cooling level (0, 1, 2, 3) - pwm inverted */
|
||||
cooling-levels = <255 128 64 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
vdd_sys_mux: regulator-vdd-sys-mux {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_SYS_MUX";
|
||||
|
|
@ -1778,4 +1790,67 @@ vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg {
|
|||
enable-active-high;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
vdd_fan: regulator-vdd-fan {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_FAN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&exp1 4 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
|
||||
regulator-enable-ramp-delay = <284>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
trips {
|
||||
cpu_trip_critical: critical {
|
||||
temperature = <96500>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu_trip_hot: hot {
|
||||
temperature = <70000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
cpu_trip_active: active {
|
||||
temperature = <50000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_passive: passive {
|
||||
temperature = <30000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
cooling-device = <&fan 3 3>;
|
||||
trip = <&cpu_trip_critical>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
cooling-device = <&fan 2 2>;
|
||||
trip = <&cpu_trip_hot>;
|
||||
};
|
||||
|
||||
map2 {
|
||||
cooling-device = <&fan 1 1>;
|
||||
trip = <&cpu_trip_active>;
|
||||
};
|
||||
|
||||
map3 {
|
||||
cooling-device = <&fan 0 0>;
|
||||
trip = <&cpu_trip_passive>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -419,6 +419,12 @@ pmc@7000e400 {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
cec@70015000 {
|
||||
status = "okay";
|
||||
|
||||
hdmi-phandle = <&sor1>;
|
||||
};
|
||||
|
||||
hda@70030000 {
|
||||
nvidia,model = "NVIDIA Jetson Nano HDA";
|
||||
|
||||
|
|
|
|||
|
|
@ -959,6 +959,15 @@ fuse@7000f800 {
|
|||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
cec@70015000 {
|
||||
compatible = "nvidia,tegra210-cec";
|
||||
reg = <0x0 0x070015000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_CEC>;
|
||||
clock-names = "cec";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mc: memory-controller@70019000 {
|
||||
compatible = "nvidia,tegra210-mc";
|
||||
reg = <0x0 0x70019000 0x0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -16,6 +16,18 @@ / {
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &gen1_i2c;
|
||||
i2c1 = &gen2_i2c;
|
||||
i2c2 = &cam_i2c;
|
||||
i2c3 = &dp_aux_ch1_i2c;
|
||||
i2c4 = &bpmp_i2c;
|
||||
i2c5 = &dp_aux_ch0_i2c;
|
||||
i2c6 = &dp_aux_ch2_i2c;
|
||||
i2c7 = &gen8_i2c;
|
||||
i2c8 = &dp_aux_ch3_i2c;
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
|
|
@ -2948,6 +2960,11 @@ spi@3270000 {
|
|||
<&bpmp TEGRA234_CLK_QSPI0_PM>;
|
||||
clock-names = "qspi", "qspi_out";
|
||||
resets = <&bpmp TEGRA234_RESET_QSPI0>;
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
|
||||
<&bpmp TEGRA234_CLK_QSPI0_PM>;
|
||||
assigned-clock-rates = <199999999 99999999>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -3031,6 +3048,11 @@ spi@3300000 {
|
|||
<&bpmp TEGRA234_CLK_QSPI1_PM>;
|
||||
clock-names = "qspi", "qspi_out";
|
||||
resets = <&bpmp TEGRA234_RESET_QSPI1>;
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>;
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
|
||||
<&bpmp TEGRA234_CLK_QSPI1_PM>;
|
||||
assigned-clock-rates = <199999999 99999999>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user