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SoCFPGA DTS updates for v7.2

Browse Source 
- dt-bindings updates:
 	- Document compatible for Agilex5 socdk debug daughter card
 	- Document compatible for Agilex7-M devkit
 
 - Add support for Agilex7-M devkit
 - Remove reg property in the PMU on 32-bit SoCFPGA
 - Set i3c alias on Agilex3 and Agilex5
 - Update data-width of DMA controller on Agilex5
 - Set phy-mode to rgmii on Agilex5
 - Increase the JFFS2 rootfs partition on the Arria10 NAND SoCDK
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmobVx4ACgkQGZQEC4Gj
 KPSENQ/8DPUlUWpVEpAeiphYoTelIJj/yPHlgsKsrz8Ux6tclVgx87O9U6+ASjF7
 c09SZ/jUYTlhMJT+t86H6IV+xsgrA83T//U0FlmNrlb/8EeO4Z7Z3b3ycwqeQDBC
 t0afXeOrzG4HF6+PrnrQJ9/KwRbueBG8MwKdSuRTKII6ZwLYf3Tr/yMhPV6h6BEN
 LOdysaf+BCI3vgtAoPIjCJRXBQrOb+Cbx5YLNzJF1ObFznBM2kdN6dceCFcQjJHS
 xjJBZjXg1hAGSXFF1q5UKX3LkKY/ia+EPAqEDh1dqZktK/3+twibz/eUX7DpHlg+
 QFAFU0YoNUibBOi7gd98AN5zfwRD0dViUGsz7miIVVmZe1qpPBQLm46jhqN0/WNp
 8D/v8iaHkMemr01updrVl6CT0rEFXJBDuMpLr8qhjwKH/FwvFaLCgbCR4OGOFHTz
 cQtq7EQTjwr+vRTpyYK5JSG+nQkI+3EXcXYOFSGpyqZX7YG0aKyCp/kiJDyIpHiH
 LdHTNFoREARiDv/OdEvh38ozGZy7NDRM+MMzP1KzH58xIi9tNWdCIwJitpJjdatP
 wytSQnTu4dKPPl/I6khn28fMCPE4Ambeh2YpfpEEPeWlIAnIkBljC0hbKhyJA+X7
 wg84MxcCnBURQu28XD1U/Tsq5w0UydrsIRpJUKHuYazgqFGJFB4=
 =fuTI
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_updates_for_v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v7.2
- dt-bindings updates:
	- Document compatible for Agilex5 socdk debug daughter card
	- Document compatible for Agilex7-M devkit

- Add support for Agilex7-M devkit
- Remove reg property in the PMU on 32-bit SoCFPGA
- Set i3c alias on Agilex3 and Agilex5
- Update data-width of DMA controller on Agilex5
- Set phy-mode to rgmii on Agilex5
- Increase the JFFS2 rootfs partition on the Arria10 NAND SoCDK

* tag 'socfpga_dts_updates_for_v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: arria10: Increase JFFS2 rootfs partition size
  dt-bindings: altera: add compatible for agilex5 socdk debug daughter card
  arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay
  arm64: dts: socfpga: agilex5: update data-width for dmac
  arm64: dts: socfpga: agilex3: set alias for i3c controller
  arm64: dts: socfpga: agilex5: set alias for i3c controllers
  ARM: dts: socfpga: remove the reg property in the pmu
  arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit
  dt-bindings: arm: altera: document the Agilex7-M devkit

Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij 2026-06-04 13:50:09 +02:00
commit 7b93c5b058
12 changed files with 131 additions and 14 deletions
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7
Documentation/devicetree/bindings/arm/altera.yaml
View File

@ -111,10 +111,17 @@ properties:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-013b
- intel,socfpga-agilex5-socdk-debug
- intel,socfpga-agilex5-socdk-modular
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
- description: Agilex7m boards
items:
- enum:
- altr,socfpga-agilex7m-socdk
- const: altr,socfpga-agilex7m
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt

4
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
View File

@ -37,13 +37,11 @@ cpu1: cpu@1 {
};
};
pmu: pmu@ff111000 {
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&intc>;
interrupts = <0 176 4>, <0 177 4>;
interrupt-affinity = <&cpu0>, <&cpu1>;
reg = <0xff111000 0x1000>,
<0xff113000 0x1000>;
};
intc: interrupt-controller@fffed000 {

4
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
View File

@ -29,13 +29,11 @@ cpu1: cpu@1 {
};
};
pmu: pmu@ff111000 {
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&intc>;
interrupts = <0 124 4>, <0 125 4>;
interrupt-affinity = <&cpu0>, <&cpu1>;
reg = <0xff111000 0x1000>,
<0xff113000 0x1000>;
};
intc: interrupt-controller@ffffd000 {

4
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts
View File

@ -18,9 +18,9 @@ partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x02500000>;
};
partition@1c00000 {
partition@2500000 {
label = "Root Filesystem - JFFS2";
reg = <0x02500000 0x05500000>;
reg = <0x02500000 0x3db00000>;
};
};
};

1
arch/arm64/boot/dts/intel/Makefile
View File

@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex5_socdk_013b.dtb \
socfpga_agilex5_socdk_modular.dtb \
socfpga_agilex5_socdk_nand.dtb \
socfpga_agilex7m_socdk.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

2
arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
View File

@ -12,6 +12,8 @@ / {
aliases {
serial0 = &uart0;
ethernet2 = &gmac2;
i3c0 = &i3c0;
i3c1 = &i3c1;
};
chosen {

4
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
View File

@ -343,7 +343,7 @@ dmac0: dma-controller@0 {
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,data-width = <3>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
@ -362,7 +362,7 @@ dmac1: dma-controller@10000 {
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,data-width = <3>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;

4
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
View File

@ -13,6 +13,8 @@ aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
i3c0 = &i3c0;
i3c1 = &i3c1;
};
chosen {
@ -42,7 +44,7 @@ &gpio0 {
&gmac2 {
status = "okay";
phy-mode = "rgmii-id";
phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;

4
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
View File

@ -11,6 +11,8 @@ / {
aliases {
serial0 = &uart0;
ethernet2 = &gmac2;
i3c0 = &i3c0;
i3c1 = &i3c1;
};
chosen {
@ -41,7 +43,7 @@ memory@80000000 {
&gmac2 {
status = "okay";
phy-mode = "rgmii-id";
phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;

4
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
View File

@ -11,6 +11,8 @@ / {
aliases {
serial0 = &uart0;
ethernet2 = &gmac2;
i3c0 = &i3c0;
i3c1 = &i3c1;
};
chosen {
@ -44,7 +46,7 @@ &gpio1 {
&gmac2 {
status = "okay";
phy-mode = "rgmii-id";
phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;

4
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
View File

@ -11,6 +11,8 @@ / {
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
i3c0 = &i3c0;
i3c1 = &i3c1;
};
chosen {
@ -39,7 +41,7 @@ memory@80000000 {
&gmac0 {
status = "okay";
phy-mode = "rgmii-id";
phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac0_phy0>;
max-frame-size = <9000>;

103
arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts Normal file
View File

@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2026 Altera Corporation
#include "socfpga_agilex.dtsi"
/ {
model = "Altera SoCFPGA Agilex7-M SoCDK";
compatible = "altr,socfpga-agilex7m-socdk",
"altr,socfpga-agilex7m";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
led-1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
led-2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0x80000000 0 0>;
};
};
&gpio1 {
status = "okay";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@4 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};