From 6a1405b315166dd282a78025e0ea2fc9a9a7b619 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 19 Apr 2026 18:24:15 -0500 Subject: [PATCH 1/9] dt-bindings: arm: altera: document the Agilex7-M devkit The Agilex7-M is a rebranded version of the original Agilex SoC. The Agilex7-M SoC has the same core peripherals as the Agilex device. This change is to document the Agilex7m devkit which has the Agilex7-M device. The Agilex7-M SoC supports DDR4, DDR5, LPDDR5, PCIE 5.0(x16), but not QSPI. Also, now that Altera has separated from Intel, use the "altr" company prefix. Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 206686f3eebc..4b096e52243e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -115,6 +115,12 @@ properties: - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex7m boards + items: + - enum: + - altr,socfpga-agilex7m-socdk + - const: altr,socfpga-agilex7m + - description: SoCFPGA VT items: - const: altr,socfpga-vt From 66764673e09b3b9c0e9dc1f785ac9cb7b0e0183a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 19 Apr 2026 18:24:16 -0500 Subject: [PATCH 2/9] arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit The Agilex7-M devkit contains an Agilex7M SoC, which is a newly branded version of the original Agilex SoC. The Agilex7M core peripherals are identical to the Agilex SoC. We can re-use the socfpga_agilex.dtsi for this devkit. The Agilex7-M devkit supports PCIE 5.0(x16), DDR4, DDR5, LPDDR5 and does not have QSPI. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex7m_socdk.dts | 103 ++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 33fcc55d0cb9..088a03b89c99 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex7m_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts new file mode 100644 index 000000000000..c1f270b9334c --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7m_socdk.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2026 Altera Corporation + +#include "socfpga_agilex.dtsi" + +/ { + model = "Altera SoCFPGA Agilex7-M SoCDK"; + compatible = "altr,socfpga-agilex7m-socdk", + "altr,socfpga-agilex7m"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led-0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; From b5a0814a2cbb91e9376937f6b7de6ddff5eae14a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 23 Apr 2026 12:48:47 -0500 Subject: [PATCH 3/9] ARM: dts: socfpga: remove the reg property in the pmu The Cortex-A9 PMU accesses the hardware via system coprocessor registers, not memory-mapped I/O. The driver does not parse or use a 'reg' property from the device tree, so we can remove the reg from the DTS. This change fixes this dtbs_check warning: (arm,cortex-a9-pmu): 'reg' does not match any of the regexes Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 4 +--- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 5dc8d33e8ad7..98cb4cad2a10 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -37,13 +37,11 @@ cpu1: cpu@1 { }; }; - pmu: pmu@ff111000 { + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&intc>; interrupts = <0 176 4>, <0 177 4>; interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; }; intc: interrupt-controller@fffed000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index a53a94678df2..ba4c0ca89788 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -29,13 +29,11 @@ cpu1: cpu@1 { }; }; - pmu: pmu@ff111000 { + pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&intc>; interrupts = <0 124 4>, <0 125 4>; interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; }; intc: interrupt-controller@ffffd000 { From 5b80089b47f8307c2265357e4d3ae90cb40ac0d6 Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Tue, 5 May 2026 13:15:16 +0800 Subject: [PATCH 4/9] arm64: dts: socfpga: agilex5: set alias for i3c controllers Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main master and a secondary master. Setting the alias for both i3c controllers to prevent bus id contention when both controllers are enabled which results in driver probe failures. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 262bb3e8e5c7..dae0db9f8819 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -13,6 +13,8 @@ aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index f71e1280c778..86137380df04 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index 1831402d8808..e728cedb4cbd 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts index ec4541d44c9b..21faa47681fa 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -11,6 +11,8 @@ / { aliases { serial0 = &uart0; ethernet0 = &gmac0; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { From 49a2a555a14920a1c9e3175c6ebb7d65eb06cf34 Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Tue, 5 May 2026 13:15:17 +0800 Subject: [PATCH 5/9] arm64: dts: socfpga: agilex3: set alias for i3c controller Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary master. Setting the alias for both i3c controllers to prevent bus id contention when both controllers are enabled which results in driver probe failures. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts index 14b299f19f3a..25e17df0cbdb 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -12,6 +12,8 @@ / { aliases { serial0 = &uart0; ethernet2 = &gmac2; + i3c0 = &i3c0; + i3c1 = &i3c1; }; chosen { From 90d083b05f057c3107a7344f652d3a1ae1a2536e Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Wed, 6 May 2026 14:21:49 +0800 Subject: [PATCH 6/9] arm64: dts: socfpga: agilex5: update data-width for dmac Update data-width property for dmac to 3 which is 64 bits to match value configured in the hardware register. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 02e62d954e94..b06c6d5d60ee 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -343,7 +343,7 @@ dmac0: dma-controller@0 { #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <1>; - snps,data-width = <2>; + snps,data-width = <3>; snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; @@ -362,7 +362,7 @@ dmac1: dma-controller@10000 { #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <1>; - snps,data-width = <2>; + snps,data-width = <3>; snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; From c5637e5ceb4b4bbe80fceec77f5e663c4ff7b508 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 6 May 2026 20:32:02 -0700 Subject: [PATCH 7/9] arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay The Agilex5 SoC provides RGMII TX/RX clock delay compensation through its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the MAC driver to additionally insert internal TX/RX delays, resulting in double delay being applied and causing Ethernet link timing issues. Change phy-mode to "rgmii" across all Agilex5 device tree files to reflect that the clock delay is already handled by the hardware and no additional software-inserted delay is required. Add an inline comment to satisfy checkpatch and document the hardware-provided delay. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index dae0db9f8819..57d3c5807c65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -44,7 +44,7 @@ &gpio0 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 86137380df04..82cd4115746e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -43,7 +43,7 @@ memory@80000000 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index e728cedb4cbd..4d32b6928ce1 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -46,7 +46,7 @@ &gpio1 { &gmac2 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac2_phy0>; max-frame-size = <9000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts index 21faa47681fa..81443096cf99 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -41,7 +41,7 @@ memory@80000000 { &gmac0 { status = "okay"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */ phy-handle = <&emac0_phy0>; max-frame-size = <9000>; From 0ce60cd362a0a01bd439e85bc93e6a61434e63da Mon Sep 17 00:00:00 2001 From: Adrian Ng Ho Yin Date: Fri, 8 May 2026 18:57:47 +0800 Subject: [PATCH 8/9] dt-bindings: altera: add compatible for agilex5 socdk debug daughter card Agilex5 devkit supports a debug daughter card that inherits the configurations from socdk but disables gpio0 and gmac2 and enables gmac0 and spi0. Signed-off-by: Adrian Ng Ho Yin Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 4b096e52243e..0b418d9d60db 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -111,6 +111,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-debug - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 From 7557d67a6057362a65ad03a03cbefe7f03523003 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Mon, 11 May 2026 01:15:19 -0700 Subject: [PATCH 9/9] ARM: dts: socfpga: arria10: Increase JFFS2 rootfs partition size Increase the JFFS2 partition size to support larger root filesystem. Also fix the partition label to match the actual start address. Signed-off-by: Niravkumar L Rabara Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- .../arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts index a662df319a84..5f9b98b0b393 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts @@ -18,9 +18,9 @@ partition@0 { label = "Boot and fpga data"; reg = <0x0 0x02500000>; }; - partition@1c00000 { + partition@2500000 { label = "Root Filesystem - JFFS2"; - reg = <0x02500000 0x05500000>; + reg = <0x02500000 0x3db00000>; }; }; };