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Merge branches 'clk-allwinner', 'clk-amlogic', 'clk-imx', 'clk-microchip' and 'clk-qcom' into clk-next

Browse Source 
* clk-allwinner:
  clk: sunxi-ng: ccu_common: Use readl_relaxed_poll_timeout_atomic for PLL lock
  clk: sunxi-ng: sun55i-a523-r-ccu: Use P-only clocks for timers
  clk: sunxi-ng: sun55i-a523-ccu: Use P-only clocks for high-speed timers
  clk: sunxi-ng: sun55i-a523-ccu: Use M-only clocks for MBUS, IOMMU and DRAM
  clk: sunxi-ng: div: Add feature support to M clock macro

* clk-amlogic:
  clk: meson: t7: don't mark sys_ampipe_nand as critical
  dt-bindings: clock: Add Amlogic A9 SCMI clock controller
  clk: meson: t7: keep the memory fabric clocks running

* clk-imx:
  clk: imx: Fix clock reference leak in imx_obtain_fixed_clock_hw()
  clk: imx: Fix clock reference leak in imx_get_clk_hw_by_name()
  clk: imx: fracn-gppll: Add 350 MHz support
  clk: imx: composite-93: return timeout from gate enable

* clk-microchip:
  clk: at91: main: Drop unneeded cast in at91_clk_register_main_osc()

* clk-qcom: (156 commits)
  clk: qcom: Add support for camera clock controller on Maili
  clk: qcom: ipq9650: Use icc-clk for enabling NoC related clocks
  clk: qcom: ipq5210: add 24MHz rate for USB UTMI clock
  clk: qcom: ipq5332: add 24MHz rate for USB UTMI clock
  clk: qcom: ipq5018: add 24MHz rate for USB UTMI clock
  clk: qcom: Fix camera rivian PLL configuration settings
  clk: qcom: videocc-sm8350: Use common probe handling for always-on clocks
  clk: qcom: videocc-sm8250: Use common probe handling for always-on clocks
  clk: qcom: videocc-sm7150: Use common probe handling for always-on clocks
  clk: qcom: videocc-sm6350: Use common probe handling for always-on clocks
  clk: qcom: videocc-sa8775p: Use common probe handling for always-on clocks
  clk: qcom: lpasscorecc-sc7180: Use common probe handling for always-on clocks
  clk: qcom: gpucc-x1p42100: Use common probe handling for always-on clocks
  clk: qcom: gpucc-x1e80100: Use common probe handling for always-on clocks
  clk: qcom: gpucc-sm8550: Use common probe handling for always-on clocks
  clk: qcom: gpucc-sm4450: Use common probe handling for always-on clocks
  clk: qcom: gpucc-sc8280xp: Use common probe handling for always-on clocks
  clk: qcom: gpucc-sc7280: Use common probe handling for always-on clocks
  clk: qcom: gpucc-sar2130p: Use common probe handling for always-on clocks
  clk: qcom: gcc-x1e80100: Use common clock controller probe data
  ...
This commit is contained in:
Brian Masney 2026-10-26 19:48:44 -04:00
commit 79f5eab7ec
166 changed files with 19723 additions and 1662 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
Documentation/devicetree/bindings/clock/qcom,gcc-msm8952.yaml Normal file
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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8952.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8952
maintainers:
- Muzaffer Kadir <muzafferkadir@mainlining.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8952.
See also:
include/dt-bindings/clock/qcom,gcc-msm8952.h
properties:
compatible:
enum:
- qcom,gcc-msm8952
clocks:
items:
- description: XO source
- description: Always-on XO source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8952.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@1800000 {
compatible = "qcom,gcc-msm8952";
reg = <0x01800000 0x80000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>;
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

6
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
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@ -31,11 +31,13 @@ properties:
maxItems: 5
power-domains:
maxItems: 1
items:
- description: CX power domain
required:
- compatible
- '#power-domain-cells'
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
@ -85,6 +87,7 @@ examples:
# Example for GCC for SDM845:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
@ -94,6 +97,7 @@ examples:
<&pcie0_lane>,
<&pcie1_lane>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
power-domains = <&rpmhpd SDM845_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
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@ -31,10 +31,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -45,12 +50,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm6350";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
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@ -30,10 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -44,12 +49,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8150";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
power-domains = <&rpmhpd SM8150_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
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@ -32,10 +32,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -46,6 +51,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8250";
reg = <0x00100000 0x1f0000>;
@ -53,6 +59,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
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@ -51,10 +51,15 @@ properties:
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -65,12 +70,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8350";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
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@ -47,10 +47,15 @@ properties:
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
minItems: 2
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -61,11 +66,13 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8450";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

80
Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml Normal file
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@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,hawi-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on Hawi
maintainers:
- Dongfang Zhao <dongfang.zhao@oss.qualcomm.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also: include/dt-bindings/clock/qcom,hawi-gpucc.h
properties:
compatible:
enum:
- qcom,hawi-gpucc
- qcom,maili-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
power-domains:
items:
- description: A phandle to the MX power-domain
- description: A phandle to the CX power-domain
- description: A phandle to the GMXC power-domain
required-opps:
items:
- description: MX performance points
- description: CX performance points
- description: GMXC performance points
required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,hawi-gcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d90000 {
compatible = "qcom,hawi-gpucc";
reg = <0x0 0x03d90000 0x0 0x9800>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
power-domains = <&rpmhpd RPMHPD_MX>,
<&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_GMXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs_d3>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

1
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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@ -25,6 +25,7 @@ properties:
compatible:
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5210-cmn-pll
- qcom,ipq5332-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq6018-cmn-pll

23
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
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@ -4,25 +4,32 @@
$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics power domain Controller on Kaanapali
title: Qualcomm Graphics GX Power Domain Controller
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC). This module provides the power domains control
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
The Qualcomm graphics GX clock controller (GXCLKCTL) contains PLLs, clocks
and power domains (GDSC). This module provides the power domain control of
GXCLKCTL on Qualcomm SoCs, which helps the recovery of the graphics
subsystem.
See also:
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
properties:
compatible:
enum:
- qcom,glymur-gxclkctl
- qcom,kaanapali-gxclkctl
- qcom,sm8750-gxclkctl
oneOf:
- enum:
- qcom,glymur-gxclkctl
- qcom,kaanapali-gxclkctl
- qcom,sm8750-gxclkctl
- items:
- enum:
- qcom,hawi-gxclkctl
- qcom,maili-gxclkctl
- const: qcom,kaanapali-gxclkctl
power-domains:
description:

52
Documentation/devicetree/bindings/clock/qcom,kuno-gcc.yaml Normal file
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kuno-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Kuno
maintainers:
- Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks and resets on Kuno.
See also: include/dt-bindings/clock/qcom,kuno-gcc.h
properties:
compatible:
const: qcom,kuno-gcc
clocks:
items:
- description: Board XO source
- description: Board active-only XO source
- description: Sleep clock source
- description: PCIe pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@80000 {
compatible = "qcom,kuno-gcc";
reg = <0x00080000 0x1f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

39
Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml
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@ -8,16 +8,23 @@ title: Qualcomm Camera Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-camcc.h
See also:
include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h
include/dt-bindings/clock/qcom,eliza-camcc.h
include/dt-bindings/clock/qcom,milos-camcc.h
properties:
compatible:
const: qcom,milos-camcc
enum:
- qcom,eliza-cambistmclkcc
- qcom,eliza-camcc
- qcom,milos-camcc
clocks:
items:
@ -29,12 +36,33 @@ properties:
items:
- description: Interconnect path to enable the MultiMedia NoC
power-domains:
items:
- description: CX power domain
- description: MX power domain
required-opps:
items:
- description: CX performance point
- description: MX performance point
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
- if:
not:
properties:
compatible:
contains:
const: qcom,eliza-cambistmclkcc
then:
required:
- '#power-domain-cells'
unevaluatedProperties: false
@ -43,6 +71,7 @@ examples:
#include <dt-bindings/clock/qcom,milos-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@adb0000 {
compatible = "qcom,milos-camcc";
reg = <0x0adb0000 0x40000>;
@ -51,6 +80,12 @@ examples:
<&gcc GCC_CAMERA_AHB_CLK>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

29
Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml
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@ -8,16 +8,21 @@ title: Qualcomm Video Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-videocc.h
See also:
include/dt-bindings/clock/qcom,eliza-videocc.h
include/dt-bindings/clock/qcom,milos-videocc.h
properties:
compatible:
const: qcom,milos-videocc
enum:
- qcom,eliza-videocc
- qcom,milos-videocc
clocks:
items:
@ -26,9 +31,22 @@ properties:
- description: Sleep clock source
- description: Video AHB clock from GCC
power-domains:
items:
- description: CX power domain
- description: MX power domain
required-opps:
items:
- description: CX performance point
- description: MX performance point
required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
@ -38,6 +56,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@aaf0000 {
compatible = "qcom,milos-videocc";
reg = <0x0aaf0000 0x10000>;
@ -45,6 +64,12 @@ examples:
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
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@ -31,10 +31,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -45,6 +50,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0x00100000 0x1f0000>;
@ -52,6 +58,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml
View File

@ -33,9 +33,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -46,6 +51,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,qcs8300-gcc";
reg = <0x00100000 0xc7018>;
@ -59,6 +65,7 @@ examples:
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

5
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
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@ -56,6 +56,11 @@ properties:
- qcom,rpmcc-shikra
- const: qcom,rpmcc-qcm2290
- const: qcom,rpmcc
- items:
- enum:
- qcom,rpmcc-msm8952
- const: qcom,rpmcc-msm8976
- const: qcom,rpmcc
'#clock-cells':
const: 1

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
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@ -22,6 +22,7 @@ properties:
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,kuno-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
@ -39,6 +40,7 @@ properties:
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm7250-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk

7
Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
View File

@ -38,9 +38,14 @@ properties:
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -51,6 +56,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@80000 {
compatible = "qcom,sdx75-gcc";
reg = <0x80000 0x1f7400>;
@ -59,6 +65,7 @@ examples:
<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
View File

@ -29,9 +29,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -42,12 +47,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,sm4450-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

9
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
View File

@ -4,10 +4,13 @@
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6375
title: Qualcomm Global Clock & Reset Controller on SM6375 and SM7150
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
- Bjorn Andersson <andersson@kernel.org>
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <davidwronek@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@ -20,7 +23,9 @@ allOf:
properties:
compatible:
const: qcom,sm6375-gcc
enum:
- qcom,sm6375-gcc
- qcom,sm7150-gcc
clocks:
items:

53
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
View File

@ -1,53 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM7150
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <davidwronek@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM7150
See also: include/dt-bindings/clock/qcom,sm7150-gcc.h
properties:
compatible:
const: qcom,sm7150-gcc
clocks:
items:
- description: Board XO source
- description: Board XO Active-Only source
- description: Sleep clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm7150-gcc";
reg = <0x00100000 0x001f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

47
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -16,8 +16,10 @@ description: |
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,hawi-camcc.h
include/dt-bindings/clock/qcom,kaanapali-camcc.h
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,nord-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
@ -26,15 +28,24 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
oneOf:
- enum:
- qcom,hawi-camcc
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,maili-camcc
- qcom,nord-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
- items:
- enum:
- qcom,hawi-cambistmclkcc
- qcom,maili-cambistmclkcc
- const: qcom,kaanapali-cambistmclkcc
clocks:
items:
@ -43,6 +54,10 @@ properties:
- description: Board active XO source
- description: Sleep clock source
interconnects:
items:
- description: Interconnect path to enable the MultiMedia NoC
power-domains:
description:
Power domains required for the clock controller to operate
@ -78,12 +93,24 @@ allOf:
then:
required:
- required-opps
- if:
properties:
compatible:
contains:
enum:
- qcom,hawi-camcc
- qcom,maili-camcc
then:
required:
- interconnects
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ade0000 {
@ -97,6 +124,8 @@ examples:
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

3
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -15,6 +15,7 @@ description: |
domains on Qualcomm SoCs.
See also:
include/dt-bindings/clock/qcom,eliza-gpucc.h
include/dt-bindings/clock/qcom,glymur-gpucc.h
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
@ -32,6 +33,7 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-gpucc
- qcom,glymur-gpucc
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
@ -75,6 +77,7 @@ allOf:
compatible:
contains:
enum:
- qcom,eliza-gpucc
- qcom,sm8750-gpucc
then:
required:

2
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@ -19,6 +19,7 @@ description: |
include/dt-bindings/clock/qcom,hawi-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,maili-videocc.h
include/dt-bindings/clock/qcom,nord-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@ -31,6 +32,7 @@ properties:
- qcom,hawi-videocc
- qcom,kaanapali-videocc
- qcom,maili-videocc
- qcom,nord-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc

7
Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
View File

@ -31,9 +31,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -44,6 +49,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,sm8550-gcc";
reg = <0x00100000 0x001f4200>;
@ -55,6 +61,7 @@ examples:
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -36,7 +36,6 @@ properties:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
- items:
- enum:

7
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
View File

@ -32,9 +32,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -45,6 +50,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,sm8650-gcc";
reg = <0x00100000 0x001f4200>;
@ -58,6 +64,7 @@ examples:
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
View File

@ -34,9 +34,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX power domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -47,6 +52,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,sm8750-gcc";
reg = <0x00100000 0x001f4200>;
@ -58,6 +64,7 @@ examples:
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

114
Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml Normal file
View File

@ -0,0 +1,114 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-tcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm TCSR Clock Controller on X1E80100
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks on X1E80100
See also:
- include/dt-bindings/clock/qcom,x1e80100-tcsr.h
properties:
compatible:
items:
- enum:
- qcom,x1e80100-tcsr
- const: syscon
clocks:
items:
- description: TCXO pad clock
reg:
maxItems: 1
'#clock-cells':
const: 1
vdda-qrefrpt0-0p9-supply: true
vdda-qrefrpt1-0p9-supply: true
vdda-qrefrpt2-0p9-supply: true
vdda-qrefrpt3-0p9-supply: true
vdda-qrefrpt4-0p9-supply: true
vdda-qrefrx0-0p9-supply: true
vdda-qrefrx1-0p9-supply: true
vdda-qrefrx2-0p9-supply: true
vdda-qrefrx3-0p9-supply: true
vdda-qrefrx4-0p9-supply: true
vdda-qreftx0-0p9-supply: true
vdda-qreftx0-1p2-supply: true
vdda-qreftx1-0p9-supply: true
vdda-qreftx1-1p2-supply: true
vdda-refgen0-0p9-supply: true
vdda-refgen0-1p2-supply: true
vdda-refgen2-0p9-supply: true
vdda-refgen2-1p2-supply: true
required:
- compatible
- clocks
- '#clock-cells'
- vdda-qrefrpt0-0p9-supply
- vdda-qrefrpt1-0p9-supply
- vdda-qrefrpt2-0p9-supply
- vdda-qrefrpt3-0p9-supply
- vdda-qrefrpt4-0p9-supply
- vdda-qrefrx0-0p9-supply
- vdda-qrefrx1-0p9-supply
- vdda-qrefrx2-0p9-supply
- vdda-qrefrx3-0p9-supply
- vdda-qrefrx4-0p9-supply
- vdda-qreftx0-0p9-supply
- vdda-qreftx0-1p2-supply
- vdda-qreftx1-0p9-supply
- vdda-qreftx1-1p2-supply
- vdda-refgen0-0p9-supply
- vdda-refgen0-1p2-supply
- vdda-refgen2-0p9-supply
- vdda-refgen2-1p2-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@1fc0000 {
compatible = "qcom,x1e80100-tcsr", "syscon";
reg = <0x0 0x1fc0000 0x0 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
vdda-qrefrpt0-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt1-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt2-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt3-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt4-0p9-supply = <&vreg_l1a>;
vdda-qrefrx0-0p9-supply = <&vreg_l1a>;
vdda-qrefrx1-0p9-supply = <&vreg_l1a>;
vdda-qrefrx2-0p9-supply = <&vreg_l1a>;
vdda-qrefrx3-0p9-supply = <&vreg_l1a>;
vdda-qrefrx4-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-1p2-supply = <&vreg_l2a>;
vdda-qreftx1-0p9-supply = <&vreg_l1a>;
vdda-qreftx1-1p2-supply = <&vreg_l2a>;
vdda-refgen0-0p9-supply = <&vreg_l1a>;
vdda-refgen0-1p2-supply = <&vreg_l2a>;
vdda-refgen2-0p9-supply = <&vreg_l1a>;
vdda-refgen2-1p2-supply = <&vreg_l2a>;
};
};
...

1
MAINTAINERS
View File

@ -22367,6 +22367,7 @@ F: drivers/media/platform/qcom/camss/
QUALCOMM CLOCK DRIVERS
M: Bjorn Andersson <andersson@kernel.org>
R: Abel Vesa <abelvesa@kernel.org>
L: linux-arm-msm@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git

2
drivers/clk/at91/clk-main.c
View File

@ -170,7 +170,7 @@ at91_clk_register_main_osc(struct regmap *regmap,
init.name = name;
init.ops = &main_osc_ops;
if (parent_data)
init.parent_data = (const struct clk_parent_data *)parent_data;
init.parent_data = parent_data;
else
init.parent_names = &parent_name;
init.num_parents = 1;

11
drivers/clk/imx/clk-composite-93.c
View File

@ -43,11 +43,12 @@ static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg)
return ret;
}
static void imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable)
static int imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable)
{
struct clk_gate *gate = to_clk_gate(hw);
unsigned long flags;
u32 reg;
int ret;
if (gate->lock)
spin_lock_irqsave(gate->lock, flags);
@ -61,17 +62,17 @@ static void imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable)
writel(reg, gate->reg);
imx93_clk_composite_wait_ready(hw, gate->reg);
ret = imx93_clk_composite_wait_ready(hw, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
return ret;
}
static int imx93_clk_composite_gate_enable(struct clk_hw *hw)
{
imx93_clk_composite_gate_endisable(hw, 1);
return 0;
return imx93_clk_composite_gate_endisable(hw, 1);
}
static void imx93_clk_composite_gate_disable(struct clk_hw *hw)

1
drivers/clk/imx/clk-fracn-gppll.c
View File

@ -89,6 +89,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(350000000U, 175, 0, 1, 0, 12),
PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9),
PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),

15
drivers/clk/imx/clk.c
View File

@ -95,11 +95,16 @@ struct clk_hw *imx_obtain_fixed_clock_hw(
const char *name, unsigned long rate)
{
struct clk *clk;
struct clk_hw *hw;
clk = imx_obtain_fixed_clock_from_dt(name);
if (IS_ERR(clk))
clk = imx_clk_fixed(name, rate);
return __clk_get_hw(clk);
return __clk_get_hw(imx_clk_fixed(name, rate));
hw = __clk_get_hw(clk);
clk_put(clk);
return hw;
}
struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,
@ -119,12 +124,16 @@ struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,
struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
{
struct clk *clk;
struct clk_hw *hw;
clk = of_clk_get_by_name(np, name);
if (IS_ERR(clk))
return ERR_PTR(-ENOENT);
return __clk_get_hw(clk);
hw = __clk_get_hw(clk);
clk_put(clk);
return hw;
}
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);

11
drivers/clk/meson/t7-peripherals.c
View File

@ -947,9 +947,14 @@ static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0);
static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0);
static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0);
static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0);
static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0);
static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0);
static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0);
/*
* NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA between
* the peripherals and the DRAM. After the clocks are disabled, a device that
* starts a transfer cannot complete it.
*/
static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0);
static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0);
static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0);

167
drivers/clk/qcom/Kconfig
View File

@ -19,6 +19,17 @@ menuconfig COMMON_CLK_QCOM
if COMMON_CLK_QCOM
config CLK_ELIZA_CAMCC
tristate "Eliza Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_ELIZA_GCC
default m if ARCH_QCOM
help
Support for the camera clock controller on Qualcomm Technologies, Inc
Eliza devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config CLK_ELIZA_DISPCC
tristate "Eliza Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -39,6 +50,16 @@ config CLK_ELIZA_GCC
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
config CLK_ELIZA_GPUCC
tristate "Eliza Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_ELIZA_GCC
default m if ARCH_QCOM
help
Support for the graphics clock controller on Eliza devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config CLK_ELIZA_TCSRCC
tristate "Eliza TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -59,6 +80,16 @@ config CLK_GLYMUR_CAMCC
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config CLK_ELIZA_VIDEOCC
tristate "Eliza Video Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_ELIZA_GCC
default m if ARCH_QCOM
help
Support for the video clock controller on Eliza devices.
Say Y if you want to support video devices and functionality such as
video encode and decode.
config CLK_GLYMUR_DISPCC
tristate "Glymur Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -73,7 +104,6 @@ config CLK_GLYMUR_DISPCC
config CLK_GLYMUR_EVACC
tristate "Glymur EVA Clock Controller"
depends on ARM64 || COMPILE_TEST
default m if ARCH_QCOM
select CLK_GLYMUR_GCC
default m if ARCH_QCOM
help
@ -96,6 +126,7 @@ config CLK_GLYMUR_GPUCC
tristate "Glymur Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_GLYMUR_GCC
default m if ARCH_QCOM
help
Support for the graphics clock controller on Glymur devices.
Say Y if you want to support graphics controller devices and
@ -181,6 +212,27 @@ config CLK_KAANAPALI_VIDEOCC
Say Y if you want to support video devices and functionality such as
video encode/decode.
config CLK_KUNO_GCC
tristate "Kuno Global Clock Controller"
depends on ARM || COMPILE_TEST
select QCOM_GDSC
default ARCH_QCOM
help
Support for the global clock controller (GCC) on Kuno devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, SD, PCIe and Ethernet on the Kuno SoC. This clock
controller supplies the clocks and resets to those peripherals.
config CLK_MAILI_VIDEOCC
tristate "Maili Video Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_HAWI_GCC
default m if ARCH_QCOM
help
Support for the video clock controller on Maili devices.
Say Y if you want to support video devices and functionality such as
video encode/decode.
config CLK_NORD_DISPCC
tristate "Nord Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -192,15 +244,16 @@ config CLK_NORD_DISPCC
Say Y if you want to support display devices and functionality such as
splash screen.
config CLK_MAILI_VIDEOCC
tristate "Maili Video Clock Controller"
config CLK_NORD_CAMCC
tristate "Nord Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_HAWI_GCC
select CLK_NORD_GCC
default m if ARCH_QCOM
help
Support for the video clock controller on Maili devices.
Say Y if you want to support video devices and functionality such as
video encode/decode.
Support for the camera clock controller on Qualcomm Technologies, Inc
Nord devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config CLK_NORD_GCC
tristate "Nord Global Clock Controller"
@ -213,26 +266,6 @@ config CLK_NORD_GCC
SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination
of GCC, SE_GCC, NE_GCC and NW_GCC.
config CLK_SHIKRA_AUDIOCORECC
tristate "Shikra Audio Core Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_SHIKRA_GCC
default m if ARCH_QCOM
help
Support for the Audio Core clock controller on Qualcomm Shikra devices.
Say Y if you want to use AudioCoreCC clocks required to support audio
devices and it's functionality.
config CLK_SHIKRA_GCC
tristate "Shikra Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
default ARCH_QCOM
help
Support for the global clock controller on Shikra devices.
Say Y if you want to use multimedia devices or peripheral
devices such as Camera, Video, UART, SPI, I2C, USB, SD/eMMC etc.
config CLK_NORD_GPUCC
tristate "Nord Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -244,6 +277,45 @@ config CLK_NORD_GPUCC
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config CLK_NORD_TCSRCC
tristate "Nord TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
default m if ARCH_QCOM
help
Support for the TCSR clock controller on Nord devices.
Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
config CLK_SHIKRA_AUDIOCORECC
tristate "Shikra Audio Core Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_SHIKRA_GCC
default m if ARCH_QCOM
help
Support for the Audio Core clock controller on Qualcomm Shikra devices.
Say Y if you want to use AudioCoreCC clocks required to support audio
devices and it's functionality.
config CLK_NORD_VIDEOCC
tristate "Nord VIDEO Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_NORD_GCC
default m if ARCH_QCOM
help
Support for the video clock controller on Qualcomm Technologies, Inc.
Nord devices.
Say Y if you want to support video devices and functionality such as
video encode/decode.
config CLK_SHIKRA_GCC
tristate "Shikra Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
default ARCH_QCOM
help
Support for the global clock controller on Shikra devices.
Say Y if you want to use multimedia devices or peripheral
devices such as Camera, Video, UART, SPI, I2C, USB, SD/eMMC etc.
config CLK_X1E80100_CAMCC
tristate "X1E80100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -423,6 +495,17 @@ config QCOM_CLK_RPMH
Say Y if you want to support the clocks exposed by RPMh on
platforms such as SDM845.
config CLK_HAWI_CAMCC
tristate "Hawi Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_HAWI_GCC
default m if ARCH_QCOM
help
Support for the camera clock controller on Qualcomm Technologies, Inc
Hawi devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config CLK_HAWI_GCC
tristate "Hawi Global Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -433,6 +516,18 @@ config CLK_HAWI_GCC
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SD/eMMC, PCIe, etc.
config CLK_HAWI_GPUCC
tristate "Hawi Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_HAWI_GCC
default m if ARCH_QCOM
help
Support for the graphics clock controller on Hawi devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics. It also provides GX clock
domain control required for GPU power management on Hawi-based
devices.
config CLK_HAWI_TCSRCC
tristate "Hawi TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
@ -694,6 +789,16 @@ config MSM_GCC_8939
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8952
tristate "MSM8952 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
default ARCH_QCOM
help
Support for the global clock controller on MSM8952 devices.
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8960
tristate "APQ8064/MSM8960 Global Clock Controller"
depends on ARM || COMPILE_TEST
@ -895,14 +1000,6 @@ config QCS_GCC_404
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
config CLK_NORD_TCSRCC
tristate "Nord TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
default m if ARCH_QCOM
help
Support for the TCSR clock controller on Nord devices.
Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
config SA_CAMCC_8775P
tristate "SA8775P Camera Clock Controller"
depends on ARM64 || COMPILE_TEST

9
drivers/clk/qcom/Makefile
View File

@ -21,9 +21,12 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLK_ELIZA_CAMCC) += cambistmclkcc-eliza.o camcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
@ -32,7 +35,9 @@ obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
obj-$(CONFIG_CLK_HAWI_CAMCC) += cambistmclkcc-kaanapali.o camcc-hawi.o
obj-$(CONFIG_CLK_HAWI_GCC) += gcc-hawi.o
obj-$(CONFIG_CLK_HAWI_GPUCC) += gpucc-hawi.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_HAWI_TCSRCC) += tcsrcc-hawi.o
obj-$(CONFIG_CLK_HAWI_VIDEOCC) += videocc-hawi.o
obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
@ -41,11 +46,14 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
obj-$(CONFIG_CLK_KUNO_GCC) += gcc-kuno.o
obj-$(CONFIG_CLK_MAILI_VIDEOCC) += videocc-maili.o
obj-$(CONFIG_CLK_NORD_CAMCC) += camcc-nord.o
obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o
obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o
obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_NORD_VIDEOCC) += videocc-glymur.o
obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o
obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
@ -82,6 +90,7 @@ obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
obj-$(CONFIG_MSM_GCC_8917) += gcc-msm8917.o
obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o
obj-$(CONFIG_MSM_GCC_8952) += gcc-msm8952.o
obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o

464
drivers/clk/qcom/cambistmclkcc-eliza.c Normal file
View File

@ -0,0 +1,464 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,eliza-cambistmclkcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_AHB_CLK,
};
enum {
P_BI_TCXO,
P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN,
P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco rivian_ole_vco[] = {
{ 777000000, 1285000000, 0 },
};
/* 960.0 MHz Configuration */
static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config = {
.l = 0x32,
.cal_l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x10000030,
.config_ctl_hi_val = 0x80890263,
.config_ctl_hi1_val = 0x00000217,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000000,
};
static struct clk_alpha_pll cam_bist_mclk_cc_pll0 = {
.offset = 0x0,
.config = &cam_bist_mclk_cc_pll0_config,
.vco_table = rivian_ole_vco,
.num_vco = ARRAY_SIZE(rivian_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_evo_ops,
},
},
};
static const struct parent_map cam_bist_mclk_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
};
static const struct parent_map cam_bist_mclk_cc_parent_map_1[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_bist_mclk_cc_parent_data_1[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4),
F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src = {
.cmd_rcgr = 0x4000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src = {
.cmd_rcgr = 0x401c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src = {
.cmd_rcgr = 0x4038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src = {
.cmd_rcgr = 0x4054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src = {
.cmd_rcgr = 0x4070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src = {
.cmd_rcgr = 0x408c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src = {
.cmd_rcgr = 0x40a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src = {
.cmd_rcgr = 0x40c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_bist_mclk_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_bist_mclk_cc_sleep_clk_src = {
.cmd_rcgr = 0x40e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_1,
.freq_tbl = ftbl_cam_bist_mclk_cc_sleep_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_sleep_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch cam_bist_mclk_cc_mclk0_clk = {
.halt_reg = 0x4018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk1_clk = {
.halt_reg = 0x4034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk2_clk = {
.halt_reg = 0x4050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk3_clk = {
.halt_reg = 0x406c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x406c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk4_clk = {
.halt_reg = 0x4088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk5_clk = {
.halt_reg = 0x40a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk6_clk = {
.halt_reg = 0x40c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk7_clk = {
.halt_reg = 0x40dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *cam_bist_mclk_cc_eliza_clocks[] = {
[CAM_BIST_MCLK_CC_MCLK0_CLK] = &cam_bist_mclk_cc_mclk0_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] = &cam_bist_mclk_cc_mclk0_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK] = &cam_bist_mclk_cc_mclk1_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] = &cam_bist_mclk_cc_mclk1_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK] = &cam_bist_mclk_cc_mclk2_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] = &cam_bist_mclk_cc_mclk2_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK] = &cam_bist_mclk_cc_mclk3_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] = &cam_bist_mclk_cc_mclk3_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK] = &cam_bist_mclk_cc_mclk4_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] = &cam_bist_mclk_cc_mclk4_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK] = &cam_bist_mclk_cc_mclk5_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] = &cam_bist_mclk_cc_mclk5_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK] = &cam_bist_mclk_cc_mclk6_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] = &cam_bist_mclk_cc_mclk6_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK] = &cam_bist_mclk_cc_mclk7_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] = &cam_bist_mclk_cc_mclk7_clk_src.clkr,
[CAM_BIST_MCLK_CC_PLL0] = &cam_bist_mclk_cc_pll0.clkr,
[CAM_BIST_MCLK_CC_SLEEP_CLK_SRC] = &cam_bist_mclk_cc_sleep_clk_src.clkr,
};
static struct clk_alpha_pll *cam_bist_mclk_cc_eliza_plls[] = {
&cam_bist_mclk_cc_pll0,
};
static const u32 cam_bist_mclk_cc_eliza_critical_cbcrs[] = {
0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
};
static const struct regmap_config cam_bist_mclk_cc_eliza_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5010,
.fast_io = true,
};
static const struct qcom_cc_driver_data cam_bist_mclk_cc_eliza_driver_data = {
.alpha_plls = cam_bist_mclk_cc_eliza_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_eliza_plls),
.clk_cbcrs = cam_bist_mclk_cc_eliza_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_eliza_critical_cbcrs),
};
static const struct qcom_cc_desc cam_bist_mclk_cc_eliza_desc = {
.config = &cam_bist_mclk_cc_eliza_regmap_config,
.clks = cam_bist_mclk_cc_eliza_clocks,
.num_clks = ARRAY_SIZE(cam_bist_mclk_cc_eliza_clocks),
.use_rpm = true,
.driver_data = &cam_bist_mclk_cc_eliza_driver_data,
};
static const struct of_device_id cam_bist_mclk_cc_eliza_match_table[] = {
{ .compatible = "qcom,eliza-cambistmclkcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_eliza_match_table);
static int cam_bist_mclk_cc_eliza_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &cam_bist_mclk_cc_eliza_desc);
}
static struct platform_driver cam_bist_mclk_cc_eliza_driver = {
.probe = cam_bist_mclk_cc_eliza_probe,
.driver = {
.name = "cambistmclkcc-eliza",
.of_match_table = cam_bist_mclk_cc_eliza_match_table,
},
};
module_platform_driver(cam_bist_mclk_cc_eliza_driver);
MODULE_DESCRIPTION("QTI CAMBISTMCLKCC Eliza Driver");
MODULE_LICENSE("GPL");

7
drivers/clk/qcom/cambistmclkcc-kaanapali.c
View File

@ -394,11 +394,18 @@ static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config = {
.fast_io = true,
};
static void cam_bist_mclk_cc_kaanapali_regs_configure(struct device *dev, struct regmap *regmap)
{
regmap_write(regmap, 0x18, 0); /* CAM_BIST_MCLK_CC_PLL0_USER_CTL_U */
regmap_write(regmap, 0x28, 0); /* CAM_BIST_MCLK_CC_PLL0_CONFIG_CTL_U2 */
}
static const struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
.alpha_plls = cam_bist_mclk_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls),
.clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_critical_cbcrs),
.clk_regs_configure = cam_bist_mclk_cc_kaanapali_regs_configure,
};
static const struct qcom_cc_desc cam_bist_mclk_cc_kaanapali_desc = {

7
drivers/clk/qcom/cambistmclkcc-sm8750.c
View File

@ -413,11 +413,18 @@ static const struct regmap_config cam_bist_mclk_cc_sm8750_regmap_config = {
.fast_io = true,
};
static void cam_bist_mclk_cc_sm8750_regs_configure(struct device *dev, struct regmap *regmap)
{
regmap_write(regmap, 0x18, 0); /* CAM_BIST_MCLK_CC_PLL0_USER_CTL_U */
regmap_write(regmap, 0x28, 0); /* CAM_BIST_MCLK_CC_PLL0_CONFIG_CTL_U2 */
}
static const struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_critical_cbcrs),
.clk_regs_configure = cam_bist_mclk_cc_sm8750_regs_configure,
};
static const struct qcom_cc_desc cam_bist_mclk_cc_sm8750_desc = {

2803
drivers/clk/qcom/camcc-eliza.c Normal file
View File

File diff suppressed because it is too large Load Diff

7
drivers/clk/qcom/camcc-glymur.c
View File

@ -2235,11 +2235,18 @@ static const struct regmap_config cam_cc_glymur_regmap_config = {
.fast_io = true,
};
static void cam_cc_glymur_regs_configure(struct device *dev, struct regmap *regmap)
{
regmap_write(regmap, 0x2018, 0); /* CAM_CC_PLL2_PLL_USER_CTL_U */
regmap_write(regmap, 0x2028, 0); /* CAM_CC_PLL2_PLL_CONFIG_CTL_U2 */
}
static const struct qcom_cc_driver_data cam_cc_glymur_driver_data = {
.alpha_plls = cam_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_glymur_plls),
.clk_cbcrs = cam_cc_glymur_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_glymur_critical_cbcrs),
.clk_regs_configure = cam_cc_glymur_regs_configure,
};
static const struct qcom_cc_desc cam_cc_glymur_desc = {

3152
drivers/clk/qcom/camcc-hawi.c Normal file
View File

File diff suppressed because it is too large Load Diff

2941
drivers/clk/qcom/camcc-nord.c Normal file
View File

File diff suppressed because it is too large Load Diff

36
drivers/clk/qcom/camcc-sa8775p.c
View File

@ -1818,7 +1818,30 @@ static const struct regmap_config cam_cc_sa8775p_regmap_config = {
.fast_io = true,
};
static const u32 cam_cc_sa8775p_critical_cbcrs[] = {
0x13194, /* CAM_CC_CAMNOC_XO_CLK */
0x131ec, /* CAM_CC_GDSC_CLK */
0x13208, /* CAM_CC_SLEEP_CLK */
};
static const u32 cam_cc_qcs8300_critical_cbcrs[] = {
0x13178, /* CAM_CC_CAMNOC_XO_CLK */
0x131d0, /* CAM_CC_GDSC_CLK */
0x131ec, /* CAM_CC_SLEEP_CLK */
};
static const struct qcom_cc_driver_data cam_cc_sa8775p_driver_data = {
.clk_cbcrs = cam_cc_sa8775p_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sa8775p_critical_cbcrs),
};
static const struct qcom_cc_driver_data cam_cc_qcs8300_driver_data = {
.clk_cbcrs = cam_cc_qcs8300_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_qcs8300_critical_cbcrs),
};
static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
.driver_data = &cam_cc_sa8775p_driver_data,
.config = &cam_cc_sa8775p_regmap_config,
.clks = cam_cc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sa8775p_clocks),
@ -1837,6 +1860,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table);
static int cam_cc_sa8775p_probe(struct platform_device *pdev)
{
struct qcom_cc_desc desc = cam_cc_sa8775p_desc;
struct regmap *regmap;
int ret;
@ -1927,18 +1951,10 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
&cam_cc_titan_top_accu_shift_clk.clkr;
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
} else {
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
desc.driver_data = &cam_cc_qcs8300_driver_data;
}
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
ret = qcom_cc_really_probe(&pdev->dev, &desc, regmap);
pm_runtime_put(&pdev->dev);

13
drivers/clk/qcom/camcc-sc8280xp.c
View File

@ -2967,7 +2967,17 @@ static const struct regmap_config camcc_sc8280xp_regmap_config = {
.fast_io = true,
};
static const u32 camcc_sc8280xp_critical_cbcrs[] = {
0xc1e4, /* CAMCC_GDSC_CLK */
};
static const struct qcom_cc_driver_data camcc_sc8280xp_driver_data = {
.clk_cbcrs = camcc_sc8280xp_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(camcc_sc8280xp_critical_cbcrs),
};
static const struct qcom_cc_desc camcc_sc8280xp_desc = {
.driver_data = &camcc_sc8280xp_driver_data,
.config = &camcc_sc8280xp_regmap_config,
.clks = camcc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(camcc_sc8280xp_clocks),
@ -3011,9 +3021,6 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config);
clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &camcc_sc8280xp_desc, regmap);
if (ret)
goto err_disable;

13
drivers/clk/qcom/camcc-sm7150.c
View File

@ -2008,7 +2008,17 @@ static const struct regmap_config camcc_sm7150_regmap_config = {
.fast_io = true,
};
static const u32 camcc_sm7150_critical_cbcrs[] = {
0xc1a0, /* CAMCC_GDSC_CLK */
};
static const struct qcom_cc_driver_data camcc_sm7150_driver_data = {
.clk_cbcrs = camcc_sm7150_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(camcc_sm7150_critical_cbcrs),
};
static const struct qcom_cc_desc camcc_sm7150_desc = {
.driver_data = &camcc_sm7150_driver_data,
.config = &camcc_sm7150_regmap_config,
.clk_hws = camcc_sm7150_hws,
.num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws),
@ -2038,9 +2048,6 @@ static int camcc_sm7150_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */
return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap);
}

13
drivers/clk/qcom/camcc-sm8150.c
View File

@ -2093,7 +2093,17 @@ static const struct regmap_config cam_cc_sm8150_regmap_config = {
.fast_io = true,
};
static const u32 cam_cc_sm8150_critical_cbcrs[] = {
0xc1e4, /* CAM_CC_GDSC_CLK */
};
static const struct qcom_cc_driver_data cam_cc_sm8150_driver_data = {
.clk_cbcrs = cam_cc_sm8150_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8150_critical_cbcrs),
};
static const struct qcom_cc_desc cam_cc_sm8150_desc = {
.driver_data = &cam_cc_sm8150_driver_data,
.config = &cam_cc_sm8150_regmap_config,
.clks = cam_cc_sm8150_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sm8150_clocks),
@ -2134,9 +2144,6 @@ static int cam_cc_sm8150_probe(struct platform_device *pdev)
clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
/* Keep the critical clock always-on */
qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8150_desc, regmap);
pm_runtime_put(&pdev->dev);

9
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -2373,6 +2373,15 @@ void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
{
u32 lval = config->l;
/*
* If the bootloader left the PLL enabled it's likely that there are
* RCGs that will lock up if we disable the PLL below.
*/
if (trion_pll_is_enabled(pll, regmap)) {
pr_debug("Lucid Ole PLL is already enabled, skipping configuration\n");
return;
}
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);

35
drivers/clk/qcom/clk-rcg2.c
View File

@ -1332,7 +1332,10 @@ static int clk_rcg2_set_force_enable(struct clk_hw *hw)
/* wait for RCG to turn ON */
for (count = 500; count > 0; count--) {
if (clk_rcg2_is_enabled(hw))
ret = clk_rcg2_is_enabled(hw);
if (ret < 0)
return ret;
if (ret)
return 0;
udelay(1);
@ -1361,8 +1364,10 @@ clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
return ret;
ret = clk_rcg2_configure(rcg, f);
if (ret)
if (ret) {
clk_rcg2_clear_force_enable(hw);
return ret;
}
return clk_rcg2_clear_force_enable(hw);
}
@ -1555,7 +1560,20 @@ const struct clk_ops clk_rcg2_shared_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/*
* Read the config register so that the parent is properly mapped at
* registration time.
*/
return regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
&rcg->parked_cfg);
}
const struct clk_ops clk_rcg2_shared_floor_ops = {
.init = clk_rcg2_shared_no_init_park,
.enable = clk_rcg2_shared_enable,
.disable = clk_rcg2_shared_disable,
.get_parent = clk_rcg2_shared_get_parent,
@ -1567,19 +1585,6 @@ const struct clk_ops clk_rcg2_shared_floor_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg2_shared_floor_ops);
static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/*
* Read the config register so that the parent is properly mapped at
* registration time.
*/
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
return 0;
}
/*
* Like clk_rcg2_shared_ops but skip the init so that the clk frequency is left
* unchanged at registration time.

16
drivers/clk/qcom/clk-regmap-divider.c
View File

@ -27,7 +27,8 @@ static int div_ro_determine_rate(struct clk_hw *hw,
val &= BIT(divider->width) - 1;
return divider_ro_determine_rate(hw, req, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST, val);
CLK_DIVIDER_ROUND_CLOSEST | divider->flags,
val);
}
static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
@ -35,7 +36,7 @@ static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
return divider_determine_rate(hw, req, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
CLK_DIVIDER_ROUND_CLOSEST | divider->flags);
}
static int div_set_rate(struct clk_hw *hw, unsigned long rate,
@ -43,14 +44,16 @@ static int div_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
struct clk_regmap *clkr = &divider->clkr;
u32 div;
int div;
div = divider_get_val(rate, parent_rate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
CLK_DIVIDER_ROUND_CLOSEST | divider->flags);
if (div < 0)
return div;
return regmap_update_bits(clkr->regmap, divider->reg,
(BIT(divider->width) - 1) << divider->shift,
div << divider->shift);
(u32)div << divider->shift);
}
static unsigned long div_recalc_rate(struct clk_hw *hw,
@ -65,7 +68,8 @@ static unsigned long div_recalc_rate(struct clk_hw *hw,
div &= BIT(divider->width) - 1;
return divider_recalc_rate(hw, parent_rate, div, NULL,
CLK_DIVIDER_ROUND_CLOSEST, divider->width);
CLK_DIVIDER_ROUND_CLOSEST | divider->flags,
divider->width);
}
const struct clk_ops clk_regmap_div_ops = {

1
drivers/clk/qcom/clk-regmap-divider.h
View File

@ -13,6 +13,7 @@ struct clk_regmap_div {
u32 reg;
u32 shift;
u32 width;
unsigned long flags;
struct clk_regmap clkr;
};

44
drivers/clk/qcom/clk-rpmh.c
View File

@ -393,6 +393,7 @@ DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk7, _a1_e0, "C7A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2);
@ -902,6 +903,10 @@ static struct clk_hw *glymur_rpmh_clocks[] = {
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a1_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a1_e0_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a1_e0.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a1_e0_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a1_e0.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a1_e0_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_glymur = {
@ -937,6 +942,20 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
.num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
};
static struct clk_hw *kuno_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_kuno = {
.clks = kuno_rpmh_clocks,
.num_clks = ARRAY_SIZE(kuno_rpmh_clocks),
};
static struct clk_hw *eliza_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
@ -1005,6 +1024,29 @@ static const struct clk_rpmh_desc clk_rpmh_hawi = {
.num_clks = ARRAY_SIZE(hawi_rpmh_clocks),
};
static struct clk_hw *sm7250_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_d.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_d_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm7250 = {
.clks = sm7250_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm7250_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -1097,6 +1139,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,hawi-rpmh-clk", .data = &clk_rpmh_hawi},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
{ .compatible = "qcom,kuno-rpmh-clk", .data = &clk_rpmh_kuno},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
{ .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},
{ .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
@ -1114,6 +1157,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
{ .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
{ .compatible = "qcom,sm7250-rpmh-clk", .data = &clk_rpmh_sm7250},
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},

13
drivers/clk/qcom/dispcc-sc7280.c
View File

@ -860,7 +860,17 @@ static const struct regmap_config disp_cc_sc7280_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sc7280_critical_cbcrs[] = {
0x5008, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sc7280_driver_data = {
.clk_cbcrs = disp_cc_sc7280_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sc7280_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sc7280_desc = {
.driver_data = &disp_cc_sc7280_driver_data,
.config = &disp_cc_sc7280_regmap_config,
.clks = disp_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
@ -886,9 +896,6 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
}

18
drivers/clk/qcom/dispcc-sc8280xp.c
View File

@ -3108,7 +3108,17 @@ static const struct regmap_config disp_cc_sc8280xp_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sc8280xp_critical_cbcrs[] = {
0x605c, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sc8280xp_driver_data = {
.clk_cbcrs = disp_cc_sc8280xp_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sc8280xp_critical_cbcrs),
};
static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = {
.driver_data = &disp_cc_sc8280xp_driver_data,
.config = &disp_cc_sc8280xp_regmap_config,
.clks = disp0_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks),
@ -3119,6 +3129,7 @@ static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = {
};
static const struct qcom_cc_desc disp1_cc_sc8280xp_desc = {
.driver_data = &disp_cc_sc8280xp_driver_data,
.config = &disp_cc_sc8280xp_regmap_config,
.clks = disp1_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks),
@ -3167,13 +3178,8 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
if (ret) {
if (ret)
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
}
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);

15
drivers/clk/qcom/dispcc-sm4450.c
View File

@ -719,7 +719,18 @@ static const struct regmap_config disp_cc_sm4450_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sm4450_critical_cbcrs[] = {
0xe070, /* DISP_CC_SLEEP_CLK */
0xe054, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sm4450_driver_data = {
.clk_cbcrs = disp_cc_sm4450_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm4450_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sm4450_desc = {
.driver_data = &disp_cc_sm4450_driver_data,
.config = &disp_cc_sm4450_regmap_config,
.clks = disp_cc_sm4450_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm4450_clocks),
@ -746,10 +757,6 @@ static int disp_cc_sm4450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll0_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xe070); /* DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm4450_desc, regmap);
}

13
drivers/clk/qcom/dispcc-sm6115.c
View File

@ -561,7 +561,17 @@ static const struct regmap_config disp_cc_sm6115_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sm6115_critical_cbcrs[] = {
0x604c, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sm6115_driver_data = {
.clk_cbcrs = disp_cc_sm6115_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm6115_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sm6115_desc = {
.driver_data = &disp_cc_sm6115_driver_data,
.config = &disp_cc_sm6115_regmap_config,
.clks = disp_cc_sm6115_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks),
@ -588,9 +598,6 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6115_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");

13
drivers/clk/qcom/dispcc-sm7150.c
View File

@ -963,7 +963,17 @@ static const struct regmap_config dispcc_sm7150_regmap_config = {
.fast_io = true,
};
static const u32 dispcc_sm7150_critical_cbcrs[] = {
0x605c, /* DISPCC_XO_CLK */
};
static const struct qcom_cc_driver_data dispcc_sm7150_driver_data = {
.clk_cbcrs = dispcc_sm7150_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(dispcc_sm7150_critical_cbcrs),
};
static const struct qcom_cc_desc dispcc_sm7150_desc = {
.driver_data = &dispcc_sm7150_driver_data,
.config = &dispcc_sm7150_regmap_config,
.clks = dispcc_sm7150_clocks,
.num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
@ -991,9 +1001,6 @@ static int dispcc_sm7150_probe(struct platform_device *pdev)
/* Enable clock gating for DSI and MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISPCC_XO_CLK */
return qcom_cc_really_probe(&pdev->dev, &dispcc_sm7150_desc, regmap);
}

13
drivers/clk/qcom/dispcc-sm8250.c
View File

@ -1232,7 +1232,17 @@ static const struct regmap_config disp_cc_sm8250_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sm8250_critical_cbcrs[] = {
0x605c, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sm8250_driver_data = {
.clk_cbcrs = disp_cc_sm8250_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8250_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sm8250_desc = {
.driver_data = &disp_cc_sm8250_driver_data,
.config = &disp_cc_sm8250_regmap_config,
.clks = disp_cc_sm8250_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
@ -1370,9 +1380,6 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);

40
drivers/clk/qcom/dispcc-sm8450.c
View File

@ -613,7 +613,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};
@ -1778,6 +1778,29 @@ static const struct regmap_config disp_cc_sm8450_regmap_config = {
.fast_io = true,
};
static struct clk_alpha_pll *disp_cc_sm8450_plls[] = {
&disp_cc_pll0,
&disp_cc_pll1,
};
static const u32 disp_cc_sm8450_critical_cbcrs[] = {
0xe05c, /* DISP_CC_XO_CLK */
};
static void disp_cc_sm8450_clk_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Enable clock gating for MDP clocks */
regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));
}
static const struct qcom_cc_driver_data disp_cc_sm8450_driver_data = {
.alpha_plls = disp_cc_sm8450_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_sm8450_plls),
.clk_cbcrs = disp_cc_sm8450_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8450_critical_cbcrs),
.clk_regs_configure = disp_cc_sm8450_clk_regs_configure,
};
static const struct qcom_cc_desc disp_cc_sm8450_desc = {
.config = &disp_cc_sm8450_regmap_config,
.clks = disp_cc_sm8450_clocks,
@ -1786,6 +1809,7 @@ static const struct qcom_cc_desc disp_cc_sm8450_desc = {
.num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),
.gdscs = disp_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),
.driver_data = &disp_cc_sm8450_driver_data,
};
static const struct of_device_id disp_cc_sm8450_match_table[] = {
@ -1823,19 +1847,13 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config);
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config);
disp_cc_pll0.config = &sm8475_disp_cc_pll0_config;
disp_cc_pll1.config = &sm8475_disp_cc_pll1_config;
} else {
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
disp_cc_pll0.config = &disp_cc_pll0_config;
disp_cc_pll1.config = &disp_cc_pll1_config;
}
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);
if (ret)
goto err_put_rpm;

13
drivers/clk/qcom/dispcc-sm8550.c
View File

@ -1744,7 +1744,17 @@ static const struct regmap_config disp_cc_sm8550_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sm8550_critical_cbcrs[] = {
0xe054, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sm8550_driver_data = {
.clk_cbcrs = disp_cc_sm8550_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8550_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sm8550_desc = {
.driver_data = &disp_cc_sm8550_driver_data,
.config = &disp_cc_sm8550_regmap_config,
.clks = disp_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks),
@ -1800,9 +1810,6 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap);
if (ret)
goto err_put_rpm;

19
drivers/clk/qcom/dispcc-sm8750.c
View File

@ -1884,7 +1884,20 @@ static const struct regmap_config disp_cc_sm8750_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_sm8750_critical_cbcrs[] = {
0xe07c, /* DISP_CC_SLEEP_CLK */
0xe05c, /* DISP_CC_XO_CLK */
0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
};
static const struct qcom_cc_driver_data disp_cc_sm8750_driver_data = {
.clk_cbcrs = disp_cc_sm8750_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8750_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_sm8750_desc = {
.driver_data = &disp_cc_sm8750_driver_data,
.config = &disp_cc_sm8750_regmap_config,
.clks = disp_cc_sm8750_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8750_clocks),
@ -1926,12 +1939,6 @@ static int disp_cc_sm8750_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe07c); /* DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xc00c); /* DISP_CC_MDSS_RSCC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xc008); /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8750_desc, regmap);
if (ret)
goto err_put_rpm;

27
drivers/clk/qcom/dispcc-x1e80100.c
View File

@ -1637,7 +1637,18 @@ static const struct regmap_config disp_cc_x1e80100_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_x1e80100_critical_cbcrs[] = {
0xe074, /* DISP_CC_SLEEP_CLK */
0xe054, /* DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_x1e80100_driver_data = {
.clk_cbcrs = disp_cc_x1e80100_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_x1e80100_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_x1e80100_desc = {
.driver_data = &disp_cc_x1e80100_driver_data,
.config = &disp_cc_x1e80100_regmap_config,
.clks = disp_cc_x1e80100_clocks,
.num_clks = ARRAY_SIZE(disp_cc_x1e80100_clocks),
@ -1678,10 +1689,6 @@ static int disp_cc_x1e80100_probe(struct platform_device *pdev)
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/* Keep clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_x1e80100_desc, regmap);
if (ret)
goto err_put_rpm;
@ -1704,17 +1711,7 @@ static struct platform_driver disp_cc_x1e80100_driver = {
},
};
static int __init disp_cc_x1e80100_init(void)
{
return platform_driver_register(&disp_cc_x1e80100_driver);
}
subsys_initcall(disp_cc_x1e80100_init);
static void __exit disp_cc_x1e80100_exit(void)
{
platform_driver_unregister(&disp_cc_x1e80100_driver);
}
module_exit(disp_cc_x1e80100_exit);
subsys_platform_driver(disp_cc_x1e80100_driver);
MODULE_DESCRIPTION("QTI Display Clock Controller X1E80100 Driver");
MODULE_LICENSE("GPL");

15
drivers/clk/qcom/dispcc0-sa8775p.c
View File

@ -1414,7 +1414,18 @@ static const struct regmap_config disp_cc_0_sa8775p_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_0_sa8775p_critical_cbcrs[] = {
0xc070, /* MDSS_0_DISP_CC_SLEEP_CLK */
0xc054, /* MDSS_0_DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_0_sa8775p_driver_data = {
.clk_cbcrs = disp_cc_0_sa8775p_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_0_sa8775p_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_0_sa8775p_desc = {
.driver_data = &disp_cc_0_sa8775p_driver_data,
.config = &disp_cc_0_sa8775p_regmap_config,
.clks = disp_cc_0_sa8775p_clocks,
.num_clks = ARRAY_SIZE(disp_cc_0_sa8775p_clocks),
@ -1452,10 +1463,6 @@ static int disp_cc_0_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll0, regmap, &mdss_0_disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll1, regmap, &mdss_0_disp_cc_pll1_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_0_DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_0_DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_0_sa8775p_desc, regmap);
pm_runtime_put(&pdev->dev);

15
drivers/clk/qcom/dispcc1-sa8775p.c
View File

@ -1414,7 +1414,18 @@ static const struct regmap_config disp_cc_1_sa8775p_regmap_config = {
.fast_io = true,
};
static const u32 disp_cc_1_sa8775p_critical_cbcrs[] = {
0xc070, /* MDSS_1_DISP_CC_SLEEP_CLK */
0xc054, /* MDSS_1_DISP_CC_XO_CLK */
};
static const struct qcom_cc_driver_data disp_cc_1_sa8775p_driver_data = {
.clk_cbcrs = disp_cc_1_sa8775p_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_1_sa8775p_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_1_sa8775p_desc = {
.driver_data = &disp_cc_1_sa8775p_driver_data,
.config = &disp_cc_1_sa8775p_regmap_config,
.clks = disp_cc_1_sa8775p_clocks,
.num_clks = ARRAY_SIZE(disp_cc_1_sa8775p_clocks),
@ -1452,10 +1463,6 @@ static int disp_cc_1_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll0, regmap, &mdss_1_disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll1, regmap, &mdss_1_disp_cc_pll1_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_1_DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_1_DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_1_sa8775p_desc, regmap);
pm_runtime_put(&pdev->dev);

13
drivers/clk/qcom/gcc-eliza.c
View File

@ -3066,6 +3066,7 @@ static const struct qcom_cc_desc gcc_eliza_desc = {
.num_resets = ARRAY_SIZE(gcc_eliza_resets),
.gdscs = gcc_eliza_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
.use_rpm = true,
.driver_data = &gcc_eliza_driver_data,
};
@ -3088,17 +3089,7 @@ static struct platform_driver gcc_eliza_driver = {
},
};
static int __init gcc_eliza_init(void)
{
return platform_driver_register(&gcc_eliza_driver);
}
subsys_initcall(gcc_eliza_init);
static void __exit gcc_eliza_exit(void)
{
platform_driver_unregister(&gcc_eliza_driver);
}
module_exit(gcc_eliza_exit);
subsys_platform_driver(gcc_eliza_driver);
MODULE_DESCRIPTION("QTI GCC Eliza Driver");
MODULE_LICENSE("GPL");

81
drivers/clk/qcom/gcc-glymur.c
View File

@ -481,36 +481,6 @@ static const struct clk_parent_data gcc_parent_data_17[] = {
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_18[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_19[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_20[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_20[] = {
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_21[] = {
{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
@ -907,47 +877,44 @@ static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = {
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x7706c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_18,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_18,
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770f0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_19,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x7705c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_20,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_20,
.num_parents = ARRAY_SIZE(gcc_parent_data_20),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
@ -8571,17 +8538,7 @@ static struct platform_driver gcc_glymur_driver = {
},
};
static int __init gcc_glymur_init(void)
{
return platform_driver_register(&gcc_glymur_driver);
}
subsys_initcall(gcc_glymur_init);
static void __exit gcc_glymur_exit(void)
{
platform_driver_unregister(&gcc_glymur_driver);
}
module_exit(gcc_glymur_exit);
subsys_platform_driver(gcc_glymur_driver);
MODULE_DESCRIPTION("QTI GCC Glymur Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-hawi.c
View File

@ -3841,17 +3841,7 @@ static struct platform_driver gcc_hawi_driver = {
},
};
static int __init gcc_hawi_init(void)
{
return platform_driver_register(&gcc_hawi_driver);
}
subsys_initcall(gcc_hawi_init);
static void __exit gcc_hawi_exit(void)
{
platform_driver_unregister(&gcc_hawi_driver);
}
module_exit(gcc_hawi_exit);
subsys_platform_driver(gcc_hawi_driver);
MODULE_DESCRIPTION("QTI GCC HAWI Driver");
MODULE_LICENSE("GPL");

10
drivers/clk/qcom/gcc-ipq5018.c
View File

@ -68,6 +68,15 @@ static struct clk_alpha_pll gpll0_main = {
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
/*
* During system boot, this PLL feeds the CPUs.
* Mark it as critical to ensure that CCF does
* not disable it, even if there are no active
* consumers. This is needed to avoid a system
* hang caused by turning off the clock driving
* the CPUs.
*/
.flags = CLK_IS_CRITICAL,
},
},
};
@ -1260,6 +1269,7 @@ static struct clk_rcg2 usb0_master_clk_src = {
};
static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(60000000, P_GPLL4, 10, 1, 2),
{ }
};

1
drivers/clk/qcom/gcc-ipq5210.c
View File

@ -716,6 +716,7 @@ static struct clk_rcg2 gcc_usb0_master_clk_src = {
};
static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
{ }
};

1
drivers/clk/qcom/gcc-ipq5332.c
View File

@ -1038,6 +1038,7 @@ static struct clk_rcg2 gcc_usb0_master_clk_src = {
};
static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
{ }
};

4
drivers/clk/qcom/gcc-ipq5424.c
View File

@ -2949,7 +2949,7 @@ static const struct qcom_reset_map gcc_ipq5424_resets[] = {
[GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 },
[GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 },
[GCC_IMEM_BCR] = { 0x0e000, 0 },
[GCC_TME_BCR] = { 0x100000, 0 },
[GCC_TME_BCR] = { 0x10000, 0 },
[GCC_DDRSS_BCR] = { 0x11000, 0 },
[GCC_PRNG_BCR] = { 0x13020, 0 },
[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
@ -2960,7 +2960,7 @@ static const struct qcom_reset_map gcc_ipq5424_resets[] = {
[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
[GCC_WCSS_BCR] = { 0x18004, 0 },
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
[GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 },
[GCC_TME_SEC_BUS_BCR] = { 0x1a030, 0 },
[GCC_ADSS_BCR] = { 0x1c000, 0 },
[GCC_LPASS_BCR] = { 0x27000, 0 },
[GCC_PCIE0_BCR] = { 0x28000, 0 },

22
drivers/clk/qcom/gcc-ipq9650.c
View File

@ -4,11 +4,13 @@
*/
#include <linux/clk-provider.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq9650-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq9650.h>
#include <dt-bindings/reset/qcom,ipq9650-gcc.h>
#include "clk-alpha-pll.h"
@ -3474,6 +3476,22 @@ static const struct qcom_reset_map gcc_ipq9650_resets[] = {
[GCC_USB_BCR] = { 0x2c000 },
};
#define IPQ_APPS_ID 9650 /* some unique value */
static const struct qcom_icc_hws_data icc_ipq9650_hws[] = {
{ MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
{ MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_ANOC_PCIE0_1LANE_S_CLK },
{ MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_2LANE_M_CLK },
{ MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_ANOC_PCIE1_2LANE_S_CLK },
{ MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
{ MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_ANOC_PCIE2_2LANE_S_CLK },
{ MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
{ MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_ANOC_PCIE3_2LANE_S_CLK },
{ MASTER_ANOC_PCIE4, SLAVE_ANOC_PCIE4, GCC_ANOC_PCIE4_1LANE_M_CLK },
{ MASTER_CNOC_PCIE4, SLAVE_CNOC_PCIE4, GCC_ANOC_PCIE4_1LANE_S_CLK },
{ MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK },
};
static const struct of_device_id gcc_ipq9650_match_table[] = {
{ .compatible = "qcom,ipq9650-gcc" },
{ }
@ -3503,6 +3521,9 @@ static const struct qcom_cc_desc gcc_ipq9650_desc = {
.num_resets = ARRAY_SIZE(gcc_ipq9650_resets),
.clk_hws = gcc_ipq9650_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq9650_hws),
.icc_hws = icc_ipq9650_hws,
.num_icc_hws = ARRAY_SIZE(icc_ipq9650_hws),
.icc_first_node_id = IPQ_APPS_ID,
};
static int gcc_ipq9650_probe(struct platform_device *pdev)
@ -3515,6 +3536,7 @@ static struct platform_driver gcc_ipq9650_driver = {
.driver = {
.name = "qcom,gcc-ipq9650",
.of_match_table = gcc_ipq9650_match_table,
.sync_state = icc_sync_state,
},
};

13
drivers/clk/qcom/gcc-kaanapali.c
View File

@ -3500,6 +3500,7 @@ static const struct qcom_cc_desc gcc_kaanapali_desc = {
.num_resets = ARRAY_SIZE(gcc_kaanapali_resets),
.gdscs = gcc_kaanapali_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs),
.use_rpm = true,
.driver_data = &gcc_kaanapali_driver_data,
};
@ -3522,17 +3523,7 @@ static struct platform_driver gcc_kaanapali_driver = {
},
};
static int __init gcc_kaanapali_init(void)
{
return platform_driver_register(&gcc_kaanapali_driver);
}
subsys_initcall(gcc_kaanapali_init);
static void __exit gcc_kaanapali_exit(void)
{
platform_driver_unregister(&gcc_kaanapali_driver);
}
module_exit(gcc_kaanapali_exit);
subsys_platform_driver(gcc_kaanapali_driver);
MODULE_DESCRIPTION("QTI GCC Kaanapali Driver");
MODULE_LICENSE("GPL");

1473
drivers/clk/qcom/gcc-kuno.c Normal file
View File

File diff suppressed because it is too large Load Diff

12
drivers/clk/qcom/gcc-milos.c
View File

@ -3208,17 +3208,7 @@ static struct platform_driver gcc_milos_driver = {
},
};
static int __init gcc_milos_init(void)
{
return platform_driver_register(&gcc_milos_driver);
}
subsys_initcall(gcc_milos_init);
static void __exit gcc_milos_exit(void)
{
platform_driver_unregister(&gcc_milos_driver);
}
module_exit(gcc_milos_exit);
subsys_platform_driver(gcc_milos_driver);
MODULE_DESCRIPTION("QTI GCC Milos Driver");
MODULE_LICENSE("GPL");

4
drivers/clk/qcom/gcc-msm8939.c
View File

@ -3665,6 +3665,7 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
@ -3682,6 +3683,7 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
.halt_reg = 0x4c034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c034,
.enable_mask = BIT(0),
@ -3754,6 +3756,7 @@ static struct gdsc venus_core0_gdsc = {
.pd = {
.name = "venus_core0",
},
.flags = HW_CTRL_TRIGGER,
.pwrsts = PWRSTS_OFF_ON,
};
@ -3762,6 +3765,7 @@ static struct gdsc venus_core1_gdsc = {
.pd = {
.name = "venus_core1",
},
.flags = HW_CTRL_TRIGGER,
.pwrsts = PWRSTS_OFF_ON,
};

3548
drivers/clk/qcom/gcc-msm8952.c Normal file
View File

File diff suppressed because it is too large Load Diff

12
drivers/clk/qcom/gcc-nord.c
View File

@ -1862,17 +1862,7 @@ static struct platform_driver gcc_nord_driver = {
},
};
static int __init gcc_nord_init(void)
{
return platform_driver_register(&gcc_nord_driver);
}
subsys_initcall(gcc_nord_init);
static void __exit gcc_nord_exit(void)
{
platform_driver_unregister(&gcc_nord_driver);
}
module_exit(gcc_nord_exit);
subsys_platform_driver(gcc_nord_driver);
MODULE_DESCRIPTION("QTI GCC NORD Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-qcm2290.c
View File

@ -2923,17 +2923,7 @@ static struct platform_driver gcc_qcm2290_driver = {
},
};
static int __init gcc_qcm2290_init(void)
{
return platform_driver_register(&gcc_qcm2290_driver);
}
subsys_initcall(gcc_qcm2290_init);
static void __exit gcc_qcm2290_exit(void)
{
platform_driver_unregister(&gcc_qcm2290_driver);
}
module_exit(gcc_qcm2290_exit);
subsys_platform_driver(gcc_qcm2290_driver);
MODULE_DESCRIPTION("QTI GCC QCM2290 Driver");
MODULE_LICENSE("GPL v2");

69
drivers/clk/qcom/gcc-qcs615.c
View File

@ -2958,7 +2958,34 @@ static const struct regmap_config gcc_qcs615_regmap_config = {
.fast_io = true,
};
static const u32 gcc_qcs615_critical_cbcrs[] = {
0xb008, /* GCC_CAMERA_AHB_CLK */
0xb044, /* GCC_CAMERA_XO_CLK */
0xb00c, /* GCC_DISP_AHB_CLK */
0xb048, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0xb004, /* GCC_VIDEO_AHB_CLK */
0xb040, /* GCC_VIDEO_XO_CLK */
0x48004, /* GCC_CPUSS_GNOC_CLK */
};
static void gcc_qcs615_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Disable the GPLL0 active input to MM blocks and GPU via MISC registers. */
regmap_update_bits(regmap, 0x0b084, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x9b000, BIT(0), BIT(0));
}
static const struct qcom_cc_driver_data gcc_qcs615_driver_data = {
.clk_cbcrs = gcc_qcs615_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_qcs615_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_qcs615_regs_configure,
};
static const struct qcom_cc_desc gcc_qcs615_desc = {
.driver_data = &gcc_qcs615_driver_data,
.config = &gcc_qcs615_regmap_config,
.clk_hws = gcc_qcs615_hws,
.num_clk_hws = ARRAY_SIZE(gcc_qcs615_hws),
@ -2978,35 +3005,7 @@ MODULE_DEVICE_TABLE(of, gcc_qcs615_match_table);
static int gcc_qcs615_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_qcs615_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to MM blocks and GPU
* via MISC registers.
*/
regmap_update_bits(regmap, 0x0b084, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x9b000, BIT(0), BIT(0));
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x480040); /* GCC_CPUSS_GNOC_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_qcs615_desc, regmap);
return qcom_cc_probe(pdev, &gcc_qcs615_desc);
}
static struct platform_driver gcc_qcs615_driver = {
@ -3017,17 +3016,7 @@ static struct platform_driver gcc_qcs615_driver = {
},
};
static int __init gcc_qcs615_init(void)
{
return platform_driver_register(&gcc_qcs615_driver);
}
subsys_initcall(gcc_qcs615_init);
static void __exit gcc_qcs615_exit(void)
{
platform_driver_unregister(&gcc_qcs615_driver);
}
module_exit(gcc_qcs615_exit);
subsys_platform_driver(gcc_qcs615_driver);
MODULE_DESCRIPTION("QTI GCC QCS615 Driver");
MODULE_LICENSE("GPL");

167
drivers/clk/qcom/gcc-qcs8300.c
View File

@ -42,6 +42,7 @@ enum {
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL1_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL5_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
@ -128,6 +129,23 @@ static struct clk_alpha_pll gcc_gpll4 = {
},
};
static struct clk_alpha_pll gcc_gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll5",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@ -364,6 +382,22 @@ static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_19[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
.reg = 0xa9074,
.shift = 0,
@ -1094,6 +1128,25 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = {
F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4),
{ }
};
static struct clk_rcg2 gcc_tscss_cntr_clk_src = {
.cmd_rcgr = 0x21008,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_19,
.freq_tbl = ftbl_gcc_tscss_cntr_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_tscss_cntr_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
@ -2899,6 +2952,50 @@ static struct clk_branch gcc_sgmi_clkref_en = {
},
};
static struct clk_branch gcc_tscss_ahb_clk = {
.halt_reg = 0x21024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tscss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tscss_etu_clk = {
.halt_reg = 0x21020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tscss_etu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tscss_global_cntr_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x21004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tscss_global_cntr_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_tscss_cntr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x83020,
.halt_check = BRANCH_HALT_VOTED,
@ -3360,6 +3457,7 @@ static struct clk_regmap *gcc_qcs8300_clocks[] = {
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL1] = &gcc_gpll1.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL5] = &gcc_gpll5.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
@ -3464,6 +3562,10 @@ static struct clk_regmap *gcc_qcs8300_clocks[] = {
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
[GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr,
[GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr,
[GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr,
[GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
@ -3523,6 +3625,7 @@ static const struct qcom_reset_map gcc_qcs8300_resets[] = {
[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
[GCC_SDCC1_BCR] = { 0x20000 },
[GCC_TSCSS_BCR] = { 0x21000 },
[GCC_UFS_PHY_BCR] = { 0x83000 },
[GCC_USB20_PRIM_BCR] = { 0x1c000 },
[GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
@ -3570,7 +3673,32 @@ static const struct regmap_config gcc_qcs8300_regmap_config = {
.fast_io = true,
};
static const u32 gcc_qcs8300_critical_cbcrs[] = {
0x32004, /* GCC_CAMERA_AHB_CLK */
0x32020, /* GCC_CAMERA_XO_CLK */
0x33004, /* GCC_DISP_AHB_CLK */
0x33018, /* GCC_DISP_XO_CLK */
0x7d004, /* GCC_GPU_CFG_AHB_CLK */
0x34004, /* GCC_VIDEO_AHB_CLK */
0x34024, /* GCC_VIDEO_XO_CLK */
};
static void gcc_qcs8300_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
static const struct qcom_cc_driver_data gcc_qcs8300_driver_data = {
.clk_cbcrs = gcc_qcs8300_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_qcs8300_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_qcs8300_regs_configure,
};
static const struct qcom_cc_desc gcc_qcs8300_desc = {
.driver_data = &gcc_qcs8300_driver_data,
.config = &gcc_qcs8300_regmap_config,
.clks = gcc_qcs8300_clocks,
.num_clks = ARRAY_SIZE(gcc_qcs8300_clocks),
@ -3578,6 +3706,7 @@ static const struct qcom_cc_desc gcc_qcs8300_desc = {
.num_resets = ARRAY_SIZE(gcc_qcs8300_resets),
.gdscs = gcc_qcs8300_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_qcs8300_match_table[] = {
@ -3588,31 +3717,7 @@ MODULE_DEVICE_TABLE(of, gcc_qcs8300_match_table);
static int gcc_qcs8300_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_qcs8300_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_qcs8300_desc, regmap);
return qcom_cc_probe(pdev, &gcc_qcs8300_desc);
}
static struct platform_driver gcc_qcs8300_driver = {
@ -3623,17 +3728,7 @@ static struct platform_driver gcc_qcs8300_driver = {
},
};
static int __init gcc_qcs8300_init(void)
{
return platform_driver_register(&gcc_qcs8300_driver);
}
subsys_initcall(gcc_qcs8300_init);
static void __exit gcc_qcs8300_exit(void)
{
platform_driver_unregister(&gcc_qcs8300_driver);
}
module_exit(gcc_qcs8300_exit);
subsys_platform_driver(gcc_qcs8300_driver);
MODULE_DESCRIPTION("QTI GCC QCS8300 Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-qdu1000.c
View File

@ -2689,17 +2689,7 @@ static struct platform_driver gcc_qdu1000_driver = {
},
};
static int __init gcc_qdu1000_init(void)
{
return platform_driver_register(&gcc_qdu1000_driver);
}
subsys_initcall(gcc_qdu1000_init);
static void __exit gcc_qdu1000_exit(void)
{
platform_driver_unregister(&gcc_qdu1000_driver);
}
module_exit(gcc_qdu1000_exit);
subsys_platform_driver(gcc_qdu1000_driver);
MODULE_DESCRIPTION("QTI GCC QDU1000 Driver");
MODULE_LICENSE("GPL");

56
drivers/clk/qcom/gcc-sa8775p.c
View File

@ -4644,7 +4644,34 @@ static const struct regmap_config gcc_sa8775p_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sa8775p_critical_cbcrs[] = {
0x32004, /* GCC_CAMERA_AHB_CLK */
0x32020, /* GCC_CAMERA_XO_CLK */
0xc7004, /* GCC_DISP1_AHB_CLK */
0xc7018, /* GCC_DISP1_XO_CLK */
0x33004, /* GCC_DISP_AHB_CLK */
0x33018, /* GCC_DISP_XO_CLK */
0x7d004, /* GCC_GPU_CFG_AHB_CLK */
0x34004, /* GCC_VIDEO_AHB_CLK */
0x34024, /* GCC_VIDEO_XO_CLK */
};
static void gcc_sa8775p_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
static const struct qcom_cc_driver_data gcc_sa8775p_driver_data = {
.clk_cbcrs = gcc_sa8775p_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sa8775p_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sa8775p_regs_configure,
};
static const struct qcom_cc_desc gcc_sa8775p_desc = {
.driver_data = &gcc_sa8775p_driver_data,
.config = &gcc_sa8775p_regmap_config,
.clks = gcc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
@ -4652,6 +4679,7 @@ static const struct qcom_cc_desc gcc_sa8775p_desc = {
.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
.gdscs = gcc_sa8775p_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sa8775p_match_table[] = {
@ -4662,33 +4690,7 @@ MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
static int gcc_sa8775p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sa8775p_desc);
}
static struct platform_driver gcc_sa8775p_driver = {

58
drivers/clk/qcom/gcc-sar2130p.c
View File

@ -2300,7 +2300,29 @@ static const struct regmap_config gcc_sar2130p_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sar2130p_critical_cbcrs[] = {
0x37004, /* GCC_DISP_AHB_CLK */
0x42004, /* GCC_VIDEO_AHB_CLK */
0x42028, /* GCC_VIDEO_XO_CLK */
0x9b004, /* GCC_GPU_CFG_AHB_CLK */
};
static void gcc_sar2130p_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x62204, 0x0);
}
static const struct qcom_cc_driver_data gcc_sar2130p_driver_data = {
.clk_cbcrs = gcc_sar2130p_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sar2130p_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sar2130p_regs_configure,
};
static const struct qcom_cc_desc gcc_sar2130p_desc = {
.driver_data = &gcc_sar2130p_driver_data,
.config = &gcc_sar2130p_regmap_config,
.clks = gcc_sar2130p_clocks,
.num_clks = ARRAY_SIZE(gcc_sar2130p_clocks),
@ -2308,6 +2330,7 @@ static const struct qcom_cc_desc gcc_sar2130p_desc = {
.num_resets = ARRAY_SIZE(gcc_sar2130p_resets),
.gdscs = gcc_sar2130p_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sar2130p_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sar2130p_match_table[] = {
@ -2318,28 +2341,7 @@ MODULE_DEVICE_TABLE(of, gcc_sar2130p_match_table);
static int gcc_sar2130p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sar2130p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x9b004); /* GCC_GPU_CFG_AHB_CLK */
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x62204, 0x0);
return qcom_cc_really_probe(&pdev->dev, &gcc_sar2130p_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sar2130p_desc);
}
static struct platform_driver gcc_sar2130p_driver = {
@ -2350,17 +2352,7 @@ static struct platform_driver gcc_sar2130p_driver = {
},
};
static int __init gcc_sar2130p_init(void)
{
return platform_driver_register(&gcc_sar2130p_driver);
}
subsys_initcall(gcc_sar2130p_init);
static void __exit gcc_sar2130p_exit(void)
{
platform_driver_unregister(&gcc_sar2130p_driver);
}
module_exit(gcc_sar2130p_exit);
subsys_platform_driver(gcc_sar2130p_driver);
MODULE_DESCRIPTION("QTI GCC SAR2130P Driver");
MODULE_LICENSE("GPL");

60
drivers/clk/qcom/gcc-sc7180.c
View File

@ -2408,7 +2408,35 @@ static const struct regmap_config gcc_sc7180_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sc7180_critical_cbcrs[] = {
0x48004, /* GCC_CPUSS_GNOC_CLK */
0x0b004, /* GCC_VIDEO_AHB_CLK */
0x0b008, /* GCC_CAMERA_AHB_CLK */
0x0b00c, /* GCC_DISP_AHB_CLK */
0x0b02c, /* GCC_CAMERA_XO_CLK */
0x0b028, /* GCC_VIDEO_XO_CLK */
0x0b030, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
};
static void gcc_sc7180_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Disable the GPLL0 active input to MM blocks, NPU and GPU via MISC registers. */
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
}
static const struct qcom_cc_driver_data gcc_sc7180_driver_data = {
.clk_cbcrs = gcc_sc7180_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc7180_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sc7180_regs_configure,
};
static const struct qcom_cc_desc gcc_sc7180_desc = {
.driver_data = &gcc_sc7180_driver_data,
.config = &gcc_sc7180_regmap_config,
.clk_hws = gcc_sc7180_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
@ -2428,37 +2456,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
static int gcc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to MM blocks, NPU
* and GPU via MISC registers.
*/
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sc7180_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sc7180_desc);
}
static struct platform_driver gcc_sc7180_driver = {

67
drivers/clk/qcom/gcc-sc7280.c
View File

@ -3438,7 +3438,34 @@ static const struct regmap_config gcc_sc7280_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sc7280_critical_cbcrs[] = {
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26028, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x2701c, /* GCC_DISP_XO_CLK */
0x28004, /* GCC_VIDEO_AHB_CLK */
0x28014, /* GCC_VIDEO_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
};
static void gcc_sc7280_regs_configure(struct device *dev, struct regmap *regmap)
{
regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
static const struct qcom_cc_driver_data gcc_sc7280_driver_data = {
.clk_cbcrs = gcc_sc7280_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc7280_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sc7280_regs_configure,
};
static const struct qcom_cc_desc gcc_sc7280_desc = {
.driver_data = &gcc_sc7280_driver_data,
.config = &gcc_sc7280_regmap_config,
.clks = gcc_sc7280_clocks,
.num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
@ -3446,6 +3473,7 @@ static const struct qcom_cc_desc gcc_sc7280_desc = {
.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
.gdscs = gcc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sc7280_match_table[] = {
@ -3456,32 +3484,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
static int gcc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sc7280_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sc7280_desc);
}
static struct platform_driver gcc_sc7280_driver = {
@ -3492,17 +3495,7 @@ static struct platform_driver gcc_sc7280_driver = {
},
};
static int __init gcc_sc7280_init(void)
{
return platform_driver_register(&gcc_sc7280_driver);
}
subsys_initcall(gcc_sc7280_init);
static void __exit gcc_sc7280_exit(void)
{
platform_driver_unregister(&gcc_sc7280_driver);
}
module_exit(gcc_sc7280_exit);
subsys_platform_driver(gcc_sc7280_driver);
MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
MODULE_LICENSE("GPL v2");

47
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -7509,7 +7509,27 @@ static const struct regmap_config gcc_sc8280xp_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sc8280xp_critical_cbcrs[] = {
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26020, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x27028, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x28004, /* GCC_VIDEO_AHB_CLK */
0x28028, /* GCC_VIDEO_XO_CLK */
0xbb004, /* GCC_DISP1_AHB_CLK */
0xbb028, /* GCC_DISP1_XO_CLK */
};
static const struct qcom_cc_driver_data gcc_sc8280xp_driver_data = {
.clk_cbcrs = gcc_sc8280xp_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc8280xp_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
};
static const struct qcom_cc_desc gcc_sc8280xp_desc = {
.driver_data = &gcc_sc8280xp_driver_data,
.config = &gcc_sc8280xp_regmap_config,
.clks = gcc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks),
@ -7538,21 +7558,6 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
goto err_put_rpm;
}
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
goto err_put_rpm;
ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap);
if (ret)
goto err_put_rpm;
@ -7581,17 +7586,7 @@ static struct platform_driver gcc_sc8280xp_driver = {
},
};
static int __init gcc_sc8280xp_init(void)
{
return platform_driver_register(&gcc_sc8280xp_driver);
}
subsys_initcall(gcc_sc8280xp_init);
static void __exit gcc_sc8280xp_exit(void)
{
platform_driver_unregister(&gcc_sc8280xp_driver);
}
module_exit(gcc_sc8280xp_exit);
subsys_platform_driver(gcc_sc8280xp_driver);
MODULE_DESCRIPTION("Qualcomm SC8280XP GCC driver");
MODULE_LICENSE("GPL");

43
drivers/clk/qcom/gcc-sdx55.c
View File

@ -1587,7 +1587,25 @@ static const struct regmap_config gcc_sdx55_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sdx55_critical_cbcrs[] = {
0x6d008, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
};
static void gcc_sdx55_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Keep some clocks always-on */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
}
static const struct qcom_cc_driver_data gcc_sdx55_driver_data = {
.clk_cbcrs = gcc_sdx55_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sdx55_critical_cbcrs),
.clk_regs_configure = gcc_sdx55_regs_configure,
};
static const struct qcom_cc_desc gcc_sdx55_desc = {
.driver_data = &gcc_sdx55_driver_data,
.config = &gcc_sdx55_regmap_config,
.clks = gcc_sdx55_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
@ -1605,18 +1623,7 @@ MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table);
static int gcc_sdx55_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sdx55_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
return qcom_cc_really_probe(&pdev->dev, &gcc_sdx55_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sdx55_desc);
}
static struct platform_driver gcc_sdx55_driver = {
@ -1627,17 +1634,7 @@ static struct platform_driver gcc_sdx55_driver = {
},
};
static int __init gcc_sdx55_init(void)
{
return platform_driver_register(&gcc_sdx55_driver);
}
subsys_initcall(gcc_sdx55_init);
static void __exit gcc_sdx55_exit(void)
{
platform_driver_unregister(&gcc_sdx55_driver);
}
module_exit(gcc_sdx55_exit);
subsys_platform_driver(gcc_sdx55_driver);
MODULE_DESCRIPTION("QTI GCC SDX55 Driver");
MODULE_LICENSE("GPL v2");

43
drivers/clk/qcom/gcc-sdx65.c
View File

@ -1551,7 +1551,25 @@ static const struct regmap_config gcc_sdx65_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sdx65_critical_cbcrs[] = {
0x6d008, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
};
static void gcc_sdx65_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Keep some clocks always-on */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
}
static const struct qcom_cc_driver_data gcc_sdx65_driver_data = {
.clk_cbcrs = gcc_sdx65_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sdx65_critical_cbcrs),
.clk_regs_configure = gcc_sdx65_regs_configure,
};
static const struct qcom_cc_desc gcc_sdx65_desc = {
.driver_data = &gcc_sdx65_driver_data,
.config = &gcc_sdx65_regmap_config,
.clks = gcc_sdx65_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx65_clocks),
@ -1569,18 +1587,7 @@ MODULE_DEVICE_TABLE(of, gcc_sdx65_match_table);
static int gcc_sdx65_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
return qcom_cc_really_probe(&pdev->dev, &gcc_sdx65_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sdx65_desc);
}
static struct platform_driver gcc_sdx65_driver = {
@ -1591,17 +1598,7 @@ static struct platform_driver gcc_sdx65_driver = {
},
};
static int __init gcc_sdx65_init(void)
{
return platform_driver_register(&gcc_sdx65_driver);
}
subsys_initcall(gcc_sdx65_init);
static void __exit gcc_sdx65_exit(void)
{
platform_driver_unregister(&gcc_sdx65_driver);
}
module_exit(gcc_sdx65_exit);
subsys_platform_driver(gcc_sdx65_driver);
MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
MODULE_LICENSE("GPL v2");

44
drivers/clk/qcom/gcc-sdx75.c
View File

@ -2905,7 +2905,20 @@ static const struct regmap_config gcc_sdx75_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sdx75_critical_cbcrs[] = {
0x3e004, /* GCC_AHB_PCIE_LINK_CLK */
0x3e008, /* GCC_XO_PCIE_LINK_CLK */
};
static const struct qcom_cc_driver_data gcc_sdx75_driver_data = {
.clk_cbcrs = gcc_sdx75_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sdx75_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
};
static const struct qcom_cc_desc gcc_sdx75_desc = {
.driver_data = &gcc_sdx75_driver_data,
.config = &gcc_sdx75_regmap_config,
.clks = gcc_sdx75_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx75_clocks),
@ -2913,6 +2926,7 @@ static const struct qcom_cc_desc gcc_sdx75_desc = {
.num_resets = ARRAY_SIZE(gcc_sdx75_resets),
.gdscs = gcc_sdx75_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sdx75_match_table[] = {
@ -2923,23 +2937,7 @@ MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table);
static int gcc_sdx75_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sdx75_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */
qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */
return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sdx75_desc);
}
static struct platform_driver gcc_sdx75_driver = {
@ -2950,17 +2948,7 @@ static struct platform_driver gcc_sdx75_driver = {
},
};
static int __init gcc_sdx75_init(void)
{
return platform_driver_register(&gcc_sdx75_driver);
}
subsys_initcall(gcc_sdx75_init);
static void __exit gcc_sdx75_exit(void)
{
platform_driver_unregister(&gcc_sdx75_driver);
}
module_exit(gcc_sdx75_exit);
subsys_platform_driver(gcc_sdx75_driver);
MODULE_DESCRIPTION("QTI GCC SDX75 Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-shikra.c
View File

@ -4416,17 +4416,7 @@ static struct platform_driver gcc_shikra_driver = {
},
};
static int __init gcc_shikra_init(void)
{
return platform_driver_register(&gcc_shikra_driver);
}
subsys_initcall(gcc_shikra_init);
static void __exit gcc_shikra_exit(void)
{
platform_driver_unregister(&gcc_shikra_driver);
}
module_exit(gcc_shikra_exit);
subsys_platform_driver(gcc_shikra_driver);
MODULE_DESCRIPTION("QTI GCC Shikra Driver");
MODULE_LICENSE("GPL");

77
drivers/clk/qcom/gcc-sm4450.c
View File

@ -140,6 +140,7 @@ static const struct alpha_pll_config gcc_gpll3_config = {
};
static struct clk_alpha_pll gcc_gpll3 = {
.config = &gcc_gpll3_config,
.offset = 0x3000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
@ -2815,7 +2816,41 @@ static const struct regmap_config gcc_sm4450_regmap_config = {
.fast_io = true,
};
static struct clk_alpha_pll *gcc_sm4450_plls[] = {
&gcc_gpll3,
};
static const u32 gcc_sm4450_critical_cbcrs[] = {
0x36004, /* GCC_CAMERA_AHB_CLK */
0x36018, /* GCC_CAMERA_SLEEP_CLK */
0x3601c, /* GCC_CAMERA_XO_CLK */
0x37004, /* GCC_DISP_AHB_CLK */
0x37014, /* GCC_DISP_XO_CLK */
0x81004, /* GCC_GPU_CFG_AHB_CLK */
0x42004, /* GCC_VIDEO_AHB_CLK */
0x42018, /* GCC_VIDEO_XO_CLK */
};
static void gcc_sm4450_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for the UFS PHY ICE core clock */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
}
static const struct qcom_cc_driver_data gcc_sm4450_driver_data = {
.alpha_plls = gcc_sm4450_plls,
.num_alpha_plls = ARRAY_SIZE(gcc_sm4450_plls),
.clk_cbcrs = gcc_sm4450_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm4450_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sm4450_regs_configure,
};
static const struct qcom_cc_desc gcc_sm4450_desc = {
.driver_data = &gcc_sm4450_driver_data,
.config = &gcc_sm4450_regmap_config,
.clks = gcc_sm4450_clocks,
.num_clks = ARRAY_SIZE(gcc_sm4450_clocks),
@ -2823,6 +2858,7 @@ static const struct qcom_cc_desc gcc_sm4450_desc = {
.num_resets = ARRAY_SIZE(gcc_sm4450_resets),
.gdscs = gcc_sm4450_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm4450_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sm4450_match_table[] = {
@ -2833,34 +2869,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm4450_match_table);
static int gcc_sm4450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm4450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gcc_gpll3, regmap, &gcc_gpll3_config);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
return qcom_cc_really_probe(&pdev->dev, &gcc_sm4450_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm4450_desc);
}
static struct platform_driver gcc_sm4450_driver = {
@ -2871,17 +2880,7 @@ static struct platform_driver gcc_sm4450_driver = {
},
};
static int __init gcc_sm4450_init(void)
{
return platform_driver_register(&gcc_sm4450_driver);
}
subsys_initcall(gcc_sm4450_init);
static void __exit gcc_sm4450_exit(void)
{
platform_driver_unregister(&gcc_sm4450_driver);
}
module_exit(gcc_sm4450_exit);
subsys_platform_driver(gcc_sm4450_driver);
MODULE_DESCRIPTION("QTI GCC SM4450 Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-sm6115.c
View File

@ -3525,17 +3525,7 @@ static struct platform_driver gcc_sm6115_driver = {
},
};
static int __init gcc_sm6115_init(void)
{
return platform_driver_register(&gcc_sm6115_driver);
}
subsys_initcall(gcc_sm6115_init);
static void __exit gcc_sm6115_exit(void)
{
platform_driver_unregister(&gcc_sm6115_driver);
}
module_exit(gcc_sm6115_exit);
subsys_platform_driver(gcc_sm6115_driver);
MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/gcc-sm6125.c
View File

@ -4172,17 +4172,7 @@ static struct platform_driver gcc_sm6125_driver = {
},
};
static int __init gcc_sm6125_init(void)
{
return platform_driver_register(&gcc_sm6125_driver);
}
subsys_initcall(gcc_sm6125_init);
static void __exit gcc_sm6125_exit(void)
{
platform_driver_unregister(&gcc_sm6125_driver);
}
module_exit(gcc_sm6125_exit);
subsys_platform_driver(gcc_sm6125_driver);
MODULE_DESCRIPTION("QTI GCC SM6125 Driver");
MODULE_LICENSE("GPL v2");

12
drivers/clk/qcom/gcc-sm6375.c
View File

@ -3903,17 +3903,7 @@ static struct platform_driver gcc_sm6375_driver = {
},
};
static int __init gcc_sm6375_init(void)
{
return platform_driver_register(&gcc_sm6375_driver);
}
subsys_initcall(gcc_sm6375_init);
static void __exit gcc_sm6375_exit(void)
{
platform_driver_unregister(&gcc_sm6375_driver);
}
module_exit(gcc_sm6375_exit);
subsys_platform_driver(gcc_sm6375_driver);
MODULE_DESCRIPTION("QTI GCC SM6375 Driver");
MODULE_LICENSE("GPL");

72
drivers/clk/qcom/gcc-sm7150.c
View File

@ -2966,7 +2966,35 @@ static const struct regmap_config gcc_sm7150_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sm7150_critical_cbcrs[] = {
0x48004, /* GCC_CPUSS_GNOC_CLK */
0x0b004, /* GCC_VIDEO_AHB_CLK */
0x0b008, /* GCC_CAMERA_AHB_CLK */
0x0b00c, /* GCC_DISP_AHB_CLK */
0x0b02c, /* GCC_CAMERA_XO_CLK */
0x0b028, /* GCC_VIDEO_XO_CLK */
0x0b030, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
};
static void gcc_sm7150_regs_configure(struct device *dev, struct regmap *regmap)
{
/* Disable the GPLL0 active input to MM blocks, NPU and GPU via MISC registers. */
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
}
static const struct qcom_cc_driver_data gcc_sm7150_driver_data = {
.clk_cbcrs = gcc_sm7150_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm7150_critical_cbcrs),
.dfs_rcgs = gcc_sm7150_dfs_desc,
.num_dfs_rcgs = ARRAY_SIZE(gcc_sm7150_dfs_desc),
.clk_regs_configure = gcc_sm7150_regs_configure,
};
static const struct qcom_cc_desc gcc_sm7150_desc = {
.driver_data = &gcc_sm7150_driver_data,
.config = &gcc_sm7150_regmap_config,
.clk_hws = gcc_sm7150_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sm7150_hws),
@ -2986,37 +3014,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm7150_match_table);
static int gcc_sm7150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm7150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to MM blocks, NPU
* and GPU via MISC registers.
*/
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc,
ARRAY_SIZE(gcc_sm7150_dfs_desc));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sm7150_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm7150_desc);
}
static struct platform_driver gcc_sm7150_driver = {
@ -3027,17 +3025,7 @@ static struct platform_driver gcc_sm7150_driver = {
},
};
static int __init gcc_sm7150_init(void)
{
return platform_driver_register(&gcc_sm7150_driver);
}
subsys_initcall(gcc_sm7150_init);
static void __exit gcc_sm7150_exit(void)
{
platform_driver_unregister(&gcc_sm7150_driver);
}
module_exit(gcc_sm7150_exit);
subsys_platform_driver(gcc_sm7150_driver);
MODULE_DESCRIPTION("Qualcomm SM7150 Global Clock Controller");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/gcc-sm8150.c
View File

@ -3808,17 +3808,7 @@ static struct platform_driver gcc_sm8150_driver = {
},
};
static int __init gcc_sm8150_init(void)
{
return platform_driver_register(&gcc_sm8150_driver);
}
subsys_initcall(gcc_sm8150_init);
static void __exit gcc_sm8150_exit(void)
{
platform_driver_unregister(&gcc_sm8150_driver);
}
module_exit(gcc_sm8150_exit);
subsys_platform_driver(gcc_sm8150_driver);
MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
MODULE_LICENSE("GPL v2");

69
drivers/clk/qcom/gcc-sm8250.c
View File

@ -3603,6 +3603,15 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static const u32 gcc_sm8250_critical_cbcrs[] = {
0x0b004, /* GCC_VIDEO_AHB_CLK */
0x0b008, /* GCC_CAMERA_AHB_CLK */
0x0b00c, /* GCC_DISP_AHB_CLK */
0x4818c, /* GCC_CPUSS_DVM_BUS_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x52000, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
};
static const struct regmap_config gcc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -3611,6 +3620,24 @@ static const struct regmap_config gcc_sm8250_regmap_config = {
.fast_io = true,
};
static void gcc_sm8250_regs_configure(struct device *dev, struct regmap *regmap)
{
/*
* Disable the GPLL0 active input to NPU and GPU
* via MISC registers.
*/
regmap_set_bits(regmap, 0x4d110, 0x3);
regmap_set_bits(regmap, 0x71028, 0x3);
}
static const struct qcom_cc_driver_data gcc_sm8250_driver_data = {
.clk_cbcrs = gcc_sm8250_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm8250_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sm8250_regs_configure,
};
static const struct qcom_cc_desc gcc_sm8250_desc = {
.config = &gcc_sm8250_regmap_config,
.clks = gcc_sm8250_clocks,
@ -3619,6 +3646,7 @@ static const struct qcom_cc_desc gcc_sm8250_desc = {
.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
.gdscs = gcc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
.driver_data = &gcc_sm8250_driver_data,
};
static const struct of_device_id gcc_sm8250_match_table[] = {
@ -3629,34 +3657,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table);
static int gcc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8250_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to NPU and GPU
* via MISC registers.
*/
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8250_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm8250_desc);
}
static struct platform_driver gcc_sm8250_driver = {
@ -3667,17 +3668,7 @@ static struct platform_driver gcc_sm8250_driver = {
},
};
static int __init gcc_sm8250_init(void)
{
return platform_driver_register(&gcc_sm8250_driver);
}
subsys_initcall(gcc_sm8250_init);
static void __exit gcc_sm8250_exit(void)
{
platform_driver_unregister(&gcc_sm8250_driver);
}
module_exit(gcc_sm8250_exit);
subsys_platform_driver(gcc_sm8250_driver);
MODULE_DESCRIPTION("QTI GCC SM8250 Driver");
MODULE_LICENSE("GPL v2");

65
drivers/clk/qcom/gcc-sm8350.c
View File

@ -3779,7 +3779,32 @@ static const struct regmap_config gcc_sm8350_regmap_config = {
.fast_io = true,
};
static const u32 gcc_sm8350_critical_cbcrs[] = {
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26018, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x2701c, /* GCC_DISP_XO_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x28004, /* GCC_VIDEO_AHB_CLK */
0x28020, /* GCC_VIDEO_XO_CLK */
};
static void gcc_sm8350_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
}
static const struct qcom_cc_driver_data gcc_sm8350_driver_data = {
.clk_cbcrs = gcc_sm8350_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm8350_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sm8350_regs_configure,
};
static const struct qcom_cc_desc gcc_sm8350_desc = {
.driver_data = &gcc_sm8350_driver_data,
.config = &gcc_sm8350_regmap_config,
.clks = gcc_sm8350_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
@ -3787,6 +3812,7 @@ static const struct qcom_cc_desc gcc_sm8350_desc = {
.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
.gdscs = gcc_sm8350_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
.use_rpm = true,
};
static const struct of_device_id gcc_sm8350_match_table[] = {
@ -3797,32 +3823,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
static int gcc_sm8350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map gcc registers\n");
return PTR_ERR(regmap);
}
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8350_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm8350_desc);
}
static struct platform_driver gcc_sm8350_driver = {
@ -3833,17 +3834,7 @@ static struct platform_driver gcc_sm8350_driver = {
},
};
static int __init gcc_sm8350_init(void)
{
return platform_driver_register(&gcc_sm8350_driver);
}
subsys_initcall(gcc_sm8350_init);
static void __exit gcc_sm8350_exit(void)
{
platform_driver_unregister(&gcc_sm8350_driver);
}
module_exit(gcc_sm8350_exit);
subsys_platform_driver(gcc_sm8350_driver);
MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
MODULE_LICENSE("GPL v2");

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