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Amlogic clock updates for v7.4

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* Keep T7 MMC bus clock running when needed
 * A9 SCMI clock controller bindings
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Merge tag 'clk-meson-v7.4-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Amlogic clock updates for v7.4

* Keep T7 MMC bus clock running when needed
* A9 SCMI clock controller bindings
This commit is contained in:
Jerome Brunet 2026-10-10 12:57:13 +02:00
commit 5c62aa1924
2 changed files with 59 additions and 3 deletions
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11
drivers/clk/meson/t7-peripherals.c
View File

@ -947,9 +947,14 @@ static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0);
static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0);
static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0);
static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0);
static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0);
static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0);
static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0);
/*
* NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA between
* the peripherals and the DRAM. After the clocks are disabled, a device that
* starts a transfer cannot complete it.
*/
static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL);
static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0);
static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0);
static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0);

51
include/dt-bindings/clock/amlogic,a9-scmi-clkc.h Normal file
View File

@ -0,0 +1,51 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2026 Amlogic, Inc. All rights reserved.
*/
#ifndef __AMLOGIC_A9_SCMI_CLKC_H
#define __AMLOGIC_A9_SCMI_CLKC_H
#define CLKID_GP0_PLL_OSC 0
#define CLKID_GP1_PLL_OSC 1
#define CLKID_HIFI_PLL_OSC 2
#define CLKID_GP2_PLL_OSC 3
#define CLKID_MCLK_PLL_OSC 4
#define CLKID_FIXED_PLL 5
#define CLKID_FCLK_50M_PREDIV 6
#define CLKID_FCLK_50M_DIV 7
#define CLKID_FCLK_50M 8
#define CLKID_FCLK_DIV2_DIV 9
#define CLKID_FCLK_DIV2 10
#define CLKID_FCLK_DIV2P5_DIV 11
#define CLKID_FCLK_DIV2P5 12
#define CLKID_FCLK_DIV3_DIV 13
#define CLKID_FCLK_DIV3 14
#define CLKID_FCLK_DIV4_DIV 15
#define CLKID_FCLK_DIV4 16
#define CLKID_FCLK_DIV5_DIV 17
#define CLKID_FCLK_DIV5 18
#define CLKID_FCLK_DIV7_DIV 19
#define CLKID_FCLK_DIV7 20
#define CLKID_SYS_CLK 21
#define CLKID_SYS_AO_SYS 22
#define CLKID_SYS_MMC_APB 23
#define CLKID_SYS_CPU_APB 24
#define CLKID_SYS_GIC 25
#define CLKID_AXI_CLK 26
#define CLKID_AXI_SYS_NIC 27
#define CLKID_AXI_RAMA 28
#define CLKID_CPU_CLK 29
#define CLKID_A78_CLK 30
#define CLKID_DSU_CLK 31
#define CLKID_ACLKM 32
#define CLKID_GP1_PLL 33
#define CLKID_GP2_PLL 34
#define CLKID_SYS_PLL_DIV16 35
#define CLKID_CPU_CLK_DIV16 36
#define CLKID_A78_CLK_DIV16 37
#define CLKID_DSU_CLK_DIV16 38
#define CLKID_GIC_CLK 39
#define CLKID_RTC 40
#endif /* __AMLOGIC_A9_SCMI_CLKC_H */