From 43e1705ecab981c66baee89041e6f728c0436f19 Mon Sep 17 00:00:00 2001 From: Lucas Tanure Date: Sat, 29 Aug 2026 10:47:55 +0100 Subject: [PATCH 1/3] clk: meson: t7: keep the memory fabric clocks running Four clocks feed the bus that moves data between the peripherals and memory. Nothing in Linux claims them, so they were switched off shortly after boot, and any device that started a transfer after that point simply stopped. The SD card, which comes up about two seconds in, never finished reading its identification. There is no device these clocks belong to, so mark them as always needed. Fixes: fab4d651b592 ("clk: meson: t7: add t7 clock peripherals controller driver") Assisted-by: Claude:claude-opus-5 Signed-off-by: Lucas Tanure Link: https://patch.msgid.link/20260829094758.23248-2-tanure@linux.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/t7-peripherals.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c index 214db7850d86..55d09e78593b 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -945,11 +945,16 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); +/* + * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI bus + * used for DMA between the peripherals and the DRAM. After the clocks are + * disabled, a device that starts a transfer cannot complete it. + */ +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); -static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0); -static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0); -static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0); +static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); +static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); +static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0); static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0); static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0); From f25652a1c0d0b0d2cf6615f1aa693f7f941aff6a Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Thu, 17 Sep 2026 16:39:09 +0800 Subject: [PATCH 2/3] dt-bindings: clock: Add Amlogic A9 SCMI clock controller Add the SCMI clock controller dt-bindings for the Amlogic A9 SoC family. Acked-by: Conor Dooley Signed-off-by: Jian Hu Link: https://patch.msgid.link/20260917-a9_scmi-v3-1-5ad843766774@amlogic.com Signed-off-by: Jerome Brunet --- .../dt-bindings/clock/amlogic,a9-scmi-clkc.h | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a9-scmi-clkc.h diff --git a/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h new file mode 100644 index 000000000000..d543db9fe035 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AMLOGIC_A9_SCMI_CLKC_H +#define __AMLOGIC_A9_SCMI_CLKC_H + +#define CLKID_GP0_PLL_OSC 0 +#define CLKID_GP1_PLL_OSC 1 +#define CLKID_HIFI_PLL_OSC 2 +#define CLKID_GP2_PLL_OSC 3 +#define CLKID_MCLK_PLL_OSC 4 +#define CLKID_FIXED_PLL 5 +#define CLKID_FCLK_50M_PREDIV 6 +#define CLKID_FCLK_50M_DIV 7 +#define CLKID_FCLK_50M 8 +#define CLKID_FCLK_DIV2_DIV 9 +#define CLKID_FCLK_DIV2 10 +#define CLKID_FCLK_DIV2P5_DIV 11 +#define CLKID_FCLK_DIV2P5 12 +#define CLKID_FCLK_DIV3_DIV 13 +#define CLKID_FCLK_DIV3 14 +#define CLKID_FCLK_DIV4_DIV 15 +#define CLKID_FCLK_DIV4 16 +#define CLKID_FCLK_DIV5_DIV 17 +#define CLKID_FCLK_DIV5 18 +#define CLKID_FCLK_DIV7_DIV 19 +#define CLKID_FCLK_DIV7 20 +#define CLKID_SYS_CLK 21 +#define CLKID_SYS_AO_SYS 22 +#define CLKID_SYS_MMC_APB 23 +#define CLKID_SYS_CPU_APB 24 +#define CLKID_SYS_GIC 25 +#define CLKID_AXI_CLK 26 +#define CLKID_AXI_SYS_NIC 27 +#define CLKID_AXI_RAMA 28 +#define CLKID_CPU_CLK 29 +#define CLKID_A78_CLK 30 +#define CLKID_DSU_CLK 31 +#define CLKID_ACLKM 32 +#define CLKID_GP1_PLL 33 +#define CLKID_GP2_PLL 34 +#define CLKID_SYS_PLL_DIV16 35 +#define CLKID_CPU_CLK_DIV16 36 +#define CLKID_A78_CLK_DIV16 37 +#define CLKID_DSU_CLK_DIV16 38 +#define CLKID_GIC_CLK 39 +#define CLKID_RTC 40 + +#endif /* __AMLOGIC_A9_SCMI_CLKC_H */ From 363f97a1ce635b86be7fd263d56a040fbd87bdbb Mon Sep 17 00:00:00 2001 From: Lucas Tanure Date: Sat, 5 Sep 2026 16:32:34 +0100 Subject: [PATCH 3/3] clk: meson: t7: don't mark sys_ampipe_nand as critical sys_ampipe_nand clocks the pipeline stage inserted in the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric. It does have identifiable consumers - the three MMC controllers - so marking it critical was the wrong tool: the clock should be referenced from the consumer nodes and claimed by the mmc driver instead. Drop the CLK_IS_CRITICAL flag and update the comment accordingly. sys_am2axi0..2 remain critical as they clock the AXI DMA bus itself and have no single identifiable consumer. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260905153234.133217-5-tanure@linux.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/t7-peripherals.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c index 55d09e78593b..2f429ea86796 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -945,13 +945,13 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); -/* - * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI bus - * used for DMA between the peripherals and the DRAM. After the clocks are - * disabled, a device that starts a transfer cannot complete it. - */ -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); +/* + * NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA between + * the peripherals and the DRAM. After the clocks are disabled, a device that + * starts a transfer cannot complete it. + */ static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL);