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Allwinner Clock Changes for 7.4

Browse Source 
Allwinner sunxi-ng clk library's single divider clk type gained support
 for the update bit, and various single divider clks in the A523 driver
 are converted to correctly use the single divider type.
 
 The "wait for lock" helper is changed to use atomic MMIO polling, as it
 could be used when timekeeping is not available yet, and *sleep() doesn't
 work correctly
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Merge tag 'sunxi-clk-for-7.4' into clk-allwinner

Allwinner Clock Changes for 7.4

Allwinner sunxi-ng clk library's single divider clk type gained support
for the update bit, and various single divider clks in the A523 driver
are converted to correctly use the single divider type.

The "wait for lock" helper is changed to use atomic MMIO polling, as it
could be used when timekeeping is not available yet, and *sleep() doesn't
work correctly
This commit is contained in:
Brian Masney 2026-10-09 17:57:10 +02:00
commit e87174b977
4 changed files with 89 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
View File

@ -43,27 +43,24 @@ static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1",
24, 3, /* mux */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
r_ahb_apb_parents, 0x100,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
r_ahb_apb_parents, 0x100,
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
r_ahb_apb_parents, 0x104,
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
r_ahb_apb_parents, 0x108,
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
r_ahb_apb_parents, 0x104,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
r_ahb_apb_parents, 0x108,
0, 0, /* no M */
1, 3, /* P */
4, 3, /* mux */
BIT(0),
0);
static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw,
0x11c, BIT(0), 0);

128
drivers/clk/sunxi-ng/ccu-sun55i-a523.c
View File

@ -380,14 +380,13 @@ static const struct clk_parent_data mbus_parents[] = {
{ .hw = &pll_periph1_150M_clk.hw },
{ .fw_name = "hosc" },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
0x540,
0, 5, /* M */
0, 0, /* no P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL,
CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
0x540,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL,
CCU_FEATURE_UPDATE_BIT);
static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };
@ -513,58 +512,47 @@ static const struct clk_parent_data hstimer_parents[] = {
{ .fw_name = "losc" },
{ .hw = &pll_periph0_200M_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
hstimer_parents, 0x730,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
hstimer_parents, 0x730,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
hstimer_parents,
0x734,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
hstimer_parents, 0x734,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
hstimer_parents,
0x738,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
hstimer_parents, 0x738,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
hstimer_parents,
0x73c,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
hstimer_parents, 0x73c,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
hstimer_parents,
0x740,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
hstimer_parents, 0x740,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
hstimer_parents,
0x744,
0, 0, /* M */
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
hstimer_parents, 0x744,
0, 3, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c,
BIT(0), 0);
@ -584,14 +572,13 @@ static const struct clk_parent_data iommu_parents[] = {
{ .fw_name = "hosc" },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
0x7b0,
0, 5, /* M */
0, 0, /* no P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT,
CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
0x7b0,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT,
CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc,
BIT(0), 0);
@ -603,14 +590,13 @@ static const struct clk_parent_data dram_parents[] = {
{ .hw = &pll_periph0_400M_clk.hw },
{ .hw = &pll_periph0_150M_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
0x800,
0, 5, /* M */
0, 0, /* no P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL,
CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
0x800,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL,
CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
0x804, BIT(0), 0);

2
drivers/clk/sunxi-ng/ccu_common.c
View File

@ -35,7 +35,7 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
else
addr = common->base + common->reg;
WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
WARN_ON(readl_relaxed_poll_timeout_atomic(addr, reg, reg & lock, 100, 70000));
}
EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, "SUNXI_CCU");

18
drivers/clk/sunxi-ng/ccu_div.h
View File

@ -212,16 +212,17 @@ struct ccu_div {
SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
_mshift, _mwidth, 0, _flags)
#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
#define SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags, _features) \
struct ccu_div _struct = { \
.enable = _gate, \
.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.common = { \
.reg = _reg, \
.features = _features, \
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
_parents, \
&ccu_div_ops, \
@ -229,6 +230,15 @@ struct ccu_div {
}, \
}
#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags, 0)
#define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \