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Merge tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi into soc/dt

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ARM64: DT: HiSilicon ARM64 DT updates for 6.2

- Add missing cache-level properties

* tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi:
  arm64: dts: Update cache properties for hisilicon

Link: https://lore.kernel.org/r/63744D38.9010700@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-21 11:43:39 +01:00
commit 4614161b06
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GPG Key ID: 9A6C79EFE60018D9
5 changed files with 28 additions and 0 deletions
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2
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
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@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
A73_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};

2
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -186,10 +186,12 @@ cpu7: cpu@103 {
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View File

@ -211,18 +211,22 @@ cpu15: cpu@20303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@ -211,18 +211,22 @@ cpu15: cpu@10303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
};
};

16
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@ -842,66 +842,82 @@ cpu63: cpu@70303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
cache-level = <2>;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
cache-level = <2>;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
cache-level = <2>;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
cache-level = <2>;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
cache-level = <2>;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
cache-level = <2>;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
cache-level = <2>;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
cache-level = <2>;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
cache-level = <2>;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
cache-level = <2>;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
cache-level = <2>;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
cache-level = <2>;
};
};