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Merge tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

Browse Source 
i.MX arm64 device tree update for 6.2:

- New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK.
- A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan
  support.
- Rename DTB overlay source files from .dts to .dtso.
- A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for
  i.MX8DXL.
- A couple of librem5-devkit changes, switching LED to use PWM and using
  function and color properties for LED.
- Enable wakeup-source for USB PHY for i.MX8MM/N EVK.
- A set of random changes from Marcel Ziswiler to improve i.MX8M based
  Verdin device trees.
- A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and
  DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock
  path, dropping QCA clk_out setup, adding bluetooth UART, etc.
- A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93,
  update i.MX8MP/N EVK with UART, I2C addition.
- Update cache properties per DeviceTree Specification v0.3.
- Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem.
- Misc small and random changes.

* tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits)
  arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
  arm64: dts: imx8mm-evk: add vcc supply for pca6416
  arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
  arm64: dts: imx8mn-evk: enable uart1
  arm64: dts: imx8mn-evk: add i2c gpio recovery settings
  arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
  arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
  arm64: dts: imx8mp-evk: enable I2C2 node
  arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
  arm64: dts: imx8mp-evk: enable uart1/3 ports
  ARM64: dts: imx8mp-evk: add pwm support
  arm64: dts: imx8mp: add mlmix power domain
  arm64: dts: imx8mq: fix dtschema warning for imx7-csi
  arm64: dts: Update cache properties for freescale
  arm64: dts: imx8mm-phg: Add initial board support
  arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
  arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
  arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
  arm64: dts: imx8dxl_evk: add lpspi0 support
  arm64: dts: imx8dxl: add lpspi support
  ...

Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-21 11:40:29 +01:00
commit efa0b8251f
No known key found for this signature in database
GPG Key ID: 9A6C79EFE60018D9
75 changed files with 2309 additions and 148 deletions
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2
arch/arm64/boot/dts/freescale/Makefile
View File

@ -57,10 +57,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso
View File

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso
View File

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso
View File

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso
View File

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso
View File

0
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts → arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso
View File

1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -46,6 +46,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -84,6 +84,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -79,6 +79,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
};
CPU_PW20: cpu-pw20 {

4
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
};
CPU_PW20: cpu-pw20 {

8
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -300,6 +300,7 @@ cpu701: cpu@701 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -308,6 +309,7 @@ cluster0_l2: l2-cache0 {
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -316,6 +318,7 @@ cluster1_l2: l2-cache1 {
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -324,6 +327,7 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -332,6 +336,7 @@ cluster3_l2: l2-cache3 {
cluster4_l2: l2-cache4 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -340,6 +345,7 @@ cluster4_l2: l2-cache4 {
cluster5_l2: l2-cache5 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -348,6 +354,7 @@ cluster5_l2: l2-cache5 {
cluster6_l2: l2-cache6 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -356,6 +363,7 @@ cluster6_l2: l2-cache6 {
cluster7_l2: l2-cache7 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

39
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -34,6 +34,35 @@ conn_ipg_clk: clock-conn-ipg {
clock-output-names = "conn_ipg_clk";
};
usbotg1: usb@5b0d0000 {
compatible = "fsl,imx7ulp-usb";
reg = <0x5b0d0000 0x200>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
clocks = <&usb2_lpcg 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
power-domains = <&pd IMX_SC_R_USB_0>;
status = "disabled";
};
usbmisc1: usbmisc@5b0d0200 {
#index-cells = <1>;
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x5b0d0200 0x200>;
};
usbphy1: usbphy@5b100000 {
compatible = "fsl,imx7ulp-usbphy";
reg = <0x5b100000 0x1000>;
clocks = <&usb2_lpcg 1>;
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
status = "disabled";
};
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
@ -195,4 +224,14 @@ enet1_lpcg: clock-controller@5b240000 {
"enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
usb2_lpcg: clock-controller@5b270000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b270000 0x10000>;
#clock-cells = <1>;
clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
};

164
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
View File

@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg {
clock-output-names = "dma_ipg_clk";
};
lpspi0: spi@5a000000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x5a000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&spi0_lpcg 0>,
<&spi0_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <20000000>;
power-domains = <&pd IMX_SC_R_SPI_0>;
status = "disabled";
};
lpspi1: spi@5a010000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x5a010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&spi1_lpcg 0>,
<&spi1_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
power-domains = <&pd IMX_SC_R_SPI_1>;
status = "disabled";
};
lpspi2: spi@5a020000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x5a020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&spi2_lpcg 0>,
<&spi2_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
power-domains = <&pd IMX_SC_R_SPI_2>;
status = "disabled";
};
lpspi3: spi@5a030000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x5a030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&spi3_lpcg 0>,
<&spi3_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
power-domains = <&pd IMX_SC_R_SPI_3>;
status = "disabled";
};
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@ -60,6 +124,54 @@ lpuart3: serial@5a090000 {
status = "disabled";
};
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "spi0_lpcg_clk",
"spi0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SPI_0>;
};
spi1_lpcg: clock-controller@5a410000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a410000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "spi1_lpcg_clk",
"spi1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SPI_1>;
};
spi2_lpcg: clock-controller@5a420000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a420000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "spi2_lpcg_clk",
"spi2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SPI_2>;
};
spi3_lpcg: clock-controller@5a430000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a430000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "spi3_lpcg_clk",
"spi3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SPI_3>;
};
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
@ -156,6 +268,34 @@ i2c3: i2c@5a830000 {
status = "disabled";
};
adc0: adc@5a880000 {
compatible = "nxp,imx8qxp-adc";
reg = <0x5a880000 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adc0_lpcg 0>,
<&adc0_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_ADC_0>;
status = "disabled";
};
adc1: adc@5a890000 {
compatible = "nxp,imx8qxp-adc";
reg = <0x5a890000 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adc1_lpcg 0>,
<&adc1_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_ADC_1>;
status = "disabled";
};
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@ -203,4 +343,28 @@ i2c3_lpcg: clock-controller@5ac30000 {
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
adc0_lpcg: clock-controller@5ac80000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac80000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "adc0_lpcg_clk",
"adc0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_0>;
};
adc1_lpcg: clock-controller@5ac90000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac90000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "adc1_lpcg_clk",
"adc1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_1>;
};
};

17
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
<0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
flexspi0: spi@5d120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8qxp-fspi";
reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
clock-names = "fspi", "fspi_en";
power-domains = <&pd IMX_SC_R_FSPI_0>;
status = "disabled";
};
lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

107
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -90,6 +90,28 @@ reg_usdhc2_vmmc: regulator-3 {
enable-active-high;
off-on-delay-us = <3480>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
mii_select: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "mii-select";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&adc0 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&eqos {
@ -159,6 +181,23 @@ vddio1: vddio-regulator {
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
nxp,fspi-dll-slvdly = <4>;
status = "okay";
mt35xu512aba0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@ -266,6 +305,40 @@ map0 {
};
};
&usbphy1 {
/* USB eye diagram tests result */
fsl,tx-d-cal = <114>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usbphy2 {
/* USB eye diagram tests result */
fsl,tx-d-cal = <111>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -286,6 +359,21 @@ &usdhc2 {
status = "okay";
};
&lpspi3 {
fsl,spi-num-chipselects = <1>;
fsl,spi-only-use-cs1-sel;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@ -330,6 +418,25 @@ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0

20
arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
View File

@ -11,6 +11,10 @@ &dma_ipg_clk {
clock-frequency = <160000000>;
};
&adc0 {
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
@ -50,3 +54,19 @@ &lpuart3 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};
&lpspi0 {
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
};
&lpspi1 {
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
};
&lpspi2 {
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
};
&lpspi3 {
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
};

10
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@ -140,3 +140,13 @@ &usdhc3 {
compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
&usbotg1 {
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
/*
* usbotg1 and usbotg2 share one clock
* scfw disable clock access and keep it always on
* in case other core (M4) use one of these.
*/
clocks = <&clk_dummy>;
};

46
arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
View File

@ -3,44 +3,90 @@
* Copyright 2019~2020, 2022 NXP
*/
&flexspi0 {
compatible = "nxp,imx8dxl-fspi";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
&lsio_gpio0 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 47 13>,
<&iomuxc 13 61 4>,
<&iomuxc 19 67 4>,
<&iomuxc 24 72 1>;
};
&lsio_gpio1 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 4 74 5>,
<&iomuxc 9 80 16>;
};
&lsio_gpio2 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 1 98 2>,
<&iomuxc 3 101 1>,
<&iomuxc 5 107 8>;
};
&lsio_gpio3 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 115 4>,
<&iomuxc 9 121 1>,
<&iomuxc 10 120 1>,
<&iomuxc 11 123 1>,
<&iomuxc 12 122 1>,
<&iomuxc 13 125 1>,
<&iomuxc 14 124 1>,
<&iomuxc 16 126 1>,
<&iomuxc 17 128 1>,
<&iomuxc 18 131 1>,
<&iomuxc 19 130 1>,
<&iomuxc 20 133 1>,
<&iomuxc 21 132 1>,
<&iomuxc 22 129 1>,
<&iomuxc 23 134 1>;
};
&lsio_gpio4 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 0 3>,
<&iomuxc 3 4 4>,
<&iomuxc 7 9 12>,
<&iomuxc 19 22 2>,
<&iomuxc 21 25 2>,
<&iomuxc 29 29 3>;
};
&lsio_gpio5 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 32 3>,
<&iomuxc 3 36 6>,
<&iomuxc 9 43 3>;
};
&lsio_gpio6 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 53 7>,
<&iomuxc 8 86 10>,
<&iomuxc 19 107 8>;
};
&lsio_gpio7 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 0 3>,
<&iomuxc 3 4 4>,
<&iomuxc 8 22 2>,
<&iomuxc 10 25 2>,
<&iomuxc 16 44 2>;
};
&lsio_mu0 {

7
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@ -59,6 +59,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};
@ -133,6 +134,12 @@ clk: clock-controller {
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
scu_gpio: gpio {
compatible = "fsl,imx8qxp-sc-gpio";
gpio-controller;
#gpio-cells = <2>;
};
iomuxc: pinctrl {
compatible = "fsl,imx8dxl-iomuxc";
};

6
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
View File

@ -47,15 +47,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
View File

@ -46,6 +46,12 @@ clk_xtal25: clk-xtal25 {
clock-frequency = <25000000>;
};
clk_xtal32k: clk-xtal32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
panel: panel {
backlight = <&backlight>;
power-supply = <&reg_panel_vcc>;
@ -77,12 +83,11 @@ reg_usdhc2_vcc: regulator-usdhc2-vcc {
enable-active-high;
};
watchdog-gpio {
watchdog {
/* TPS3813 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
compatible = "linux,wdt-gpio";
always-enabled;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 2..3 seconds */
@ -114,15 +119,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -183,8 +188,6 @@ fec1_phy: ethernet-phy@0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
@ -271,6 +274,9 @@ &i2c1 {
pmic: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
#clock-cells = <0>;
clocks = <&clk_xtal32k 0>;
clock-output-names = "clk-32k-out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
@ -928,6 +934,10 @@ &sai5 {
status = "disabled";
};
&snvs_rtc {
clocks = <&pmic>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;

6
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View File

@ -23,15 +23,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -56,6 +56,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
@ -343,6 +344,7 @@ pca6416: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&buck4_reg>;
};
};
@ -399,6 +401,10 @@ &uart2 { /* console */
status = "okay";
};
&usbphynop1 {
wakeup-source;
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;

146
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts Normal file
View File

@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Bang & Olufsen
* Copyright 2022 Pengutronix
*/
/dts-v1/;
#include "imx8mm-innocomm-wb15.dtsi"
/ {
model = "InnoComm WB15-EVK";
compatible = "innocomm,wb15-evk", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
label = "debug";
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_vsd_3v3: regulator-vsd-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_ethphy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy_reg>;
regulator-name = "PHY_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_ethphy>;
};
};
};
&uart2 {
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
status = "okay";
};
&usdhc2 {
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_vsd_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_fec: fec-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_fec_phy: fec-phy-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec_phy_reg: fec-phy-reg-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
>;
};
pinctrl_gpio_leds: led-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
>;
};
pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
};

480
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi Normal file
View File

@ -0,0 +1,480 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Bang & Olufsen
*/
#include "imx8mm.dtsi"
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
reg_modem: regulator-modem {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_modem_regulator>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "epdev_on";
gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_3v3_out: regulator-3v3-out {
compatible = "regulator-fixed";
regulator-name = "3V3_OUT";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <105000>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <850000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <850000>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
// buck5 in datasheet
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
// buck6 in datasheet
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
// buck7 in datasheet
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
// buck8 in datasheet
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
fsl,max-link-speed = <1>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4349-bt";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_modem_bt>;
device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
vbat-supply = <&reg_3v3_out>;
vddio-supply = <&reg_3v3_out>;
clocks = <&osc_32k>;
max-speed = <3000000>;
clock-names = "extclk";
};
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
&iomuxc {
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_pcie0: pcie0-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6
>;
};
pinctrl_modem_bt: modem-bt-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
>;
};
pinctrl_modem_regulator: modem-reg-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41
>;
};
pinctrl_pmic: pmic-irq-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_wdog: wdog-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View File

@ -47,11 +47,11 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
View File

@ -46,11 +46,11 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

266
arch/arm64/boot/dts/freescale/imx8mm-phg.dts Normal file
View File

@ -0,0 +1,266 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Fabio Estevam <festevam@denx.de>
*/
/dts-v1/;
#include "imx8mm-tqma8mqml.dtsi"
/ {
model = "Cloos i.MX8MM PHG board";
compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart2;
};
beeper {
compatible = "gpio-beeper";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
label = "status1";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
led-1 {
label = "status2";
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
led-2 {
label = "status3";
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
led-3 {
label = "run";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
led-4 {
label = "powerled";
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
};
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbphynop1 {
power-domains = <&pgc_otg1>;
};
&usbphynop2 {
power-domains = <&pgc_otg2>;
};
&usbotg1 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
sd-uhs-sdr104;
sd-uhs-ddr50;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_beeper: beepergrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
View File

@ -53,15 +53,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
View File

@ -53,15 +53,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};

30
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
View File

@ -81,15 +81,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -119,8 +119,11 @@ ethphy0: ethernet-phy@0 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -365,8 +368,11 @@ ldo4 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@52 {
@ -435,6 +441,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -442,6 +455,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso
View File

0
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts → arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso
View File

54
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@ -248,15 +248,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -326,8 +326,11 @@ &gpu_3d {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -477,8 +480,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -600,8 +606,11 @@ LDO6 {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
leds_gpio: gpio@20 {
@ -673,8 +682,11 @@ crypto@60 {
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -852,6 +864,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -859,6 +878,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -866,6 +892,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -873,6 +906,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41

66
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@ -198,15 +198,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -261,7 +261,7 @@ ethphy0: ethernet-phy@0 {
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@ -283,7 +283,8 @@ &gpio3 {
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
"lte_pwr#", "lte_rst", "lte_int", "",
"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@ -298,8 +299,11 @@ &gpio5 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -566,8 +570,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -585,16 +592,22 @@ accelerometer@19 {
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -738,14 +751,19 @@ &iomuxc {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@ -779,8 +797,6 @@ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@ -797,6 +813,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -804,6 +827,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -811,6 +841,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -818,6 +855,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19

42
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@ -207,15 +207,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -265,8 +265,11 @@ &gpio5 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -397,8 +400,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -520,8 +526,11 @@ LDO6 {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -681,6 +690,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -688,6 +704,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -695,6 +718,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19

54
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
View File

@ -266,15 +266,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -315,8 +315,11 @@ &gpio5 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -441,8 +444,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@ -564,8 +570,11 @@ LDO6 {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -582,8 +591,11 @@ accelerometer@19 {
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gpioled: gpio@27 {
@ -738,6 +750,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -745,6 +764,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -752,6 +778,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -759,6 +792,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41

16
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -3,8 +3,8 @@
* Copyright 2022 Toradex
*/
#include "dt-bindings/phy/phy-imx8-pcie.h"
#include "dt-bindings/pwm/pwm.h"
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mm.dtsi"
/ {
@ -183,15 +183,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -610,7 +610,7 @@ atmel_mxt_ts: touch@4a {
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
@ -653,7 +653,8 @@ &pcie0 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
pinctrl-names = "default";
@ -664,6 +665,7 @@ &pcie0 {
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;

6
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@ -573,9 +574,10 @@ fec_mac_address: mac-address@90 {
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mm-anatop", "syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {

6
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
View File

@ -55,15 +55,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-800M {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View File

@ -35,15 +35,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-600M {
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
};

3
arch/arm64/boot/dts/freescale/imx8mn-evk.dts
View File

@ -47,6 +47,7 @@ buck1: BUCK1{
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-standby-voltage = <750000>;
};
buck2: BUCK2 {
@ -56,8 +57,6 @@ buck2: BUCK2 {
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{

47
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -36,6 +36,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
};
@ -159,8 +160,11 @@ &i2c1 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
ptn5110: tcpc@50 {
@ -195,8 +199,11 @@ typec1_con: connector {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
@ -240,6 +247,15 @@ &spdif1 {
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MN_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@ -255,6 +271,10 @@ &uart3 {
status = "okay";
};
&usbphynop1 {
wakeup-source;
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@ -369,6 +389,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -376,6 +403,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
@ -419,6 +453,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

62
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@ -189,15 +189,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -256,7 +256,7 @@ ethphy0: ethernet-phy@0 {
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@ -278,7 +278,7 @@ &gpio3 {
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "app_gpio1", "", "uart1_rs485",
"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@ -297,8 +297,11 @@ &gpu {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -565,8 +568,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -584,16 +590,22 @@ accelerometer@19 {
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -689,10 +701,12 @@ &iomuxc {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@ -726,8 +740,6 @@ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@ -744,6 +756,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@ -751,6 +770,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@ -758,6 +784,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@ -765,6 +798,13 @@ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19

7
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@ -576,10 +577,10 @@ fec_mac_address: mac-address@90 {
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
"syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {

31
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -427,6 +427,24 @@ &uart2 {
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
/*
* PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
* which with 16x oversampling yields 4 Mbdps baud base,
* which is exactly the maximum rate supported by muRata
* 2AE bluetooth UART.
*/
assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <320000000>, <64000000>;
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
compatible = "cypress,cyw4373a0-bt";
shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
};
};
&uart3 {
@ -849,6 +867,13 @@ MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
>;
};
pinctrl_uart2_bt: dhcom-uart2-bt-grp {
fsl,pins = <
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
>;
};
pinctrl_uart3: dhcom-uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
@ -886,8 +911,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@ -901,8 +924,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@ -916,8 +937,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;

111
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -85,6 +85,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
@ -317,6 +331,13 @@ LDO5 {
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -390,10 +411,37 @@ &pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
@ -416,6 +464,15 @@ &usb_dwc3_1 {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@ -515,6 +572,17 @@ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
@ -528,6 +596,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@ -567,12 +642,39 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
@ -586,6 +688,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190

159
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@ -8,6 +8,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-tqma8mpql.dtsi"
@ -48,6 +49,27 @@ backlight_lvds: backlight {
status = "disabled";
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwmfan>;
fan-supply = <&reg_pwm_fan>;
#cooling-cells = <2>;
/* typical 25 kHz -> 40.000 nsec */
pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
cooling-levels = <0 32 64 128 196 240>;
pulses-per-revolution = <2>;
interrupt-parent = <&gpio5>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -108,6 +130,18 @@ display: display {
status = "disabled";
};
reg_pwm_fan: regulator-pwm-fan {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regpwmfan>;
regulator-name = "FAN_PWR";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vcc_12v0>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -165,6 +199,47 @@ linux,cma {
linux,cma-default;
};
};
thermal-zones {
soc-thermal {
trips {
soc_active0: trip-active0 {
temperature = <40000>;
hysteresis = <5000>;
type = "active";
};
soc_active1: trip-active1 {
temperature = <48000>;
hysteresis = <3000>;
type = "active";
};
soc_active2: trip-active2 {
temperature = <60000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&soc_active0>;
cooling-device = <&fan0 1 1>;
};
map2 {
trip = <&soc_active1>;
cooling-device = <&fan0 2 2>;
};
map3 {
trip = <&soc_active2>;
cooling-device = <&fan0 3 3>;
};
};
};
};
};
&ecspi1 {
@ -340,9 +415,16 @@ &gpio4 {
"", "", "", "",
"", "", "", "",
"", "", "DP_IRQ", "DSI_EN",
"HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
"HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",
"", "", "", "FAN_PWR",
"RTC_EVENT#", "CODEC_RST#", "", "";
pcie-refclkreq-hog {
gpio-hog;
gpios = <22 0>;
output-high;
line-name = "PCIE_REFCLK_OE#";
};
};
&gpio5 {
@ -377,6 +459,13 @@ at24c02_54: eeprom@54 {
pagesize = <16>;
vcc-supply = <&reg_vcc_3v3>;
};
pcieclk: clock-generator@6a {
compatible = "renesas,9fgv0241";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c4 {
@ -407,6 +496,25 @@ &pcf85063 {
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
};
&pcie_phy {
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcieclk 0>;
clock-names = "ref";
status = "okay";
};
&pcie {
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
@ -461,11 +569,23 @@ &usb3_0 {
status = "okay";
};
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
dr_mode = "host";
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_vcc_5v0>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_vcc_5v0>;
status = "okay";
};
&usb_dwc3_0 {
/* dual role is implemented, but not a full featured OTG */
hnp-disable;
@ -486,6 +606,31 @@ connector {
};
};
&usb_dwc3_1 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhub>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb451,8142";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_vcc_3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8140";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_vcc_3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@ -685,10 +830,18 @@ pinctrl_pwm3: pwm3grp {
fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>;
};
pinctrl_pwmfan: pwmfangrp {
fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */
};
pinctrl_reg12v0: reg12v0grp {
fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */
};
pinctrl_regpwmfan: regpwmfangrp {
fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>;
};
/* X61 */
pinctrl_uart1: uart1grp {
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>,
@ -720,6 +873,10 @@ pinctrl_usbcon0: usb0congrp {
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>;
};
pinctrl_usbhub: usbhubgrp {
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,

48
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -253,8 +253,11 @@ &gpio5 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@ -477,8 +480,11 @@ rtc@68 {
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@ -556,16 +562,22 @@ fixed-link {
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -800,6 +812,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
@ -807,6 +826,13 @@ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@ -814,6 +840,13 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
@ -821,6 +854,13 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */

1
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
View File

@ -116,6 +116,7 @@ &usb3_phy0 {
/* Verdin USB_2 */
&usb3_1 {
fsl,permanently-attached;
status = "okay";
};

49
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@ -3,7 +3,8 @@
* Copyright 2022 Toradex
*/
#include "dt-bindings/pwm/pwm.h"
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp.dtsi"
/ {
@ -678,8 +679,8 @@ gpio_expander_21: gpio-expander@21 {
status = "disabled";
};
lvds_ti_sn65dsi83: bridge@2c {
compatible = "ti,sn65dsi83";
lvds_ti_sn65dsi84: bridge@2c {
compatible = "ti,sn65dsi84";
/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
@ -712,7 +713,7 @@ atmel_mxt_ts: touch@4a {
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio4>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
@ -806,28 +807,45 @@ &uart4 {
};
/* Verdin USB_1 */
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
&usb3_0 {
fsl,disable-port-power-control;
fsl,over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_oc_n>;
};
&usb_dwc3_0 {
/* dual role only, not full featured OTG */
adp-disable;
dr_mode = "otg";
hnp-disable;
maximum-speed = "high-speed";
over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_id>;
role-switch-default-mode = "peripheral";
srp-disable;
usb-role-switch;
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
label = "Type-C";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_id>;
self-powered;
type = "micro";
vbus-supply = <&reg_usb1_vbus>;
};
};
/* Verdin USB_2 */
&usb3_1 {
fsl,disable-port-power-control;
};
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
};
&usb_dwc3_1 {
disable-over-current;
dr_mode = "host";
};
@ -1045,7 +1063,6 @@ pinctrl_gpio_hog2: gpiohog2grp {
pinctrl_gpio_hog3: gpiohog3grp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
/* CSI_1_MCLK */
<MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
};
@ -1220,7 +1237,7 @@ pinctrl_uart4: uart4grp {
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
};
/* USB_1_ID */
@ -1229,9 +1246,15 @@ pinctrl_usb_1_id: usb1idgrp {
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
};
/* USB_1_OC# */
pinctrl_usb_1_oc_n: usb1ocngrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
};
pinctrl_usb2_vbus: usb2vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
};
/* On-module Wi-Fi */

34
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -123,6 +123,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
@ -441,10 +442,10 @@ eth_mac2: mac-address@96 {
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
"syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@ -631,6 +632,14 @@ pgc_vpu_vc8000e: power-domain@22 {
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
pgc_mlmix: power-domain@24 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
};
};
};
@ -705,12 +714,15 @@ aips3: bus@30800000 {
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@ -719,12 +731,15 @@ ecspi1: spi@30820000 {
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@ -733,12 +748,15 @@ ecspi2: spi@30830000 {
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@ -1063,11 +1081,11 @@ noc: interconnect@32700000 {
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200M {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp-1000M {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
};
};

9
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -46,6 +46,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
@ -163,22 +164,22 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
/*
* On imx8mq B0 PLL can't be bypassed so low bus is 166M
*/
opp-166M {
opp-166000000 {
opp-hz = /bits/ 64 <166935483>;
};
opp-800M {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};

22
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -7,6 +7,7 @@
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "imx8mq.dtsi"
@ -61,14 +62,13 @@ button-3 {
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
compatible = "pwm-leds";
led1 {
label = "LED 1";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
default-state = "off";
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
max-brightness = <248>;
pwms = <&pwm2 0 50000 0>;
};
};
@ -615,9 +615,9 @@ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
>;
};
pinctrl_gpio_leds: gpioledgrp {
pinctrl_pwm_led: pwmledgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>;
};
@ -920,6 +920,12 @@ &pwm1 {
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_led>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};

6
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -311,15 +311,15 @@ &ddrc {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-800M {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
View File

@ -220,12 +220,14 @@ eeprom1: eeprom@53 {
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&reg_vcc3v3>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_vcc3v3>;
};
};

16
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -179,6 +179,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -605,10 +606,11 @@ fec_mac_address: mac-address@90 {
};
};
anatop: syscon@30360000 {
compatible = "fsl,imx8mq-anatop", "syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mq-anatop";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@ -1184,7 +1186,7 @@ csi1_mipi_ep: endpoint {
};
csi1: csi@30a90000 {
compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
compatible = "fsl,imx8mq-csi";
reg = <0x30a90000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
@ -1236,7 +1238,7 @@ csi2_mipi_ep: endpoint {
};
csi2: csi@30b80000 {
compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
compatible = "fsl,imx8mq-csi";
reg = <0x30b80000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
@ -1356,15 +1358,15 @@ noc: interconnect@32700000 {
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133M {
opp-133000000 {
opp-hz = /bits/ 64 <133333333>;
};
opp-400M {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp-800M {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};

38
arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
View File

@ -6,30 +6,68 @@
&lsio_gpio0 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 0 6>,
<&iomuxc 6 7 22>,
<&iomuxc 28 36 4>;
};
&lsio_gpio1 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 40 4>,
<&iomuxc 4 50 12>,
<&iomuxc 16 63 8>,
<&iomuxc 24 72 8>;
};
&lsio_gpio2 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 80 4>,
<&iomuxc 4 85 18>,
<&iomuxc 22 104 10>;
};
&lsio_gpio3 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 114 2>,
<&iomuxc 2 117 16>,
<&iomuxc 18 141 1>,
<&iomuxc 19 140 1>,
<&iomuxc 20 139 1>,
<&iomuxc 21 138 1>,
<&iomuxc 22 137 1>,
<&iomuxc 23 136 1>,
<&iomuxc 24 135 1>,
<&iomuxc 25 134 1>,
<&iomuxc 26 142 3>,
<&iomuxc 29 146 3>;
};
&lsio_gpio4 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 149 3>,
<&iomuxc 3 153 4>,
<&iomuxc 7 158 6>,
<&iomuxc 13 165 6>,
<&iomuxc 19 172 8>,
<&iomuxc 27 198 5>;
};
&lsio_gpio5 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 203 1>,
<&iomuxc 1 205 2>,
<&iomuxc 3 210 11>,
<&iomuxc 14 223 3>,
<&iomuxc 17 227 2>,
<&iomuxc 19 230 5>,
<&iomuxc 24 236 6>,
<&iomuxc 30 243 2>;
};
&lsio_gpio6 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 245 10>,
<&iomuxc 10 256 12>;
};
&lsio_gpio7 {

2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -136,6 +136,7 @@ A72_1: cpu@101 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@ -144,6 +145,7 @@ A53_L2: l2-cache0 {
A72_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

2
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
View File

@ -3,7 +3,7 @@
* Copyright 2019 Toradex
*/
#include "dt-bindings/input/linux-event-codes.h"
#include <dt-bindings/input/linux-event-codes.h>
/ {
aliases {

25
arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
View File

@ -6,26 +6,51 @@
&lsio_gpio0 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 1 56 12>,
<&iomuxc 13 69 4>,
<&iomuxc 19 75 4>,
<&iomuxc 24 80 1>,
<&iomuxc 25 82 7>;
};
&lsio_gpio1 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 89 9>,
<&iomuxc 9 99 16>,
<&iomuxc 25 116 7>;
};
&lsio_gpio2 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 123 1>,
<&iomuxc 1 126 2>,
<&iomuxc 3 129 1>;
};
&lsio_gpio3 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 146 4>,
<&iomuxc 4 151 13>,
<&iomuxc 17 165 8>;
};
&lsio_gpio4 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 0 3>,
<&iomuxc 3 4 4>,
<&iomuxc 7 9 6>,
<&iomuxc 13 16 6>,
<&iomuxc 19 23 2>,
<&iomuxc 21 26 2>,
<&iomuxc 23 30 6>,
<&iomuxc 29 37 3>;
};
&lsio_gpio5 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
gpio-ranges = <&iomuxc 0 40 3>,
<&iomuxc 3 44 6>,
<&iomuxc 9 51 3>;
};
&lsio_gpio6 {

1
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -127,6 +127,7 @@ A35_3: cpu@3 {
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>;

1
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -51,6 +51,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

111
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -17,6 +17,10 @@ / {
#size-cells = <2>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
@ -135,6 +139,7 @@ mu1: mailbox@44230000 {
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x44230000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_MU1_B_GATE>;
#mbox-cells = <2>;
status = "disabled";
};
@ -145,6 +150,15 @@ system_counter: timer@44290000 {
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
nxp,no-divider;
};
tpm2: pwm@44320000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x44320000 0x10000>;
clocks = <&clk IMX93_CLK_TPM2_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
lpi2c1: i2c@44340000 {
@ -270,10 +284,35 @@ mu2: mailbox@42440000 {
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x42440000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_MU2_B_GATE>;
#mbox-cells = <2>;
status = "disabled";
};
tpm4: pwm@424f0000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x424f0000 0x10000>;
clocks = <&clk IMX93_CLK_TPM4_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
tpm5: pwm@42500000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x42500000 0x10000>;
clocks = <&clk IMX93_CLK_TPM5_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
tpm6: pwm@42510000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x42510000 0x10000>;
clocks = <&clk IMX93_CLK_TPM6_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
lpi2c3: i2c@42530000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42530000 0x10000>;
@ -294,6 +333,30 @@ lpi2c4: i2c@42540000 {
status = "disabled";
};
lpspi3: spi@42550000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42550000 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi4: spi@42560000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42560000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpuart3: serial@42570000 {
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42570000 0x1000>;
@ -388,6 +451,54 @@ lpi2c8: i2c@426e0000 {
status = "disabled";
};
lpspi5: spi@426f0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x426f0000 0x10000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi6: spi@42700000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42700000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi7: spi@42710000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42710000 0x10000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi8: spi@42720000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42720000 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
};
aips3: bus@42800000 {

1
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@ -215,6 +215,7 @@ eeprom3: eeprom@57 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
vcc-supply = <&reg_vcc_3v3>;
};
};

2
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@ -52,10 +52,12 @@ cpu3: cpu@101 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};

2
arch/arm64/boot/dts/freescale/s32v234.dtsi
View File

@ -61,10 +61,12 @@ cpu3: cpu@101 {
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};