From ca69b6c78d5d6cd9a4417d279eda1d2cd2fb3829 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 15 Sep 2022 08:28:55 +0200 Subject: [PATCH 01/60] arm64: dts: tqma8mpql: add support for 2nd USB (host) interface The on-board USB hub has a single reset line which needs to be enabled. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 7bf6f81e87b4..1c440909f580 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -461,11 +461,23 @@ &usb3_0 { status = "okay"; }; +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; + dr_mode = "host"; + status = "okay"; +}; + &usb3_phy0 { vbus-supply = <®_vcc_5v0>; status = "okay"; }; +&usb3_phy1 { + vbus-supply = <®_vcc_5v0>; + status = "okay"; +}; + &usb_dwc3_0 { /* dual role is implemented, but not a full featured OTG */ hnp-disable; @@ -486,6 +498,31 @@ connector { }; }; +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -720,6 +757,10 @@ pinctrl_usbcon0: usb0congrp { fsl,pins = ; }; + pinctrl_usbhub: usbhubgrp { + fsl,pins = ; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = , , From 3fff54653ac2d6fd11fcbb3a303abb2e050c799b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 21 Sep 2022 09:08:33 +0200 Subject: [PATCH 02/60] arm64: dts: tqma8mq-mba8mx: Add vcc supply to i2c eeproms Fixes the warnings: at24 0-0053: supply vcc not found, using dummy regulator at24 0-0057: supply vcc not found, using dummy regulator at24 1-0057: supply vcc not found, using dummy regulator Signed-off-by: Alexander Stein Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi | 2 ++ arch/arm64/boot/dts/freescale/mba8mx.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 802ad6e5cef6..9a95e30fb42d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -220,12 +220,14 @@ eeprom1: eeprom@53 { reg = <0x53>; pagesize = <16>; read-only; + vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + vcc-supply = <®_vcc3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 104bdd4e437a..daa37adeff3b 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -215,6 +215,7 @@ eeprom3: eeprom@57 { compatible = "nxp,se97b", "atmel,24c02"; reg = <0x57>; pagesize = <16>; + vcc-supply = <®_vcc_3v3>; }; }; From 19d0fc9e973406b32573ff683eda1b70b6d72c26 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 21 Sep 2022 09:46:20 -0700 Subject: [PATCH 03/60] arm64: dts: imx8m*-venice: add I2C GPIO bus recovery support Add I2C GPIO bus recovery support by adding scl-gpios and sda-gpios for the various I2C busses on Gateworks Venice boards. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-venice-gw700x.dtsi | 24 +++++++++- .../dts/freescale/imx8mm-venice-gw7901.dts | 48 +++++++++++++++++-- .../dts/freescale/imx8mm-venice-gw7902.dts | 48 +++++++++++++++++-- .../dts/freescale/imx8mm-venice-gw7903.dts | 36 ++++++++++++-- .../dts/freescale/imx8mm-venice-gw7904.dts | 48 +++++++++++++++++-- .../dts/freescale/imx8mn-venice-gw7902.dts | 48 +++++++++++++++++-- .../dts/freescale/imx8mp-venice-gw74xx.dts | 48 +++++++++++++++++-- 7 files changed, 275 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 66a0d103c90f..c305e325d007 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -119,8 +119,11 @@ ethphy0: ethernet-phy@0 { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -365,8 +368,11 @@ ldo4 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; eeprom@52 { @@ -435,6 +441,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -442,6 +455,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index d3ee6fc4baab..826627bd4503 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -326,8 +326,11 @@ &gpu_3d { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -600,8 +606,11 @@ LDO6 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; leds_gpio: gpio@20 { @@ -673,8 +682,11 @@ crypto@60 { &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -852,6 +864,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -859,6 +878,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -866,6 +892,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -873,6 +906,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 31f4c735fe4f..0359dca031c8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -298,8 +298,11 @@ &gpio5 { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -566,8 +569,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -585,16 +591,22 @@ accelerometer@19 { /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -797,6 +809,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -804,6 +823,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -811,6 +837,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -818,6 +851,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 19f6d2943d26..1ec91c5c6a49 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -265,8 +265,11 @@ &gpio5 { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -397,8 +400,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -520,8 +526,11 @@ LDO6 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -681,6 +690,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -688,6 +704,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -695,6 +718,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index a67771d02146..93c9651c315d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -315,8 +315,11 @@ &gpio5 { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -441,8 +444,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -564,8 +570,11 @@ LDO6 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -582,8 +591,11 @@ accelerometer@19 { &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gpioled: gpio@27 { @@ -738,6 +750,13 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -745,6 +764,13 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -752,6 +778,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -759,6 +792,13 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pcie0: pciegrp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index dd4302ac1de4..187e0410b87d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -297,8 +297,11 @@ &gpu { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -565,8 +568,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -584,16 +590,22 @@ accelerometer@19 { /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -744,6 +756,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -751,6 +770,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -758,6 +784,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -765,6 +798,13 @@ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index 06b4c93c5876..ceeca4966fc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -253,8 +253,11 @@ &gpio5 { &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ rtc@68 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -556,16 +562,22 @@ fixed-link { /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -800,6 +812,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -807,6 +826,13 @@ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -814,6 +840,13 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 @@ -821,6 +854,13 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ From c47d7b73c75a181cbfd4d680ea49bebbcde6507a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 22 Sep 2022 10:13:47 +0200 Subject: [PATCH 04/60] arm64: dts: freescale: Add InnoComm i.MX8MM based WB15 SoM and EVK Add the InnoComm i.MX8MM based WB15 SoM and its EVK. The WB15 is a half credit card sized board featuring: - i.MX8MM CPU - LPDDR4, 1GiB - eMMC, 8GiB - 1Gb Ethernet RGMII interface - WiFi 802.11 a/b/g/n/ac, Bluetooth 4.2 Signed-off-by: Sascha Hauer Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-innocomm-wb15-evk.dts | 146 ++++++ .../dts/freescale/imx8mm-innocomm-wb15.dtsi | 480 ++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 3ea9edc87909..c901404197c3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts new file mode 100644 index 000000000000..055faae79930 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Bang & Olufsen + * Copyright 2022 Pengutronix + */ + +/dts-v1/; + +#include "imx8mm-innocomm-wb15.dtsi" + +/ { + model = "InnoComm WB15-EVK"; + compatible = "innocomm,wb15-evk", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + label = "debug"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vsd_3v3>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ethphy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy_reg>; + regulator-name = "PHY_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-supply = <®_ethphy>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + >; + }; + + pinctrl_fec_phy: fec-phy-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_fec_phy_reg: fec-phy-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 + >; + }; + + pinctrl_gpio_leds: led-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6 + >; + }; + + pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi new file mode 100644 index 000000000000..44e87b1568e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Bang & Olufsen + */ + +#include "imx8mm.dtsi" +#include + +/ { + reg_modem: regulator-modem { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_modem_regulator>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_3v3_out: regulator-3v3-out { + compatible = "regulator-fixed"; + regulator-name = "3V3_OUT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <850000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <850000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // buck5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // buck6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // buck7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // buck8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + fsl,max-link-speed = <1>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4349-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_modem_bt>; + device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_out>; + vddio-supply = <®_3v3_out>; + clocks = <&osc_32k>; + max-speed = <3000000>; + clock-names = "extclk"; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */ + +&iomuxc { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_pcie0: pcie0-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6 + >; + }; + + pinctrl_modem_bt: modem-bt-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19 + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_modem_regulator: modem-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; From 94bbd9d3f52a3c79e41a75f2f7706034c95b5ae8 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Sep 2022 18:29:19 +0200 Subject: [PATCH 05/60] arm64: dts: verdin-imx8mm: verdin-imx8mp: improve include notation Improve include notation. Usually only dtsi files from the same location are included with an absolute path in quotes. Others should use a relative path enclosed in angle brackets. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index bcab830c6e95..dae830271989 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -3,8 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/phy/phy-imx8-pcie.h" -#include "dt-bindings/pwm/pwm.h" +#include +#include #include "imx8mm.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 7b712d1888ea..e8b3f903cb8c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -3,7 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/pwm/pwm.h" +#include +#include #include "imx8mp.dtsi" / { From c579c24d4a14dd600146010347e4ba62d80a6667 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Sep 2022 18:29:20 +0200 Subject: [PATCH 06/60] arm64: dts: colibri-imx8x: improve include notation Improve include notation. Usually only dtsi files from the same location are included with an absolute path in quotes. Others should use a relative path enclosed in angle brackets. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi index a08e70fb7c7a..7c334b93db3b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi @@ -3,7 +3,7 @@ * Copyright 2019 Toradex */ -#include "dt-bindings/input/linux-event-codes.h" +#include / { aliases { From 909c3951afa69f4b820ad0b7f975900f8c3d6122 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Sep 2022 18:29:21 +0200 Subject: [PATCH 07/60] arm64: dts: verdin-imx8mm: verdin-imx8mp: rename sn65dsi83 to sn65dsi84 Rename sn65dsi83 to sn65dsi84 as that is the exact chip used on the Verdin DSI to LVDS Adapter. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index dae830271989..484d58d303f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -610,7 +610,7 @@ atmel_mxt_ts: touch@4a { compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index e8b3f903cb8c..39e1d1780210 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -679,8 +679,8 @@ gpio_expander_21: gpio-expander@21 { status = "disabled"; }; - lvds_ti_sn65dsi83: bridge@2c { - compatible = "ti,sn65dsi83"; + lvds_ti_sn65dsi84: bridge@2c { + compatible = "ti,sn65dsi84"; /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; @@ -713,7 +713,7 @@ atmel_mxt_ts: touch@4a { compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio4>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; From 8fb7256af86fcdebcefcff39b3043aa1619229a7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Sep 2022 18:29:22 +0200 Subject: [PATCH 08/60] arm64: dts: verdin-imx8mm: improve pcie node Slight improvement of pcie node to be more in-line with what we add on the Verdin iMX8M Plus. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 484d58d303f3..7bc51249a502 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -653,7 +653,8 @@ &pcie0 { assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>; clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; @@ -664,6 +665,7 @@ &pcie0 { &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; fsl,clkreq-unsupported; fsl,refclk-pad-mode = ; fsl,tx-deemph-gen1 = <0x2d>; From f98c2dfedb735b28727a15de6769c68691e58617 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 23 Sep 2022 15:49:43 +0800 Subject: [PATCH 09/60] arm64: dts: imx8m: align anatop with bindings The CCM ANALOG module is used for generate PLLs, align the node with DT bindings Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 5 +++-- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 5 +++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index afb90f59c83c..ea5feb04a0b7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -573,9 +573,10 @@ fec_mac_address: mac-address@90 { }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index cb2836bfbd95..fc86e7337313 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -576,10 +576,10 @@ fec_mac_address: mac-address@90 { }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bb916a0948a8..9f1b043c2f3f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -441,10 +441,10 @@ eth_mac2: mac-address@96 { }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 19eaa523564d..b14dbf2ffb9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -605,10 +605,11 @@ fec_mac_address: mac-address@90 { }; }; - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mq-anatop"; reg = <0x30360000 0x10000>; interrupts = ; + #clock-cells = <1>; }; snvs: snvs@30370000 { From 9509593f327ac27e8cb912cfb4696feb718842d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 24 Sep 2022 19:46:03 +0200 Subject: [PATCH 10/60] arm64: dts: imx8mm: Model PMIC to SNVS RTC clock path on Data Modul i.MX8M Mini eDM SBC The PMIC is the 32 kHz clock source for the RTC_XTALI input of the SoC on this system. The RTC_XTALI input is used to supply 32 kHz clock to the SVNS RTC per "i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020" page 759 "The 32KHz XTAL module uses a different IP and it is used as the clock source for the RTC, located in the SNVS." The PMIC has its own dedicated 32 kHz XTAL on input. Model the connection in DT. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-data-modul-edm-sbc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 778bdbe228d3..84384e50298e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -46,6 +46,12 @@ clk_xtal25: clk-xtal25 { clock-frequency = <25000000>; }; + clk_xtal32k: clk-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + panel: panel { backlight = <&backlight>; power-supply = <®_panel_vcc>; @@ -271,6 +277,9 @@ &i2c1 { pmic: pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + #clock-cells = <0>; + clocks = <&clk_xtal32k 0>; + clock-output-names = "clk-32k-out"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; @@ -928,6 +937,10 @@ &sai5 { status = "disabled"; }; +&snvs_rtc { + clocks = <&pmic>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From 375347575fb369255471e1142bd62621b85d1876 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 24 Sep 2022 19:46:38 +0200 Subject: [PATCH 11/60] arm64: dts: imx8mm: Drop QCA clk out setup on Data Modul i.MX8M Mini eDM SBC The PHY clock output is not connected to anything, drop the clock output configuration. This way, the PHY does not generate output clock. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 84384e50298e..de28572cb79b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -189,8 +189,6 @@ fec1_phy: ethernet-phy@0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <10000>; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = ; qca,keep-pll-enabled; vddio-supply = <&vddio>; From 8065fc937f0f147f0a6efdf14f3cbcb821ea18db Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 30 Sep 2022 13:34:25 -0500 Subject: [PATCH 12/60] arm64: dts: imx8dxl: add usb1 and usb2 support There are two chipidea usb controller in 8dxl. Add usb node at common connect subsystem. Enable two usb at imx8dxl_evk boards dts. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 39 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 34 ++++++++++++++++ .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 10 +++++ 3 files changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 82a1c4488378..bf72732e311a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -34,6 +34,35 @@ conn_ipg_clk: clock-conn-ipg { clock-output-names = "conn_ipg_clk"; }; + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx7ulp-usb"; + reg = <0x5b0d0000 0x200>; + interrupt-parent = <&gic>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + power-domains = <&pd IMX_SC_R_USB_0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0d0200 0x200>; + }; + + usbphy1: usbphy@5b100000 { + compatible = "fsl,imx7ulp-usbphy"; + reg = <0x5b100000 0x1000>; + clocks = <&usb2_lpcg 1>; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; + usdhc1: mmc@5b010000 { interrupts = ; reg = <0x5b010000 0x10000>; @@ -195,4 +224,14 @@ enet1_lpcg: clock-controller@5b240000 { "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + clock-indices = , ; + clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index ca2a43e0cbf6..a91a70651ea4 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -266,6 +266,40 @@ map0 { }; }; +&usbphy1 { + /* USB eye diagram tests result */ + fsl,tx-d-cal = <114>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + /* USB eye diagram tests result */ + fsl,tx-d-cal = <111>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 69c4849f2132..6b416fb760d5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -140,3 +140,13 @@ &usdhc3 { compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; interrupts = ; }; + +&usbotg1 { + interrupts = ; + /* + * usbotg1 and usbotg2 share one clock + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; +}; From 29ecef8eceecec09f01e58740235009de436ea53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Sun, 9 Oct 2022 14:26:54 +0200 Subject: [PATCH 13/60] arm64: dts: librem5-devkit: Make LED use PWM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can use PWM instead of just GPIO allowing us to control brightness. Signed-off-by: Guido Günther Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mq-librem5-devkit.dts | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 6445c6b90b5b..7e4b6d65fd89 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -61,14 +61,12 @@ button-3 { }; leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "pwm-leds"; led1 { label = "LED 1"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; + max-brightness = <248>; + pwms = <&pwm2 0 50000 0>; }; }; @@ -615,9 +613,9 @@ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ >; }; - pinctrl_gpio_leds: gpioledgrp { + pinctrl_pwm_led: pwmledgrp { fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 >; }; @@ -920,6 +918,12 @@ &pwm1 { status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_led>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; From 822b29e3b2c37fc74cc38e928bb7b87faa2528a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Sun, 9 Oct 2022 14:26:55 +0200 Subject: [PATCH 14/60] arm64: dts: librem5-devkit: Use function and color rather than label MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use predefined colors and function rather than making up a random label. Signed-off-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 7e4b6d65fd89..4c8904fba1c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -7,6 +7,7 @@ #include "dt-bindings/input/input.h" #include +#include #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -64,7 +65,8 @@ leds { compatible = "pwm-leds"; led1 { - label = "LED 1"; + function = LED_FUNCTION_STATUS; + color = ; max-brightness = <248>; pwms = <&pwm2 0 50000 0>; }; From b202ac0c1308013b6d7c4ae43a350d0c8531c2c7 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Tue, 11 Oct 2022 14:47:14 -0500 Subject: [PATCH 15/60] arm64: dts: freescale: imx8dxl: add scu_gpio node add scu_gpio node in system-controller. Signed-off-by: Shenwei Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 5ddbda0b4def..9f79504f9d6a 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -133,6 +133,12 @@ clk: clock-controller { clock-names = "xtal_32KHz", "xtal_24Mhz"; }; + scu_gpio: gpio { + compatible = "fsl,imx8qxp-sc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + iomuxc: pinctrl { compatible = "fsl,imx8dxl-iomuxc"; }; From 4cce83203aecea5e15e2534be51b746ed41a9a46 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Tue, 11 Oct 2022 14:47:15 -0500 Subject: [PATCH 16/60] arm64: dts: freescale: imx8dxl-evk: enable mii_select node The mii_select node is used to determine the fec1's interface type. Using "enable-active-high" property to configure the interface type as "RMII". Deleting the property as "RGMII". Signed-off-by: Shenwei Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index a91a70651ea4..fc9647ea50e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -90,6 +90,16 @@ reg_usdhc2_vmmc: regulator-3 { enable-active-high; off-on-delay-us = <3480>; }; + + mii_select: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "mii-select"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; }; &eqos { From bce9f6f75db0a6c353f2008acadd69b423513527 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 20 Oct 2022 18:16:58 +0800 Subject: [PATCH 17/60] arm64: dts: imx93: add nxp,no-divider for sysctr There is no internal '/3' divider in i.MX93 sysctr, so need this property. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 3a5713bb4880..bb2ff2d01f84 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -145,6 +145,7 @@ system_counter: timer@44290000 { interrupts = ; clocks = <&osc_24m>; clock-names = "per"; + nxp,no-divider; }; lpi2c1: i2c@44340000 { From d8f011d79b802e9f6241cc9ec242f52cfca5b0d2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 20 Oct 2022 18:16:59 +0800 Subject: [PATCH 18/60] arm64: dts: imx93: add MU clock for mailbox Add MU clock for mailbox usage Reviewed-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index bb2ff2d01f84..4e112ebb74bc 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -135,6 +135,7 @@ mu1: mailbox@44230000 { compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x44230000 0x10000>; interrupts = ; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; @@ -271,6 +272,7 @@ mu2: mailbox@42440000 { compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x42440000 0x10000>; interrupts = ; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; From 435bfa00f4d523a67abb445833386e0a177b4a28 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Thu, 20 Oct 2022 18:17:00 +0800 Subject: [PATCH 19/60] arm64: dts: imx93: add gpio alises gpio driver need these gpio alises to config the gpio base. Reviewed-by: Jun Li Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4e112ebb74bc..d8e2301a4831 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -17,6 +17,10 @@ / { #size-cells = <2>; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; From 80e566893e81a6005c8463458a349c7ff65bce97 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 20 Oct 2022 18:17:01 +0800 Subject: [PATCH 20/60] arm64: dts: imx93: add extra lpspi node Add more lpspi nodes which exist in i.MX93 Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index d8e2301a4831..4b4a500ed86c 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -301,6 +301,30 @@ lpi2c4: i2c@42540000 { status = "disabled"; }; + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + lpuart3: serial@42570000 { compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; @@ -395,6 +419,54 @@ lpi2c8: i2c@426e0000 { status = "disabled"; }; + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + }; aips3: bus@42800000 { From 3f932b4df94f84a0f5932f29c45732cbe523196c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 20 Oct 2022 18:17:02 +0800 Subject: [PATCH 21/60] arm64: dts: imx93: add tpm nodes Add tpm[2,4-6] node Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4b4a500ed86c..db5e3ae308e9 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -153,6 +153,14 @@ system_counter: timer@44290000 { nxp,no-divider; }; + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + lpi2c1: i2c@44340000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; @@ -281,6 +289,30 @@ mu2: mailbox@42440000 { status = "disabled"; }; + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x10000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; From 48d74376fb681b15cdb9db598aad2dff596a0d9e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 20 Oct 2022 18:31:58 +0800 Subject: [PATCH 22/60] arm64: dts: imx8mp: update ecspi compatible and clk i.MX8MP ECSPI is derived from i.MX6UL, so update compatible Add assigned-clocks settings Signed-off-by: Clark Wang Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9f1b043c2f3f..7be02cd100cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -705,12 +705,15 @@ aips3: bus@30800000 { ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30820000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, <&clk IMX8MP_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -719,12 +722,15 @@ ecspi1: spi@30820000 { ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30830000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -733,12 +739,15 @@ ecspi2: spi@30830000 { ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30840000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, <&clk IMX8MP_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; dma-names = "rx", "tx"; status = "disabled"; From 3cad403f586f720dfc41a051ee781ee0c0b04a4c Mon Sep 17 00:00:00 2001 From: Li Jun Date: Fri, 28 Oct 2022 09:58:38 +0800 Subject: [PATCH 23/60] arm64: dts: imx8mm/n-evk: enable wakeup-source for usb phy Enable usb phy to be wakeup source to support system wakeup from usb. Signed-off-by: Li Jun Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 7d6317d95b13..6800d923aa7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -399,6 +399,10 @@ &uart2 { /* console */ status = "okay"; }; +&usbphynop1 { + wakeup-source; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 261c36540079..8cb87c7a0f03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -255,6 +255,10 @@ &uart3 { status = "okay"; }; +&usbphynop1 { + wakeup-source; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; From a9404a89178a866c6718c8cb0682b67f33726fb5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Oct 2022 21:49:55 +0100 Subject: [PATCH 24/60] arm64: dts: imx8mp: Bind bluetooth UART on DH electronics i.MX8M Plus DHCOM The i.MX8MP DHCOM SoM does contain muRata 2AE WiFi+BT chip, bind the bluetooth to UART2 using btbcm and hci_bcm drivers. Use PLL3 to drive UART2 clock divided down to 64 MHz to obtain suitable block clock for exact 4 Mbdps, which is the maximum supported baud rate by the muRata 2AE BT UART. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 31 +++++++++++++++---- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 0f13ee362771..6e1192e751f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -427,6 +427,24 @@ &uart2 { pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; status = "okay"; + + /* + * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock, + * which with 16x oversampling yields 4 Mbdps baud base, + * which is exactly the maximum rate supported by muRata + * 2AE bluetooth UART. + */ + assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <320000000>, <64000000>; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + compatible = "cypress,cyw4373a0-bt"; + shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + }; }; &uart3 { @@ -849,6 +867,13 @@ MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 >; }; + pinctrl_uart2_bt: dhcom-uart2-bt-grp { + fsl,pins = < + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + >; + }; + pinctrl_uart3: dhcom-uart3-grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 @@ -886,8 +911,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; @@ -901,8 +924,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; @@ -916,8 +937,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; From 630ecc93c30e6b3d8177cca2cf3b8c694544500d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 1 Nov 2022 10:21:29 +0100 Subject: [PATCH 25/60] arm64: dts: tqma8mpql: add PCIe support Add PCIe support on TQMa8MPxL module on MBa8MPxL mainboard. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 1c440909f580..3165044e87f4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -8,6 +8,7 @@ #include #include +#include #include #include "imx8mp-tqma8mpql.dtsi" @@ -48,6 +49,12 @@ backlight_lvds: backlight { status = "disabled"; }; + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -340,9 +347,16 @@ &gpio4 { "", "", "", "", "", "", "", "", "", "", "DP_IRQ", "DSI_EN", - "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "", + "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", "", "", "", "FAN_PWR", "RTC_EVENT#", "CODEC_RST#", "", ""; + + pcie-refclkreq-hog { + gpio-hog; + gpios = <22 0>; + output-high; + line-name = "PCIE_REFCLK_OE#"; + }; }; &gpio5 { @@ -377,6 +391,13 @@ at24c02_54: eeprom@54 { pagesize = <16>; vcc-supply = <®_vcc_3v3>; }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c4 { @@ -407,6 +428,25 @@ &pcf85063 { interrupts = <28 IRQ_TYPE_EDGE_FALLING>; }; +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + clocks = <&pcieclk 0>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; From 534d4f66b31b4a7fa35eec69ee24928c2f189c5d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 1 Nov 2022 10:06:42 +0100 Subject: [PATCH 26/60] arm64: dts: mba8mpxl: Add PWM fan support This adds the support for optional PWM fan 422J/2HP. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 3165044e87f4..6357f3d96ccd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -55,6 +55,21 @@ clk_xtal25: clk-xtal25 { clock-frequency = <25000000>; }; + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio5>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -115,6 +130,18 @@ display: display { status = "disabled"; }; + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpwmfan>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vcc_12v0>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -172,6 +199,47 @@ linux,cma { linux,cma-default; }; }; + + thermal-zones { + soc-thermal { + trips { + soc_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + soc_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + soc_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&soc_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&soc_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&soc_active2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; }; &ecspi1 { @@ -762,10 +830,18 @@ pinctrl_pwm3: pwm3grp { fsl,pins = ; }; + pinctrl_pwmfan: pwmfangrp { + fsl,pins = ; /* FAN RPM */ + }; + pinctrl_reg12v0: reg12v0grp { fsl,pins = ; /* VCC12V enable */ }; + pinctrl_regpwmfan: regpwmfangrp { + fsl,pins = ; + }; + /* X61 */ pinctrl_uart1: uart1grp { fsl,pins = , From d0a52238d604fefcc034fe1ab70a0d47eafbaea8 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:11:58 +0100 Subject: [PATCH 27/60] arm64: dts: verdin-imx8mp: improve pinctrl for vbus-supplies As we are using two fixed regulators for Verdin USB_1_EN (SODIMM 155) and Verdin USB_2_EN (SODIMM 185), those should be muxed as GPIOs rather than OTG_PWR. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 39e1d1780210..e2fa8070791d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -1221,7 +1221,7 @@ pinctrl_uart4: uart4grp { pinctrl_usb1_vbus: usb1vbusgrp { fsl,pins = - ; /* SODIMM 155 */ + ; /* SODIMM 155 */ }; /* USB_1_ID */ @@ -1232,7 +1232,7 @@ pinctrl_usb_1_id: usb1idgrp { pinctrl_usb2_vbus: usb2vbusgrp { fsl,pins = - ; /* SODIMM 185 */ + ; /* SODIMM 185 */ }; /* On-module Wi-Fi */ From 4306aa3b63f91a6c6265de25b96b71344bf8117e Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:11:59 +0100 Subject: [PATCH 28/60] arm64: dts: verdin-imx8mp: remove usb_2 over-current detection disabling The disable-over-current property is only applicable for the ci-hdrc-usb2 and dwc2 drivers while the i.MX 8M Plus integrates dwc3 IP. Therefore remove this property which does not really serve any purpose here. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index e2fa8070791d..e4a5fec059c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -828,7 +828,6 @@ &usb3_phy1 { }; &usb_dwc3_1 { - disable-over-current; dr_mode = "host"; }; From b1d003f1b7596bcb9503b06a0420b2fe10c06131 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:12:00 +0100 Subject: [PATCH 29/60] arm64: dts: verdin-imx8mp: add usb_1 over-current detection Add Verdin USB_1 over-current detection functionality via Verdin USB_1_OC# (SODIMM 157) being active-low and removing its previous gpio_hog3 mapping. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index e4a5fec059c1..3e767d3bb0ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -807,6 +807,12 @@ &uart4 { }; /* Verdin USB_1 */ +&usb3_0 { + fsl,over-current-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_oc_n>; +}; + &usb3_phy0 { vbus-supply = <®_usb1_vbus>; }; @@ -816,7 +822,6 @@ &usb_dwc3_0 { dr_mode = "otg"; hnp-disable; maximum-speed = "high-speed"; - over-current-active-low; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_1_id>; srp-disable; @@ -1045,7 +1050,6 @@ pinctrl_gpio_hog2: gpiohog2grp { pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - , /* SODIMM 157 */ /* CSI_1_MCLK */ ; /* SODIMM 91 */ }; @@ -1229,6 +1233,12 @@ pinctrl_usb_1_id: usb1idgrp { ; /* SODIMM 161 */ }; + /* USB_1_OC# */ + pinctrl_usb_1_oc_n: usb1ocngrp { + fsl,pins = + ; /* SODIMM 157 */ + }; + pinctrl_usb2_vbus: usb2vbusgrp { fsl,pins = ; /* SODIMM 185 */ From 683c84a63d3bd7b4a05e0b29ad138cc2f6e5b099 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:12:01 +0100 Subject: [PATCH 30/60] arm64: dts: verdin-imx8mp: disable usb port power control Disable port power control on Verdin USB_1/2 as we use regular fixed-regulators with Verdin USB_1/2_EN as enable GPIOs. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 3e767d3bb0ae..6dc312416e9c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -808,6 +808,7 @@ &uart4 { /* Verdin USB_1 */ &usb3_0 { + fsl,disable-port-power-control; fsl,over-current-active-low; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_1_oc_n>; @@ -828,6 +829,10 @@ &usb_dwc3_0 { }; /* Verdin USB_2 */ +&usb3_1 { + fsl,disable-port-power-control; +}; + &usb3_phy1 { vbus-supply = <®_usb2_vbus>; }; From d54977acb27f118c39de566a958d4f93c8825913 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:12:02 +0100 Subject: [PATCH 31/60] arm64: dts: verdin-imx8mp: add gpio usb-b connector Add GPIO USB-B connector (gpio-usb-b-connector) functionality using Verdin USB_1_ID. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-verdin.dtsi | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 6dc312416e9c..b31af0d1f386 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -814,18 +814,26 @@ &usb3_0 { pinctrl-0 = <&pinctrl_usb_1_oc_n>; }; -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; -}; - &usb_dwc3_0 { + /* dual role only, not full featured OTG */ adp-disable; dr_mode = "otg"; hnp-disable; maximum-speed = "high-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; + role-switch-default-mode = "peripheral"; srp-disable; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + self-powered; + type = "micro"; + vbus-supply = <®_usb1_vbus>; + }; }; /* Verdin USB_2 */ From 237f7d5886b0f8217bef336c6e09fb0e0e277dd6 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 2 Nov 2022 14:12:03 +0100 Subject: [PATCH 32/60] arm64: dts: verdin-imx8mp: dahlia: mark usb_2 permanently attached As both Dahlia and the Verdin Development Board have on-carrier permanently attached USB hubs mark Verdin USB_2 as such. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 4b8f86f63081..80db1ad7c230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -116,6 +116,7 @@ &usb3_phy0 { /* Verdin USB_2 */ &usb3_1 { + fsl,permanently-attached; status = "okay"; }; From 12bd480018a1883fdaf74c7b8ee66fbfed03a092 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Nov 2022 20:17:56 +0100 Subject: [PATCH 33/60] arm64: dts: imx8mm-data-modul: Rename /watchdog-gpio to plain /watchdog The DT bindings checker is confused by the -gpio node suffix, drop it to fix the following warning: " imx8mm-data-modul-edm-sbc.dtb: /: watchdog-gpio: {'pinctrl-names': ['default'], 'pinctrl-0': [[104]], 'compatible': ['linux,wdt-gpio'], 'always-enabled': True, 'gpios': [[45, 8, 0]], 'hw_algo': ['level'], 'hw_margin_ms': [[1500]], 'status': ['disabled']} is not of type 'array' " Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index de28572cb79b..adf6395406c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -83,7 +83,7 @@ reg_usdhc2_vcc: regulator-usdhc2-vcc { enable-active-high; }; - watchdog-gpio { + watchdog { /* TPS3813 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_watchdog_gpio>; From 0c068a364a13e55e4b91ad772a25b683e2f141cb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Nov 2022 20:31:02 +0100 Subject: [PATCH 34/60] arm64: dts: imx8mm: imx8mn: imx8mp: imx8mq: Replace opp-xM with opp-x000000 Fix the following dtbs_check warning on all of i.MX8M variants: " opp-table: Unevaluated properties are not allowed ('opp-25M', 'opp-100M', 'opp-750M' were unexpected) " Using the following command: " $ sed -i '/opp-[0-9]\+M/ s@M {@000000 {@' arch/arm64/boot/dts/freescale/imx8m* " The Documentation/devicetree/bindings/opp/opp-v2-base.yaml expects the OPP subnode names to be full frequency listings in Hz without unit suffixes. Only the i.MX8M DTs are affected per "git grep 'opp-[0-9]\+M'", so fix them. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 6 +++--- .../boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 8 ++++---- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 +++--- 20 files changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index cf07987ccc10..201325f566cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -47,15 +47,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index adf6395406c1..4dac8d450222 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -120,15 +120,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index a2b24d4d4e3e..b68954bcc383 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -23,15 +23,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 8d10f5b41297..5172883717d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -47,11 +47,11 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 0679728d2489..1f8326613ee9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -46,11 +46,11 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 995b44efb1b6..92616bc4f71f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -53,15 +53,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index a0bd540f27d3..ae0721b807e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -53,15 +53,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index c305e325d007..9e7d38872157 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -81,15 +81,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 826627bd4503..750a1f07ecb7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -248,15 +248,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 0359dca031c8..421fd0004eaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -198,15 +198,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 1ec91c5c6a49..8ce562246a08 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -207,15 +207,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 93c9651c315d..eceed9816f5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -266,15 +266,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7bc51249a502..0d454e0e2f7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -183,15 +183,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 1133cded9be2..8a4369d38903 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -55,15 +55,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index d8ce217c6016..5110d59b719f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -35,15 +35,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-600M { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 187e0410b87d..eea38c40750b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -189,15 +189,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 7be02cd100cf..d7039d9fe61a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1072,11 +1072,11 @@ noc: interconnect@32700000 { noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-200M { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; - opp-1000M { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 82387b9cb800..2102e9b57697 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -163,22 +163,22 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; /* * On imx8mq B0 PLL can't be bypassed so low bus is 166M */ - opp-166M { + opp-166000000 { opp-hz = /bits/ 64 <166935483>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index ae08556b2ef2..ddf0e330dc7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -311,15 +311,15 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index b14dbf2ffb9a..c6530e5c7fef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1357,15 +1357,15 @@ noc: interconnect@32700000 { noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-133M { + opp-133000000 { opp-hz = /bits/ 64 <133333333>; }; - opp-400M { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; From eff6b33c9ce96b37339b8aa25afa5601195aefe7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Nov 2022 22:19:03 +0100 Subject: [PATCH 35/60] arm64: dts: imx8mm: Remove watchdog always-enabled property from eDM SBC There is no such always-enabled property supported by gpio-watchdog driver or described in its bindings, remove it. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 4dac8d450222..24f61db33eba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -88,7 +88,6 @@ watchdog { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_watchdog_gpio>; compatible = "linux,wdt-gpio"; - always-enabled; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; hw_algo = "level"; /* Reset triggers in 2..3 seconds */ From e59418a46c14cdffc156f46781765ba43d255d21 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 7 Nov 2022 10:17:54 -0800 Subject: [PATCH 36/60] arm64: dts: imx8m{m,n}-venice-gw7902: add gpio pins for new board revision Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw7902.dts | 12 ++++++++---- .../boot/dts/freescale/imx8mn-venice-gw7902.dts | 8 ++++---- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 421fd0004eaf..32872b0b1aaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -261,7 +261,7 @@ ethphy0: ethernet-phy@0 { &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio3 { &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -750,14 +751,19 @@ &iomuxc { pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -791,8 +797,6 @@ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index eea38c40750b..b9444e4a3d2d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -256,7 +256,7 @@ ethphy0: ethernet-phy@0 { &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio3 { &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -701,10 +701,12 @@ &iomuxc { pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -738,8 +740,6 @@ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; From 1db044b25d2ed65368af0438cb33cc4f9f355bb1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:37 -0500 Subject: [PATCH 37/60] arm64: dts: imx8dxl: add adc0 support Add adc0 and adc1 node at imx8 common dma subsystem. imx8dxl have only adc0. Change irq number for adc0. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++ .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index d7b4229bb4a2..bdbb660c2682 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -156,6 +156,34 @@ i2c3: i2c@5a830000 { status = "disabled"; }; + adc0: adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 { "i2c3_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_3>; }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 795d1d472fae..ac3362e32811 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -11,6 +11,10 @@ &dma_ipg_clk { clock-frequency = <160000000>; }; +&adc0 { + interrupts = ; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; From 7772c29d61794bd34508e946381f450ce7b6a3a6 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:38 -0500 Subject: [PATCH 38/60] arm64: dts: imx8dxl_evk: add adc0 support Enable adc0 at imx8dxl_evk boards dts. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index fc9647ea50e9..11b1ff90c06d 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -91,6 +91,13 @@ reg_usdhc2_vmmc: regulator-3 { off-on-delay-us = <3480>; }; + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + mii_select: regulator-4 { compatible = "regulator-fixed"; regulator-name = "mii-select"; @@ -102,6 +109,11 @@ mii_select: regulator-4 { }; }; +&adc0 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; From 6276d66984e902ee90a2894561cdd8e71434cd71 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:39 -0500 Subject: [PATCH 39/60] arm64: dts: imx8dxl: add flexspi0 support Add flexspi0 node at common lsio subsystem. Change flexspi0 irq number for imx8dxl. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 17 ++++++++++++++++- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 6446e6df7a9a..1f3d225e64ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; lsio_mem_clk: clock-lsio-mem { compatible = "fixed-clock"; @@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 { power-domains = <&pd IMX_SC_R_GPIO_7>; }; + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + lsio_mu0: mailbox@5d1b0000 { reg = <0x5d1b0000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 815bd987b09b..85e6131ec406 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -3,6 +3,11 @@ * Copyright 2019~2020, 2022 NXP */ +&flexspi0 { + compatible = "nxp,imx8dxl-fspi"; + interrupts = ; +}; + &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; From 86d1625d2eaa4551ce35ebd0a2427720a0e9ba9b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:40 -0500 Subject: [PATCH 40/60] arm64: dts: imx8dxl_evk: add flexspi0 support Enable flexspi0 at imx8dxl_evk boards dts. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 11b1ff90c06d..f8d416f7fd92 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -181,6 +181,23 @@ vddio1: vddio-regulator { }; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &i2c2 { #address-cells = <1>; #size-cells = <0>; @@ -386,6 +403,25 @@ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 From c4098885e790e41e9aa032669633e99a1fadffc2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:41 -0500 Subject: [PATCH 41/60] arm64: dts: imx8dxl: add lpspi support Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem. Change irq number for 8dxl. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 112 ++++++++++++++++++ .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 16 +++ 2 files changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index bdbb660c2682..a943a1e2797f 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg { clock-output-names = "dma_ipg_clk"; }; + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + status = "disabled"; + }; + + lpspi1: spi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi1_lpcg 0>, + <&spi1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; @@ -60,6 +124,54 @@ lpuart3: serial@5a090000 { status = "disabled"; }; + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index ac3362e32811..6881330ab4c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -54,3 +54,19 @@ &lpuart3 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; + +&lpspi0 { + interrupts = ; +}; + +&lpspi1 { + interrupts = ; +}; + +&lpspi2 { + interrupts = ; +}; + +&lpspi3 { + interrupts = ; +}; From 65fa83a6baca5b3d21fb34b2f809a6e86d65b96f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 11 Nov 2022 10:47:42 -0500 Subject: [PATCH 42/60] arm64: dts: imx8dxl_evk: add lpspi0 support Enable lpspi0 at imx8dxl_evk boards dts. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index f8d416f7fd92..280a9c9d8bd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -359,6 +359,21 @@ &usdhc2 { status = "okay"; }; +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; From af9493d6fd9830dc312434344c4f15dd9d6167b6 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Fri, 11 Nov 2022 09:50:14 -0600 Subject: [PATCH 43/60] arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property add gpio-ranges property for imx8dxl soc. This gpio-range is used to record which GPIOs correspond to which pins on which pin controllers. The GPIO to PIN mapping will be referenced by the pad wakeup function in GPIO-MXC driver. Signed-off-by: Shenwei Wang Reviewed-by: Linus Walleij Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 85e6131ec406..5f4f789e4a73 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -11,41 +11,82 @@ &flexspi0 { &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 47 13>, + <&iomuxc 13 61 4>, + <&iomuxc 19 67 4>, + <&iomuxc 24 72 1>; }; &lsio_gpio1 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 4 74 5>, + <&iomuxc 9 80 16>; }; &lsio_gpio2 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 1 98 2>, + <&iomuxc 3 101 1>, + <&iomuxc 5 107 8>; }; &lsio_gpio3 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 115 4>, + <&iomuxc 9 121 1>, + <&iomuxc 10 120 1>, + <&iomuxc 11 123 1>, + <&iomuxc 12 122 1>, + <&iomuxc 13 125 1>, + <&iomuxc 14 124 1>, + <&iomuxc 16 126 1>, + <&iomuxc 17 128 1>, + <&iomuxc 18 131 1>, + <&iomuxc 19 130 1>, + <&iomuxc 20 133 1>, + <&iomuxc 21 132 1>, + <&iomuxc 22 129 1>, + <&iomuxc 23 134 1>; }; &lsio_gpio4 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 12>, + <&iomuxc 19 22 2>, + <&iomuxc 21 25 2>, + <&iomuxc 29 29 3>; }; &lsio_gpio5 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 32 3>, + <&iomuxc 3 36 6>, + <&iomuxc 9 43 3>; }; &lsio_gpio6 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 53 7>, + <&iomuxc 8 86 10>, + <&iomuxc 19 107 8>; }; &lsio_gpio7 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 8 22 2>, + <&iomuxc 10 25 2>, + <&iomuxc 16 44 2>; }; &lsio_mu0 { From bed3003aad6d59fa662bf333ae2c16cbd8a5da69 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Fri, 11 Nov 2022 09:50:15 -0600 Subject: [PATCH 44/60] arm64: dts: imx8qm-ss-lsio: add gpio-ranges property add gpio-ranges property for imx8qm soc. This gpio-range is used to record which GPIOs correspond to which pins on which pin controllers. The GPIO to PIN mapping will be referenced by the pad wakeup function in GPIO-MXC driver. Signed-off-by: Shenwei Wang Reviewed-by: Linus Walleij Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 669aa14ce9f7..b483134f84d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -6,30 +6,68 @@ &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 6>, + <&iomuxc 6 7 22>, + <&iomuxc 28 36 4>; }; &lsio_gpio1 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 4>, + <&iomuxc 4 50 12>, + <&iomuxc 16 63 8>, + <&iomuxc 24 72 8>; }; &lsio_gpio2 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 80 4>, + <&iomuxc 4 85 18>, + <&iomuxc 22 104 10>; }; &lsio_gpio3 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 114 2>, + <&iomuxc 2 117 16>, + <&iomuxc 18 141 1>, + <&iomuxc 19 140 1>, + <&iomuxc 20 139 1>, + <&iomuxc 21 138 1>, + <&iomuxc 22 137 1>, + <&iomuxc 23 136 1>, + <&iomuxc 24 135 1>, + <&iomuxc 25 134 1>, + <&iomuxc 26 142 3>, + <&iomuxc 29 146 3>; }; &lsio_gpio4 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 149 3>, + <&iomuxc 3 153 4>, + <&iomuxc 7 158 6>, + <&iomuxc 13 165 6>, + <&iomuxc 19 172 8>, + <&iomuxc 27 198 5>; }; &lsio_gpio5 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 203 1>, + <&iomuxc 1 205 2>, + <&iomuxc 3 210 11>, + <&iomuxc 14 223 3>, + <&iomuxc 17 227 2>, + <&iomuxc 19 230 5>, + <&iomuxc 24 236 6>, + <&iomuxc 30 243 2>; }; &lsio_gpio6 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 245 10>, + <&iomuxc 10 256 12>; }; &lsio_gpio7 { From b57220ac8d26c8ac30c530cff0d50e27ebfed904 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Fri, 11 Nov 2022 09:50:16 -0600 Subject: [PATCH 45/60] arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property add gpio-ranges property for imx8qxp soc. This gpio-range is used to record which GPIOs correspond to which pins on which pin controllers. The GPIO to PIN mapping will be referenced by the pad wakeup function in GPIO-MXC driver. Signed-off-by: Shenwei Wang Reviewed-by: Linus Walleij Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 8e2152c6eb88..8f722b1dd078 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -6,26 +6,51 @@ &lsio_gpio0 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 1 56 12>, + <&iomuxc 13 69 4>, + <&iomuxc 19 75 4>, + <&iomuxc 24 80 1>, + <&iomuxc 25 82 7>; }; &lsio_gpio1 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 89 9>, + <&iomuxc 9 99 16>, + <&iomuxc 25 116 7>; }; &lsio_gpio2 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 123 1>, + <&iomuxc 1 126 2>, + <&iomuxc 3 129 1>; }; &lsio_gpio3 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 146 4>, + <&iomuxc 4 151 13>, + <&iomuxc 17 165 8>; }; &lsio_gpio4 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 6>, + <&iomuxc 13 16 6>, + <&iomuxc 19 23 2>, + <&iomuxc 21 26 2>, + <&iomuxc 23 30 6>, + <&iomuxc 29 37 3>; }; &lsio_gpio5 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 3>, + <&iomuxc 3 44 6>, + <&iomuxc 9 51 3>; }; &lsio_gpio6 { From 77a1a1826f7d5072d78c5135877c8733468f5ceb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Nov 2022 09:44:59 -0300 Subject: [PATCH 46/60] arm64: dts: imx8mm-phg: Add initial board support Add the initial support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mm-phg.dts | 266 +++++++++++++++++++ 2 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phg.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c901404197c3..ef6f364eaa18 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts new file mode 100644 index 000000000000..e9447738b104 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Fabio Estevam + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" + +/ { + model = "Cloos i.MX8MM PHG board"; + compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "status1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "status2"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "status3"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "run"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "powerled"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbphynop1 { + power-domains = <&pgc_otg1>; +}; + +&usbphynop2 { + power-domains = <&pgc_otg2>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + sd-uhs-ddr50; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; From 3b450831e5f1af09c6b0767b20f607943a681ffb Mon Sep 17 00:00:00 2001 From: Pierre Gondois Date: Mon, 7 Nov 2022 16:57:01 +0100 Subject: [PATCH 47/60] arm64: dts: Update cache properties for freescale The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Reviewed-by: Chester Lin Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ 16 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac1c3a7e5f7a..1b33cabb4e14 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -46,6 +46,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 704f72caddd3..b9fd24cdc919 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -84,6 +84,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 3d9e29824bb2..a01e3cfec77f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -79,6 +79,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index a2cadf757148..1e5d76c4d83d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index c3dc38188c17..c12c86915ec8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 6680fb2a6dc9..e5215ed0975e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -300,6 +300,7 @@ cpu701: cpu@701 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -308,6 +309,7 @@ cluster0_l2: l2-cache0 { cluster1_l2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -316,6 +318,7 @@ cluster1_l2: l2-cache1 { cluster2_l2: l2-cache2 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -324,6 +327,7 @@ cluster2_l2: l2-cache2 { cluster3_l2: l2-cache3 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -332,6 +336,7 @@ cluster3_l2: l2-cache3 { cluster4_l2: l2-cache4 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -340,6 +345,7 @@ cluster4_l2: l2-cache4 { cluster5_l2: l2-cache5 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -348,6 +354,7 @@ cluster5_l2: l2-cache5 { cluster6_l2: l2-cache6 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -356,6 +363,7 @@ cluster6_l2: l2-cache6 { cluster7_l2: l2-cache7 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 9f79504f9d6a..0c64b9194621 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -59,6 +59,7 @@ A35_1: cpu@1 { A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ea5feb04a0b7..fae0e1a31147 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index fc86e7337313..3c8ff12ab14d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index d7039d9fe61a..4fc90477b419 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -123,6 +123,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c6530e5c7fef..3d25535b43e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -179,6 +179,7 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index c9c2b6536233..41ce8336f29e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -136,6 +136,7 @@ A72_1: cpu@101 { A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -144,6 +145,7 @@ A53_L2: l2-cache0 { A72_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index f4ea18bb95ab..85c0b1d2bac5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -127,6 +127,7 @@ A35_3: cpu@3 { A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 06ce5f19aa8a..32193a43ff49 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -51,6 +51,7 @@ A35_1: cpu@1 { A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 824d401e7a2c..d8c82da88ca0 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -52,10 +52,12 @@ cpu3: cpu@101 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index ba0b5305d481..3e306218d533 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -61,10 +61,12 @@ cpu3: cpu@101 { cluster0_l2_cache: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; From c3150e524e85b5092ce9a5ed282f96b054d8b510 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Fri, 9 Sep 2022 10:39:40 +0200 Subject: [PATCH 48/60] arm64: dts: imx8mq: fix dtschema warning for imx7-csi According to dtschema for the csi bridge, compatible is an enum and only one must be used. Fixing this removes the following warning: compatible: 'oneOf' conditional failed, one must be fixed Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 3d25535b43e5..7ce99c084e54 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1186,7 +1186,7 @@ csi1_mipi_ep: endpoint { }; csi1: csi@30a90000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + compatible = "fsl,imx8mq-csi"; reg = <0x30a90000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; @@ -1238,7 +1238,7 @@ csi2_mipi_ep: endpoint { }; csi2: csi@30b80000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + compatible = "fsl,imx8mq-csi"; reg = <0x30b80000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; From 834464c8504c5326b609f3f8052351de8b60ffec Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:53:52 +0800 Subject: [PATCH 49/60] arm64: dts: imx8mp: add mlmix power domain Add mlmix power domain Signed-off-by: Peng Fan Acked-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 4fc90477b419..7a6e6221f421 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -632,6 +632,14 @@ pgc_vpu_vc8000e: power-domain@22 { reg = ; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; From 2f6f2a0c8b064b4544f330d0f713cccf6b59d419 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Thu, 17 Nov 2022 17:53:54 +0800 Subject: [PATCH 50/60] ARM64: dts: imx8mp-evk: add pwm support Enable pwm1/2/4 support. Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM pwm4 on pin SAI5_RXFS for J21-32 Acked-by: Fugang Duan Signed-off-by: Clark Wang Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9f1469db554d..63c379e86637 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -390,6 +390,24 @@ &pcie { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -567,6 +585,24 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 From c2f812df0f833bb3304b1cb5009c9279ec707b1e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:53:55 +0800 Subject: [PATCH 51/60] arm64: dts: imx8mp-evk: enable uart1/3 ports Enable uart1/3 ports for evk board. Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart could only support max 1.5M buadrate if using OSC_24M as clock source. Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 63c379e86637..151a78563970 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -412,6 +412,15 @@ &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; @@ -434,6 +443,15 @@ &usb_dwc3_1 { status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -609,6 +627,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 @@ -622,6 +649,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 From 7a2f7d763d94b79a0b0af25b7868abb8e550a45d Mon Sep 17 00:00:00 2001 From: Han Xu Date: Thu, 17 Nov 2022 17:53:56 +0800 Subject: [PATCH 52/60] arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk enable fspi nor on imx8mp evk dts Reviewed-by: Frank Li Signed-off-by: Han Xu Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 151a78563970..0813a1075759 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -85,6 +85,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + &A53_0 { cpu-supply = <®_arm>; }; @@ -551,6 +565,17 @@ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 From e4c12d9decf55621278e58cd9010b98a6ca4ef91 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:53:57 +0800 Subject: [PATCH 53/60] arm64: dts: imx8mp-evk: enable I2C2 node Enable I2C node for i.MX8MP-EVK Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 0813a1075759..e2e1898d3d12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -331,6 +331,13 @@ LDO5 { }; }; +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -589,6 +596,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 From f4927bb2a2f8b72c0ace0233c05c3924285892a9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:53:58 +0800 Subject: [PATCH 54/60] arm64: dts: imx8mn-evk: update vdd_soc dvs voltage Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2. BUCK2 is for A53, which is handled by DVFS, so no need dvs property. nxp,dvs-run-voltage is not needed, since bootloader must configure voltage to make system boot well. Signed-off-by: Peng Fan Acked-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 4eb467df5ba7..4839a962a170 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -47,6 +47,7 @@ buck1: BUCK1{ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; + nxp,dvs-standby-voltage = <750000>; }; buck2: BUCK2 { @@ -56,8 +57,6 @@ buck2: BUCK2 { regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4{ From cbc44b22c8a8d9f63390221e84354a2c500f0c85 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:53:59 +0800 Subject: [PATCH 55/60] arm64: dts: imx8mn-evk: set off-on-delay-us in regulator Some SD Card controller and power circuitry has increased capacitance, so the usual toggling of regulator to power the card off and on is insufficient. According to SD spec, for sd card power reset operation, the sd card supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise, next time power back the sd card supply voltage to 3.3v, sd card can't support SD3.0 mode again. This patch add the off-on-delay-us, make sure the sd power reset behavior is align with the specification. Without this patch, when do quick system suspend/resume test, some sd card can't work at SD3.0 mode after system resume back. Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 8cb87c7a0f03..e066fa9af834 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -36,6 +36,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; From c0c4c4562b7c8115e44d60547b4f7c039ceca92b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:54:00 +0800 Subject: [PATCH 56/60] arm64: dts: imx8mn-evk: add i2c gpio recovery settings Add I2C gpio recovery iomuxc settings Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index e066fa9af834..2439b91e51d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -160,8 +160,11 @@ &i2c1 { &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; ptn5110: tcpc@50 { @@ -196,8 +199,11 @@ typec1_con: connector { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; pca6416: gpio@20 { @@ -374,6 +380,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -381,6 +394,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 From a8ea275d16230e5272080d101c3ab88d400f49a6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 17 Nov 2022 17:54:01 +0800 Subject: [PATCH 57/60] arm64: dts: imx8mn-evk: enable uart1 Enable uart1 for BT usage Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart could only support max 1.5M buadrate if using OSC_24M as clock source. Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 2439b91e51d8..8fef980c4ab2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -247,6 +247,15 @@ &spdif1 { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -444,6 +453,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 From 2a6b56aafb0cb3cd8bbedde4f7e5498acb30fad8 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Thu, 17 Nov 2022 17:54:02 +0800 Subject: [PATCH 58/60] arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator Some SD Card controller and power circuitry has increased capacitance, so the usual toggling of regulator to power the card off and on is insufficient. According to SD spec, for sd card power reset operation, the sd card supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise, next time power back the sd card supply voltage to 3.3v, sd card can't support SD3.0 mode again. This patch add the off-on-delay-us, make sure the sd power reset behavior is align with the specification. Without this patch, when do quick system suspend/resume test, some sd card can't work at SD3.0 mode after system resume back. Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6800d923aa7e..3f2b0ad51e18 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -56,6 +56,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 2102e9b57697..78937910f403 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -46,6 +46,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; From c6c93f78821996bed390e255fec3ac3a8c61b0bd Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Thu, 17 Nov 2022 17:54:03 +0800 Subject: [PATCH 59/60] arm64: dts: imx8mm-evk: add vcc supply for pca6416 pca6146 requires vcc-supply to work on i.MX8MM-EVK board. Reviewed-by: Shengjiu Wang Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 3f2b0ad51e18..e0b604ac0da4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -344,6 +344,7 @@ pca6416: gpio@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; }; }; From 4c33cb31282c3968000a08223591c532128dfcfd Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 24 Oct 2022 12:34:31 -0500 Subject: [PATCH 60/60] arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso DTB Overlays (.dtbo) can now be built from source files with the extension (.dtso). This makes it clear what is the content of the files and differentiates them from base DTB source files. Convert the DTB overlay source files in the arm64/freescale directory. Signed-off-by: Andrew Davis Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- .../{fsl-ls1028a-qds-13bb.dts => fsl-ls1028a-qds-13bb.dtso} | 0 .../{fsl-ls1028a-qds-65bb.dts => fsl-ls1028a-qds-65bb.dtso} | 0 .../{fsl-ls1028a-qds-7777.dts => fsl-ls1028a-qds-7777.dtso} | 0 .../{fsl-ls1028a-qds-85bb.dts => fsl-ls1028a-qds-85bb.dtso} | 0 .../{fsl-ls1028a-qds-899b.dts => fsl-ls1028a-qds-899b.dtso} | 0 .../{fsl-ls1028a-qds-9999.dts => fsl-ls1028a-qds-9999.dtso} | 0 ...e-gw72xx-0x-imx219.dts => imx8mm-venice-gw72xx-0x-imx219.dtso} | 0 ...xx-0x-rs232-rts.dts => imx8mm-venice-gw72xx-0x-rs232-rts.dtso} | 0 ...ice-gw72xx-0x-rs422.dts => imx8mm-venice-gw72xx-0x-rs422.dtso} | 0 ...ice-gw72xx-0x-rs485.dts => imx8mm-venice-gw72xx-0x-rs485.dtso} | 0 ...e-gw73xx-0x-imx219.dts => imx8mm-venice-gw73xx-0x-imx219.dtso} | 0 ...xx-0x-rs232-rts.dts => imx8mm-venice-gw73xx-0x-rs232-rts.dtso} | 0 ...ice-gw73xx-0x-rs422.dts => imx8mm-venice-gw73xx-0x-rs422.dtso} | 0 ...ice-gw73xx-0x-rs485.dts => imx8mm-venice-gw73xx-0x-rs485.dtso} | 0 14 files changed, 0 insertions(+), 0 deletions(-) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-13bb.dts => fsl-ls1028a-qds-13bb.dtso} (100%) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-65bb.dts => fsl-ls1028a-qds-65bb.dtso} (100%) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-7777.dts => fsl-ls1028a-qds-7777.dtso} (100%) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-85bb.dts => fsl-ls1028a-qds-85bb.dtso} (100%) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-899b.dts => fsl-ls1028a-qds-899b.dtso} (100%) rename arch/arm64/boot/dts/freescale/{fsl-ls1028a-qds-9999.dts => fsl-ls1028a-qds-9999.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw72xx-0x-imx219.dts => imx8mm-venice-gw72xx-0x-imx219.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw72xx-0x-rs232-rts.dts => imx8mm-venice-gw72xx-0x-rs232-rts.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw72xx-0x-rs422.dts => imx8mm-venice-gw72xx-0x-rs422.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw72xx-0x-rs485.dts => imx8mm-venice-gw72xx-0x-rs485.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw73xx-0x-imx219.dts => imx8mm-venice-gw73xx-0x-imx219.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw73xx-0x-rs232-rts.dts => imx8mm-venice-gw73xx-0x-rs232-rts.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw73xx-0x-rs422.dts => imx8mm-venice-gw73xx-0x-rs422.dtso} (100%) rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw73xx-0x-rs485.dts => imx8mm-venice-gw73xx-0x-rs485.dtso} (100%) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts rename to arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts rename to arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso