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arm64: dts: lx2160a: split the dtsi to avoid delete-property

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Reorganize the LX216XA related dts/dtsi files with the intent to avoid any
delete-property usage.

Taken into consideration the differences between the LX2160A Rev1,
LX2160A Rev2 and LX2162A SoCs, the following structure is created:

fsl-lx216x.dtsi		---> fsl-lx2160a-rev1.dtsi (PCIe gen4, 3 SerDes blocks)
(no PCIe, no SerDes)	---> fsl-lx2160a-rev2.dtsi (PCIe gen3, 3 SerDes blocks)
			---> fsl-lx2162a.dtsi (PCIe gen3, 2 SerDes blocks)

Each PCIe integration or SerDes block instantiation has its own dtsi file
which gets to be included only by the necessary SoC level dtsi file.

The dtsi file describing the PCIe controllers found on LX2160A Rev2 is
also changed so that it does not work on a already defined node but rather
it describes it entirely.

In order to decouple the LX2162A from LX2160A, a new dtsi
fsl-lx2162a-serdes.dtsi file is added which, for the moment, only
duplicates the SerDes related nodes found already for LX2160A.

Any dts which previously included fsl-lx2160a.dtsi now includes the -rev1
version and any dts which is clearly intended for LX2162A based board now
includes the fsl-lx2162a.dtsi. No changes for the final dtbs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Ioana Ciornei 2026-07-17 15:06:29 +03:00 committed by Frank Li
parent 8f69555ef5
commit 285560f0d3
12 changed files with 237 additions and 130 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
/ {
model = "NXP Layerscape LX2160ABLUEBOX3";

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"

9
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree Include file for Layerscape-LX2160A Rev1 SoC.
//
// Copyright 2026 NXP
#include "fsl-lx216x.dtsi"
#include "fsl-lx2160a-pcie-mbvl.dtsi"
#include "fsl-lx2160a-serdes.dtsi"

3
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
View File

@ -6,5 +6,6 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx216x.dtsi"
#include "fsl-lx216xa-pcie-gen3.dtsi"
#include "fsl-lx2160a-serdes.dtsi"

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
View File

@ -5,7 +5,7 @@
* Author: Gregor Herburger
*/
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
/ {
reg_vcc3v3: regulator-vcc3v3 {

2
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View File

@ -8,7 +8,7 @@
#include <dt-bindings/leds/common.h>
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {

2
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";

21
arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A
// SoC
//
// Copyright 2026 NXP
&soc {
serdes_1: phy@1ea0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
#phy-cells = <1>;
};
serdes_2: phy@1eb0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
#phy-cells = <1>;
status = "disabled";
};
};

9
arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2162 SoC
//
// Copyright 2026 NXP
#include "fsl-lx216x.dtsi"
#include "fsl-lx216xa-pcie-gen3.dtsi"
#include "fsl-lx2162a-serdes.dtsi"

3
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi → arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
View File

@ -1840,6 +1840,3 @@ optee: optee {
};
};
};
#include "fsl-lx2160a-pcie-mbvl.dtsi"
#include "fsl-lx2160a-serdes.dtsi"

310
arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
View File

@ -4,127 +4,39 @@
//
// Copyright 2026 NXP
&pcie1 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie2 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie3 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie4 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie5 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie6 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&soc {
pcie1: pcie@3400000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
@ -135,6 +47,37 @@ pcie_ep1: pcie-ep@3400000 {
status = "disabled";
};
pcie2: pcie@3500000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
@ -145,6 +88,38 @@ pcie_ep2: pcie-ep@3500000 {
status = "disabled";
};
pcie3: pcie@3600000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
@ -155,6 +130,37 @@ pcie_ep3: pcie-ep@3600000 {
status = "disabled";
};
pcie4: pcie@3700000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep4: pcie-ep@3700000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
@ -165,6 +171,38 @@ pcie_ep4: pcie-ep@3700000 {
status = "disabled";
};
pcie5: pcie@3800000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep5: pcie-ep@3800000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
@ -175,6 +213,38 @@ pcie_ep5: pcie-ep@3800000 {
status = "disabled";
};
pcie6: pcie@3900000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep6: pcie-ep@3900000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000