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arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file
The LX2160A Rev2 SoC changed the PCIe controllers used. This difference is reflected in the fsl-lx2160a-rev2.dtsi file which modifies the relevant dt nodes so that they match the actual HW. Extract these modifications into a separate dtsi file as a first step into a complete overhaul of the LX216xA related dts files with the intent to not use delete-node or delete-property. No final dtb changes are expected with this patch. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Ioana Ciornei
Frank Li
parent
9f0f43baf1
commit
8f69555ef5
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@ -7,187 +7,4 @@
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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&pcie1 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x80 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie2 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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0x88 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie3 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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0x90 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie4 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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0x98 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie5 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
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0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie6 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
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0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&soc {
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pcie_ep1: pcie-ep@3400000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x80 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep2: pcie-ep@3500000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03500000 0x0 0x00100000
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0x88 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep3: pcie-ep@3600000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03600000 0x0 0x00100000
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0x90 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <256>;
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num-ib-windows = <24>;
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status = "disabled";
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};
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pcie_ep4: pcie-ep@3700000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03700000 0x0 0x00100000
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0x98 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep5: pcie-ep@3800000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03800000 0x0 0x00100000
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0xa0 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <256>;
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num-ib-windows = <24>;
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status = "disabled";
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};
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pcie_ep6: pcie-ep@3900000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03900000 0x0 0x00100000
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0xa8 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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};
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#include "fsl-lx216xa-pcie-gen3.dtsi"
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187
arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
Normal file
187
arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi
Normal file
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@ -0,0 +1,187 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Device Tree file describing the PCIe IPs found on the LX2160A Rev2 and LX2162A SoCs
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//
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// Copyright 2026 NXP
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&pcie1 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x80 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie2 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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0x88 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie3 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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0x90 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie4 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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0x98 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie5 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
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0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&pcie6 {
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compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
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reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
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0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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ranges = /* 16-Bit IO Window */
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<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
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/* 32-Bit - non-prefetchable */
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<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
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/* 64-Bit - prefetchable - 16GB */
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<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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/delete-property/ apio-wins;
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/delete-property/ ppio-wins;
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};
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&soc {
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pcie_ep1: pcie-ep@3400000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x80 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep2: pcie-ep@3500000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03500000 0x0 0x00100000
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0x88 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep3: pcie-ep@3600000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03600000 0x0 0x00100000
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0x90 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <256>;
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num-ib-windows = <24>;
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status = "disabled";
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};
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pcie_ep4: pcie-ep@3700000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03700000 0x0 0x00100000
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0x98 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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pcie_ep5: pcie-ep@3800000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03800000 0x0 0x00100000
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0xa0 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <256>;
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num-ib-windows = <24>;
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status = "disabled";
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};
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pcie_ep6: pcie-ep@3900000 {
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compatible = "fsl,lx2160ar2-pcie-ep";
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reg = <0x00 0x03900000 0x0 0x00100000
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0xa8 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ob-windows = <8>;
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num-ib-windows = <8>;
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status = "disabled";
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};
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};
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