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clk: qcom: clk-alpha-pll: Fix APSS_PLL_VOTE debug register output
Fix wrongly mapped APSS_PLL_VOTE debug register output name in PLL register dump. Change-Id: I729c9d4b01d046eeb9c889f7547dafe85fd920c8 Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
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@ -2019,7 +2019,7 @@ static void lucid_pll_list_registers(struct seq_file *f,
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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@ -2137,7 +2137,7 @@ static void clk_agera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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@ -2985,7 +2985,7 @@ static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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@ -3352,7 +3352,7 @@ static void lucid_evo_pll_list_registers(struct seq_file *f,
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if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
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clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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