clk: qcom: clk-alpha-pll: Fix APSS_PLL_VOTE debug register output

Fix wrongly mapped APSS_PLL_VOTE debug register output name in
PLL register dump.

Change-Id: I729c9d4b01d046eeb9c889f7547dafe85fd920c8
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
This commit is contained in:
Imran Shaik 2022-09-19 10:26:47 +05:30 committed by Mike Tipton
parent 50325a326e
commit 262e30a4f3

View File

@ -2019,7 +2019,7 @@ static void lucid_pll_list_registers(struct seq_file *f,
if (val & PLL_FSM_ENA) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}
@ -2137,7 +2137,7 @@ static void clk_agera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
if (val & PLL_FSM_ENA) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}
@ -2985,7 +2985,7 @@ static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
if (val & PLL_FSM_ENA) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}
@ -3352,7 +3352,7 @@ static void lucid_evo_pll_list_registers(struct seq_file *f,
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
data1[0].offset, &val);
clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);
}
}