From 262e30a4f372701801d30ee412ffe534d0074020 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 19 Sep 2022 10:26:47 +0530 Subject: [PATCH] clk: qcom: clk-alpha-pll: Fix APSS_PLL_VOTE debug register output Fix wrongly mapped APSS_PLL_VOTE debug register output name in PLL register dump. Change-Id: I729c9d4b01d046eeb9c889f7547dafe85fd920c8 Signed-off-by: Imran Shaik --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 25f6e8c3bd6b..be210738a788 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2019,7 +2019,7 @@ static void lucid_pll_list_registers(struct seq_file *f, if (val & PLL_FSM_ENA) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); - clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val); + clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val); } } @@ -2137,7 +2137,7 @@ static void clk_agera_pll_list_registers(struct seq_file *f, struct clk_hw *hw) if (val & PLL_FSM_ENA) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); - clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val); + clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val); } } @@ -2985,7 +2985,7 @@ static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw) if (val & PLL_FSM_ENA) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); - clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val); + clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val); } } @@ -3352,7 +3352,7 @@ static void lucid_evo_pll_list_registers(struct seq_file *f, if (val & LUCID_EVO_ENABLE_VOTE_RUN) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); - clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val); + clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val); } }