mirror of
https://github.com/torvalds/linux.git
synced 2026-05-25 15:41:52 +02:00
Renesas DTS updates for v6.16 (take two)
- Add CANFD support for the RZ/G3E SoC and the RZ/G3E SMARC Carrier-II
EVK development board,
- Add support for Ethernet port A, 9-pin D-sub serial, and USB on the
RZN1D-DB and RZN1D-EB development and expansion boards,
- Add sound support for the Retronix Sparrow Hawk board,
- Add General PWM Timer (GPT) support for the RZ/G2L and RZ/V2L SoCs
and SMARC EVK boards,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.16 (take two)
- Add CANFD support for the RZ/G3E SoC and the RZ/G3E SMARC Carrier-II
EVK development board,
- Add support for Ethernet port A, 9-pin D-sub serial, and USB on the
RZN1D-DB and RZN1D-EB development and expansion boards,
- Add sound support for the Retronix Sparrow Hawk board,
- Add General PWM Timer (GPT) support for the RZ/G2L and RZ/V2L SoCs
and SMARC EVK boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable USB host port
ARM: dts: renesas: r9a06g032-rzn1d400-db: Add pinmux for the CPLD
arm64: dts: renesas: white-hawk-single: Improve Ethernet TSN description
ARM: dts: renesas: r9a06g032-rzn1d400-db: Enable USB device port
ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe 9-pin D-sub serial port
arm64: dts: renesas: beacon-renesom: Align wifi node name with bindings
arm64: dts: renesas: rzg2l-smarc: Enable GPT on carrier board
arm64: dts: renesas: r9a07g054: Add GPT support
arm64: dts: renesas: r9a07g044: Add GPT support
arm64: dts: renesas: sparrow-hawk: Add MSIOF Sound support
ARM: dts: renesas: r9a06g032-rzn1d400-eb: Add GMAC1 port
arm64: dts: renesas: r9a09g047e57-smarc: Enable CAN Transceiver
arm64: dts: renesas: r9a09g047e57-smarc: Enable CANFD
arm64: dts: renesas: r9a09g047: Add CANFD node
Link: https://lore.kernel.org/r/cover.1746798755.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
1d55886c96
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@ -170,6 +170,9 @@ &mii_conv5 {
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pins_cpld>;
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pins_can0: pins_can0 {
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pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */
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<RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */
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@ -182,6 +185,13 @@ pins_can1: pins_can1 {
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drive-strength = <6>;
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};
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pins_cpld: pins-cpld {
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pinmux = <RZN1_PINMUX(119, RZN1_FUNC_USB)>,
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<RZN1_PINMUX(120, RZN1_FUNC_USB)>,
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<RZN1_PINMUX(121, RZN1_FUNC_USB)>,
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<RZN1_PINMUX(122, RZN1_FUNC_USB)>;
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};
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pins_eth3: pins_eth3 {
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pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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@ -282,6 +292,10 @@ &uart0 {
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status = "okay";
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};
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&udc {
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status = "okay";
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};
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&wdt0 {
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timeout-sec = <60>;
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status = "okay";
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@ -15,6 +15,44 @@ / {
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"renesas,r9a06g032";
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};
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&gmac1 {
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pinctrl-0 = <&pins_eth0>, <&pins_mdio0>;
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pinctrl-names = "default";
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <&phy_mii0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy_mii0: ethernet-phy@8 {
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reg = <8>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_ORANGE>;
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function = LED_FUNCTION_ACTIVITY;
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default-state = "keep";
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};
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};
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};
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};
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};
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&i2c2 {
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/* Sensors are different across revisions. All are LM75B compatible */
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sensor@49 {
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@ -23,6 +61,11 @@ sensor@49 {
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};
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};
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&mii_conv1 {
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renesas,miic-input = <MIIC_GMAC1_PORT>;
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status = "okay";
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};
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&mii_conv2 {
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renesas,miic-input = <MIIC_SWITCH_PORTD>;
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status = "okay";
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@ -33,7 +76,28 @@ &mii_conv3 {
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status = "okay";
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};
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&pci_usb {
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status = "okay";
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};
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&pinctrl {
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pins_eth0: pins-eth0 {
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pinmux = <RZN1_PINMUX(0, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(1, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(2, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(3, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(4, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(5, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(6, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(7, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(8, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(9, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(10, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(11, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
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drive-strength = <6>;
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bias-disable;
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};
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pins_eth1: pins-eth1 {
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pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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<RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
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@ -68,6 +132,11 @@ pins_eth2: pins-eth2 {
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bias-disable;
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};
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pins_mdio0: pins-mdio0 {
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pinmux = <RZN1_PINMUX(150, RZN1_FUNC_MDIO0_GMAC0)>,
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<RZN1_PINMUX(151, RZN1_FUNC_MDIO0_GMAC0)>;
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};
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pins_sdio1: pins-sdio1 {
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pinmux = <RZN1_PINMUX(95, RZN1_FUNC_SDIO)>,
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<RZN1_PINMUX(97, RZN1_FUNC_SDIO)>,
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@ -82,6 +151,14 @@ pins_sdio1_clk: pins-sdio1-clk {
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pinmux = <RZN1_PINMUX(96, RZN1_FUNC_SDIO)>;
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drive-strength = <12>;
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};
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pins_uart2: pins-uart2 {
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pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>,
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<RZN1_PINMUX(106, RZN1_FUNC_UART2)>,
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<RZN1_PINMUX(107, RZN1_FUNC_UART2)>,
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<RZN1_PINMUX(108, RZN1_FUNC_UART2)>;
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bias-disable;
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};
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};
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&sdio1 {
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@ -158,3 +235,10 @@ &switch_port3 {
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phy-handle = <&switch0phy1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-0 = <&pins_uart2>;
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pinctrl-names = "default";
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status = "okay";
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uart-has-rtscts;
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};
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@ -300,7 +300,7 @@ &sdhi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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brcmf: bcrmf@1 {
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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interrupts-extended = <&gpio1 27 IRQ_TYPE_LEVEL_LOW>;
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@ -4,6 +4,37 @@
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*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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/*
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* DA7212 Codec settings
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*
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* for Playback
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* > amixer set "Headphone" 40%
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* > amixer set "Headphone" on
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* > amixer set "Mixout Left DAC Left" on
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* > amixer set "Mixout Right DAC Right" on
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* > aplay xxx.wav
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*
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* for Capture (Aux/Mic)
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*
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* on/off (B)
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* CONN3 (HeadSet) ---+----> MSIOF1
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* |
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* CONN4 AUX ---------+ on/off (A)
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*
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* > amixer set "Mixin PGA" on
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* > amixer set "Mixin PGA" 50%
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* > amixer set "ADC" on
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* > amixer set "ADC" 80%
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* > amixer set "Aux" on ^
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* > amixer set "Aux" 80% | (A)
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* > amixer set "Mixin Left Aux Left" on |
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* > amixer set "Mixin Right Aux Right" on v
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* > amixer set "Mic 1" on ^
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* > amixer set "Mic 1" 80% | (B)
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* > amixer set "Mixin Left Mic 1" on |
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* > amixer set "Mixin Right Mic 1" on v
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* > arecord -f cd xxx.wav
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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@ -133,6 +164,12 @@ sn65dsi86_refclk: clk-x9 {
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clock-frequency = <38400000>;
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};
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/* Page 30 / Audio_Codec */
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sound_card: sound {
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compatible = "audio-graph-card2";
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links = <&msiof1_snd>;
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};
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/* Page 17 uSD-Slot */
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vcc_sdhi: regulator-vcc-sdhi {
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compatible = "regulator-gpio";
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|
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@ -145,6 +182,10 @@ vcc_sdhi: regulator-vcc-sdhi {
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};
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};
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&audio_clkin {
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clock-frequency = <24576000>;
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};
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/* Page 22 / Ether_AVB0 */
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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@ -334,6 +375,29 @@ i2c0_mux1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Page 30 / Audio_Codec */
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codec@1a {
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compatible = "dlg,da7212";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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clocks = <&rcar_sound>;
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clock-names = "mclk";
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VDDA-supply = <®_1p8v>;
|
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VDDMIC-supply = <®_3p3v>;
|
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VDDIO-supply = <®_3p3v>;
|
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port {
|
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da7212_endpoint: endpoint {
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bitclock-master;
|
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frame-master;
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remote-endpoint = <&msiof1_snd_endpoint>;
|
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};
|
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};
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};
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};
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i2c0_mux2: i2c@2 {
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|
|
@ -404,6 +468,23 @@ &mmc0 {
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status = "okay";
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};
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&msiof1 {
|
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pinctrl-0 = <&msiof1_pins>;
|
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pinctrl-names = "default";
|
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|
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status = "okay";
|
||||
|
||||
/* ignore DT warning */
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
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|
||||
msiof1_snd: port {
|
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msiof1_snd_endpoint: endpoint {
|
||||
remote-endpoint = <&da7212_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Page 26 / 2230 Key M M.2 */
|
||||
&pcie0_clkref {
|
||||
clock-frequency = <100000000>;
|
||||
|
|
@ -584,6 +665,31 @@ sd_uhs_pins: sd-uhs {
|
|||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
/* Page 30 / Audio_Codec */
|
||||
msiof1_pins: sound {
|
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groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd";
|
||||
function = "msiof1";
|
||||
};
|
||||
|
||||
/* Page 30 / Audio_Codec */
|
||||
sound_clk_pins: sound-clk {
|
||||
groups = "audio_clkin", "audio_clkout";
|
||||
function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
/* Page 30 / Audio_Codec */
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* It is used for ADG output as DA7212_MCLK */
|
||||
|
||||
/* audio_clkout */
|
||||
clock-frequency = <12288000>; /* 48 kHz groups */
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Page 31 / FAN */
|
||||
|
|
|
|||
|
|
@ -244,6 +244,121 @@ mtu3: timer@10001200 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: pwm@10048000 {
|
||||
compatible = "renesas,r9a07g044-gpt",
|
||||
"renesas,rzg2l-gpt";
|
||||
reg = <0 0x10048000 0 0x800>;
|
||||
#pwm-cells = <3>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0",
|
||||
"cmpe0", "cmpf0", "adtrga0", "adtrgb0",
|
||||
"ovf0", "unf0",
|
||||
"ccmpa1", "ccmpb1", "cmpc1", "cmpd1",
|
||||
"cmpe1", "cmpf1", "adtrga1", "adtrgb1",
|
||||
"ovf1", "unf1",
|
||||
"ccmpa2", "ccmpb2", "cmpc2", "cmpd2",
|
||||
"cmpe2", "cmpf2", "adtrga2", "adtrgb2",
|
||||
"ovf2", "unf2",
|
||||
"ccmpa3", "ccmpb3", "cmpc3", "cmpd3",
|
||||
"cmpe3", "cmpf3", "adtrga3", "adtrgb3",
|
||||
"ovf3", "unf3",
|
||||
"ccmpa4", "ccmpb4", "cmpc4", "cmpd4",
|
||||
"cmpe4", "cmpf4", "adtrga4", "adtrgb4",
|
||||
"ovf4", "unf4",
|
||||
"ccmpa5", "ccmpb5", "cmpc5", "cmpd5",
|
||||
"cmpe5", "cmpf5", "adtrga5", "adtrgb5",
|
||||
"ovf5", "unf5",
|
||||
"ccmpa6", "ccmpb6", "cmpc6", "cmpd6",
|
||||
"cmpe6", "cmpf6", "adtrga6", "adtrgb6",
|
||||
"ovf6", "unf6",
|
||||
"ccmpa7", "ccmpb7", "cmpc7", "cmpd7",
|
||||
"cmpe7", "cmpf7", "adtrga7", "adtrgb7",
|
||||
"ovf7", "unf7";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
|
||||
resets = <&cpg R9A07G044_GPT_RST_C>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi0: ssi@10049c00 {
|
||||
compatible = "renesas,r9a07g044-ssi",
|
||||
"renesas,rz-ssi";
|
||||
|
|
|
|||
|
|
@ -27,6 +27,13 @@
|
|||
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
|
||||
* PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1"
|
||||
* below.
|
||||
*/
|
||||
#define PMOD0_GPT 0
|
||||
|
||||
#include "r9a07g044l2.dtsi"
|
||||
#include "rzg2l-smarc-som.dtsi"
|
||||
#include "rzg2l-smarc-pinfunction.dtsi"
|
||||
|
|
|
|||
|
|
@ -244,6 +244,121 @@ mtu3: timer@10001200 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: pwm@10048000 {
|
||||
compatible = "renesas,r9a07g054-gpt",
|
||||
"renesas,rzg2l-gpt";
|
||||
reg = <0 0x10048000 0 0x800>;
|
||||
#pwm-cells = <3>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0",
|
||||
"cmpe0", "cmpf0", "adtrga0", "adtrgb0",
|
||||
"ovf0", "unf0",
|
||||
"ccmpa1", "ccmpb1", "cmpc1", "cmpd1",
|
||||
"cmpe1", "cmpf1", "adtrga1", "adtrgb1",
|
||||
"ovf1", "unf1",
|
||||
"ccmpa2", "ccmpb2", "cmpc2", "cmpd2",
|
||||
"cmpe2", "cmpf2", "adtrga2", "adtrgb2",
|
||||
"ovf2", "unf2",
|
||||
"ccmpa3", "ccmpb3", "cmpc3", "cmpd3",
|
||||
"cmpe3", "cmpf3", "adtrga3", "adtrgb3",
|
||||
"ovf3", "unf3",
|
||||
"ccmpa4", "ccmpb4", "cmpc4", "cmpd4",
|
||||
"cmpe4", "cmpf4", "adtrga4", "adtrgb4",
|
||||
"ovf4", "unf4",
|
||||
"ccmpa5", "ccmpb5", "cmpc5", "cmpd5",
|
||||
"cmpe5", "cmpf5", "adtrga5", "adtrgb5",
|
||||
"ovf5", "unf5",
|
||||
"ccmpa6", "ccmpb6", "cmpc6", "cmpd6",
|
||||
"cmpe6", "cmpf6", "adtrga6", "adtrgb6",
|
||||
"ovf6", "unf6",
|
||||
"ccmpa7", "ccmpb7", "cmpc7", "cmpd7",
|
||||
"cmpe7", "cmpf7", "adtrga7", "adtrgb7",
|
||||
"ovf7", "unf7";
|
||||
clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
|
||||
resets = <&cpg R9A07G054_GPT_RST_C>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi0: ssi@10049c00 {
|
||||
compatible = "renesas,r9a07g054-ssi",
|
||||
"renesas,rz-ssi";
|
||||
|
|
|
|||
|
|
@ -26,6 +26,13 @@
|
|||
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
|
||||
* PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1"
|
||||
* below.
|
||||
*/
|
||||
#define PMOD0_GPT 0
|
||||
|
||||
#include "r9a07g054l2.dtsi"
|
||||
#include "rzg2l-smarc-som.dtsi"
|
||||
#include "rzg2l-smarc-pinfunction.dtsi"
|
||||
|
|
|
|||
|
|
@ -301,6 +301,66 @@ scif0: serial@11c01400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@12440000 {
|
||||
compatible = "renesas,r9a09g047-canfd";
|
||||
reg = <0 0x12440000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "g_err", "g_recc",
|
||||
"ch0_err", "ch0_rec", "ch0_trx",
|
||||
"ch1_err", "ch1_rec", "ch1_trx",
|
||||
"ch2_err", "ch2_rec", "ch2_trx",
|
||||
"ch3_err", "ch3_rec", "ch3_trx",
|
||||
"ch4_err", "ch4_rec", "ch4_trx",
|
||||
"ch5_err", "ch5_rec", "ch5_trx";
|
||||
clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>,
|
||||
<&cpg CPG_MOD 0x9e>;
|
||||
clock-names = "fck", "ram_clk", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_MOD 0x9e>;
|
||||
assigned-clock-rates = <80000000>;
|
||||
resets = <&cpg 0xa1>, <&cpg 0xa2>;
|
||||
reset-names = "rstp_n", "rstc_n";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
channel2 {
|
||||
status = "disabled";
|
||||
};
|
||||
channel3 {
|
||||
status = "disabled";
|
||||
};
|
||||
channel4 {
|
||||
status = "disabled";
|
||||
};
|
||||
channel5 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
wdt1: watchdog@14400000 {
|
||||
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x14400000 0 0x400>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,10 @@
|
|||
/dts-v1/;
|
||||
|
||||
/* Switch selection settings */
|
||||
#define SW_GPIO8_CAN0_STB 0
|
||||
#define SW_GPIO9_CAN1_STB 0
|
||||
#define SW_LCD_EN 0
|
||||
#define SW_PDM_EN 0
|
||||
#define SW_SD0_DEV_SEL 0
|
||||
#define SW_SDIO_M2E 0
|
||||
|
||||
|
|
@ -33,7 +37,56 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
|
|||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
#if (!SW_PDM_EN)
|
||||
channel1 {
|
||||
status = "okay";
|
||||
#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB)
|
||||
phys = <&can_transceiver1>;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (!SW_LCD_EN)
|
||||
channel4 {
|
||||
status = "okay";
|
||||
#if (SW_GPIO8_CAN0_STB)
|
||||
phys = <&can_transceiver0>;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (!SW_LCD_EN) && (SW_GPIO8_CAN0_STB)
|
||||
&can_transceiver0 {
|
||||
standby-gpios = <&pinctrl RZG3E_GPIO(5, 4) GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB)
|
||||
&can_transceiver1 {
|
||||
standby-gpios = <&pinctrl RZG3E_GPIO(5, 5) GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&pinctrl {
|
||||
canfd_pins: canfd {
|
||||
can1_pins: can1 {
|
||||
pinmux = <RZG3E_PORT_PINMUX(L, 2, 3)>, /* RX */
|
||||
<RZG3E_PORT_PINMUX(L, 3, 3)>; /* TX */
|
||||
};
|
||||
|
||||
can4_pins: can4 {
|
||||
pinmux = <RZG3E_PORT_PINMUX(5, 2, 3)>, /* RX */
|
||||
<RZG3E_PORT_PINMUX(5, 3, 3)>; /* TX */
|
||||
};
|
||||
};
|
||||
|
||||
scif_pins: scif {
|
||||
pins = "SCIF_TXD", "SCIF_RXD";
|
||||
renesas,output-impedance = <1>;
|
||||
|
|
|
|||
|
|
@ -12,6 +12,17 @@
|
|||
* SW_SDIO_M2E:
|
||||
* 0 - SMARC SDIO signal is connected to uSD1
|
||||
* 1 - SMARC SDIO signal is connected to M.2 Key E connector
|
||||
*
|
||||
* Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the
|
||||
* corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS:
|
||||
*
|
||||
* SW_GPIO8_CAN0_STB:
|
||||
* 0 - Connect to GPIO8 PMOD (default)
|
||||
* 1 - Connect to CAN0 transceiver STB pin
|
||||
*
|
||||
* SW_GPIO9_CAN1_STB:
|
||||
* 0 - Connect to GPIO9 PMOD (default)
|
||||
* 1 - Connect to CAN1 transceiver STB pin
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
|
@ -27,6 +38,24 @@ aliases {
|
|||
serial3 = &scif0;
|
||||
mmc1 = &sdhi1;
|
||||
};
|
||||
|
||||
can_transceiver0: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <8000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can_transceiver1: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <8000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
|
|
|
|||
|
|
@ -38,6 +38,11 @@ can1-stb-hog {
|
|||
line-name = "can1_stb";
|
||||
};
|
||||
|
||||
gpt_pins: gpt {
|
||||
pinmux = <RZG2L_PORT_PINMUX(43, 0, 2)>, /* GTIOC4A */
|
||||
<RZG2L_PORT_PINMUX(43, 1, 2)>; /* GTIOC4B */
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
pins = "RIIC0_SDA", "RIIC0_SCL";
|
||||
input-enable;
|
||||
|
|
|
|||
|
|
@ -104,6 +104,14 @@ codec_endpoint: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
#if PMOD0_GPT
|
||||
&gpt {
|
||||
pinctrl-0 = <&gpt_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
#endif /* PMOD0_GPT */
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -6,12 +6,20 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Please set the switch position SYS.1 on the SoM and the corresponding macro
|
||||
* SW_SD0_DEV_SEL on the board DTS:
|
||||
* Please set the below switch position on the SoM and the corresponding macro
|
||||
* on the board DTS:
|
||||
*
|
||||
* SW_SD0_DEV_SEL:
|
||||
* Switch position SYS.1, Macro SW_SD0_DEV_SEL:
|
||||
* 0 - SD0 is connected to eMMC (default)
|
||||
* 1 - SD0 is connected to uSD0 card
|
||||
*
|
||||
* Switch position SYS.5, Macro SW_LCD_EN:
|
||||
* 0 - Select Misc. Signals routing
|
||||
* 1 - Select LCD
|
||||
*
|
||||
* Switch position BOOT.6, Macro SW_PDM_EN:
|
||||
* 0 - Select CAN routing
|
||||
* 1 - Select PDM
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@
|
|||
/ {
|
||||
model = "Renesas White Hawk Single board";
|
||||
compatible = "renesas,white-hawk-single";
|
||||
|
||||
aliases {
|
||||
ethernet3 = &tsn0;
|
||||
};
|
||||
};
|
||||
|
||||
&hscif0 {
|
||||
|
|
@ -53,7 +57,7 @@ &tsn0 {
|
|||
pinctrl-0 = <&tsn0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy3>;
|
||||
phy-handle = <&tsn0_phy>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
|
|
@ -63,7 +67,7 @@ mdio {
|
|||
reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
|
||||
reset-post-delay-us = <4000>;
|
||||
|
||||
phy3: ethernet-phy@0 {
|
||||
tsn0_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id002b.0980",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user