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Renesas DTS updates for v6.16

Browse Source 
- Add SDHI, ICU, I2C, PMIC, and GPU support on the RZ/G3E SoC and the
     RZ/G3E SoM and SMARC Carrier-II EVK development board,
   - Add internal SDHI regulator support on the RZ/V2H(P) SoC,
   - Add UFS tuning parameters in E-FUSE on the R-Car S4-8 ES1.2 SoC,
   - Add support for Ethernet ports C and D, I2C, keys, and SDHI on the
     RZ/N1D SoC and the RZN1D-DB and RZN1D-EB development and expansion
     boards,
   - Add initial support for the RZ/V2N (R9A09G056) and the RZ/V2N EVK
     board,
   - Add support for the Retronix Sparrow Hawk board, which is based on
     R-Car V4H ES3.0,
   - Add ISP core support on R-Car V3U, V4H, and V4M,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.16

  - Add SDHI, ICU, I2C, PMIC, and GPU support on the RZ/G3E SoC and the
    RZ/G3E SoM and SMARC Carrier-II EVK development board,
  - Add internal SDHI regulator support on the RZ/V2H(P) SoC,
  - Add UFS tuning parameters in E-FUSE on the R-Car S4-8 ES1.2 SoC,
  - Add support for Ethernet ports C and D, I2C, keys, and SDHI on the
    RZ/N1D SoC and the RZN1D-DB and RZN1D-EB development and expansion
    boards,
  - Add initial support for the RZ/V2N (R9A09G056) and the RZ/V2N EVK
    board,
  - Add support for the Retronix Sparrow Hawk board, which is based on
    R-Car V4H ES3.0,
  - Add ISP core support on R-Car V3U, V4H, and V4M,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  arm64: dts: renesas: r8a779h0: Add ISP core function block
  arm64: dts: renesas: r8a779g0: Add ISP core function block
  arm64: dts: renesas: r8a779a0: Add ISP core function block
  arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support
  arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52
  arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node
  arm64: dts: renesas: rzg3e-smarc-som: Add RAA215300 pmic support
  arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol
  ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe SD card port
  ARM: dts: renesas: r9a06g032: Describe SDHCI controllers
  arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
  arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe keys
  ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe I2C bus
  ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe I2C bus
  ARM: dts: renesas: r9a06g032: Describe I2C controllers
  ...

Link: https://lore.kernel.org/r/cover.1745582596.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-09 22:40:19 +02:00
commit 47ce18de8b
25 changed files with 2067 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
View File

@ -4,13 +4,13 @@
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
generation and control of clock signals for the IP modules, generation and
control of resets, and control over booting, low power consumption and power
supply domains.
@ -19,6 +19,7 @@ properties:
compatible:
enum:
- renesas,r9a09g047-cpg # RZ/G3E
- renesas,r9a09g056-cpg # RZ/V2N
- renesas,r9a09g057-cpg # RZ/V2H
reg:

2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -27,6 +27,7 @@ properties:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
- renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g056-pinctrl # RZ/V2N
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@ -145,6 +146,7 @@ allOf:
contains:
enum:
- renesas,r9a09g047-pinctrl
- renesas,r9a09g056-pinctrl
- renesas,r9a09g057-pinctrl
then:
properties:

1
Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
View File

@ -25,6 +25,7 @@ properties:
items:
- enum:
- renesas,r9a09g047-sys # RZ/G3E
- renesas,r9a09g056-sys # RZ/V2N
- renesas,r9a09g057-sys # RZ/V2H
reg:

15
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View File

@ -558,6 +558,21 @@ properties:
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
- const: renesas,r9a09g047
- description: RZ/V2N (R9A09G056)
items:
- enum:
- renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)
- enum:
- renesas,r9a09g056n41 # RZ/V2N
- renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
- renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support
- renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support
- renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support
- renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support
- renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support
- renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support
- const: renesas,r9a09g056
- description: RZ/V2H(P) (R9A09G057)
items:
- enum:

1
arch/arm/boot/dts/renesas/Makefile
View File

@ -30,4 +30,5 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
r9a06g032-rzn1d400-db.dtb \
r9a06g032-rzn1d400-eb.dtb \
sh73a0-kzm9g.dtb

110
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
View File

@ -8,8 +8,10 @@
/dts-v1/;
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/pcs-rzn1-miic.h>
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
#include "r9a06g032.dtsi"
@ -24,6 +26,68 @@ chosen {
aliases {
serial0 = &uart0;
};
keyboard {
compatible = "gpio-keys-polled";
poll-interval = <100>;
switch-1 {
linux,code = <KEY_1>;
label = "SW1-1";
debounce-interval = <20>;
gpios = <&pca9698 8 GPIO_ACTIVE_LOW>;
};
switch-2 {
linux,code = <KEY_2>;
label = "SW1-2";
debounce-interval = <20>;
gpios = <&pca9698 9 GPIO_ACTIVE_LOW>;
};
switch-3 {
linux,code = <KEY_3>;
label = "SW1-3";
debounce-interval = <20>;
gpios = <&pca9698 10 GPIO_ACTIVE_LOW>;
};
switch-4 {
linux,code = <KEY_4>;
label = "SW1-4";
debounce-interval = <20>;
gpios = <&pca9698 11 GPIO_ACTIVE_LOW>;
};
switch-5 {
linux,code = <KEY_5>;
label = "SW1-5";
debounce-interval = <20>;
gpios = <&pca9698 12 GPIO_ACTIVE_LOW>;
};
switch-6 {
linux,code = <KEY_6>;
label = "SW1-6";
debounce-interval = <20>;
gpios = <&pca9698 13 GPIO_ACTIVE_LOW>;
};
switch-7 {
linux,code = <KEY_7>;
label = "SW1-7";
debounce-interval = <20>;
gpios = <&pca9698 14 GPIO_ACTIVE_LOW>;
};
switch-8 {
linux,code = <KEY_8>;
label = "SW1-8";
debounce-interval = <20>;
gpios = <&pca9698 15 GPIO_ACTIVE_LOW>;
};
};
};
&can0 {
@ -57,6 +121,44 @@ fixed-link {
};
};
&i2c2 {
pinctrl-0 = <&pins_i2c2>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
pca9698: gpio@20 {
compatible = "nxp,pca9698";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* configure the analog switch to let i2c2 access the eeprom */
max4662-in1-hog {
gpio-hog;
gpios = <16 0>;
output-high;
};
max4662-in2-hog {
gpio-hog;
gpios = <17 0>;
output-low;
};
max4662-in3-hog {
gpio-hog;
gpios = <18 0>;
output-low;
};
};
/* Some revisions may have a 24cs64 at address 0x58 */
eeprom@50 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x50>;
};
};
&mii_conv4 {
renesas,miic-input = <MIIC_SWITCH_PORTB>;
status = "okay";
@ -114,6 +216,12 @@ pins_eth4: pins_eth4 {
bias-disable;
};
pins_i2c2: pins_i2c2 {
pinmux = <RZN1_PINMUX(115, RZN1_FUNC_I2C)>,
<RZN1_PINMUX(116, RZN1_FUNC_I2C)>;
drive-strength = <12>;
};
pins_mdio1: pins_mdio1 {
pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
<RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;

160
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts Normal file
View File

@ -0,0 +1,160 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZN1D-EB Board
*
* Copyright (C) 2023 Schneider-Electric
*
*/
#include <dt-bindings/leds/common.h>
#include "r9a06g032-rzn1d400-db.dts"
/ {
model = "RZN1D-EB Board";
compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db",
"renesas,r9a06g032";
};
&i2c2 {
/* Sensors are different across revisions. All are LM75B compatible */
sensor@49 {
compatible = "national,lm75b";
reg = <0x49>;
};
};
&mii_conv2 {
renesas,miic-input = <MIIC_SWITCH_PORTD>;
status = "okay";
};
&mii_conv3 {
renesas,miic-input = <MIIC_SWITCH_PORTC>;
status = "okay";
};
&pinctrl {
pins_eth1: pins-eth1 {
pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
drive-strength = <6>;
bias-disable;
};
pins_eth2: pins-eth2 {
pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
<RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
drive-strength = <6>;
bias-disable;
};
pins_sdio1: pins-sdio1 {
pinmux = <RZN1_PINMUX(95, RZN1_FUNC_SDIO)>,
<RZN1_PINMUX(97, RZN1_FUNC_SDIO)>,
<RZN1_PINMUX(98, RZN1_FUNC_SDIO)>,
<RZN1_PINMUX(99, RZN1_FUNC_SDIO)>,
<RZN1_PINMUX(100, RZN1_FUNC_SDIO)>,
<RZN1_PINMUX(101, RZN1_FUNC_SDIO_E)>,
<RZN1_PINMUX(102, RZN1_FUNC_SDIO_E)>;
};
pins_sdio1_clk: pins-sdio1-clk {
pinmux = <RZN1_PINMUX(96, RZN1_FUNC_SDIO)>;
drive-strength = <12>;
};
};
&sdio1 {
pinctrl-0 = <&pins_sdio1>, <&pins_sdio1_clk>;
pinctrl-names = "default";
status = "okay";
};
&switch {
pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
<&pins_mdio1>;
mdio {
/* CN15 and CN16 switches must be configured in MDIO2 mode */
switch0phy1: ethernet-phy@1 {
reg = <1>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_ACTIVITY;
default-state = "keep";
};
};
};
switch0phy10: ethernet-phy@10 {
reg = <10>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_ACTIVITY;
default-state = "keep";
};
};
};
};
};
&switch_port2 {
label = "lan2";
phy-mode = "rgmii-id";
phy-handle = <&switch0phy10>;
status = "okay";
};
&switch_port3 {
label = "lan3";
phy-mode = "rgmii-id";
phy-handle = <&switch0phy1>;
status = "okay";
};

46
arch/arm/boot/dts/renesas/r9a06g032.dtsi
View File

@ -268,6 +268,28 @@ uart7: serial@50004000 {
status = "disabled";
};
i2c1: i2c@40063000 {
compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
reg = <0x40063000 0x100>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>;
clock-names = "ref", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@40064000 {
compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
reg = <0x40064000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>;
clock-names = "ref", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
@ -276,6 +298,30 @@ pinctrl: pinctrl@40067000 {
status = "okay";
};
sdio1: mmc@40100000 {
compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
reg = <0x40100000 0x1000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int", "wakeup";
clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>;
clock-names = "clk_xin", "clk_ahb";
no-1-8-v;
status = "disabled";
};
sdio2: mmc@40101000 {
compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
reg = <0x40101000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int", "wakeup";
clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>;
clock-names = "clk_xin", "clk_ahb";
no-1-8-v;
status = "disabled";
};
nand_controller: nand-controller@40102000 {
compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
reg = <0x40102000 0x2000>;

6
arch/arm64/boot/dts/renesas/Makefile
View File

@ -94,6 +94,10 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb
r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb
r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb
@ -152,6 +156,8 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb

60
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -2588,13 +2588,20 @@ du_out_dsi1: endpoint {
isp0: isp@fed00000 {
compatible = "renesas,r8a779a0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed00000 0 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 612>;
reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
resets = <&cpg 612>;
resets = <&cpg 612>, <&cpg 16>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2672,13 +2679,20 @@ isp0vin07: endpoint {
isp1: isp@fed20000 {
compatible = "renesas,r8a779a0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed20000 0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 613>;
reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
resets = <&cpg 613>;
resets = <&cpg 613>, <&cpg 17>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2756,13 +2770,20 @@ isp1vin15: endpoint {
isp2: isp@fed30000 {
compatible = "renesas,r8a779a0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed30000 0 0x10000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 614>;
reg = <0 0xfed30000 0 0x10000>, <0 0xfef00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 614>, <&cpg CPG_MOD 18>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
resets = <&cpg 614>;
resets = <&cpg 614>, <&cpg 18>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2840,13 +2861,20 @@ isp2vin23: endpoint {
isp3: isp@fed40000 {
compatible = "renesas,r8a779a0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed40000 0 0x10000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 615>;
reg = <0 0xfed40000 0 0x10000>, <0 0xfe400000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 615>, <&cpg CPG_MOD 19>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
resets = <&cpg 615>;
resets = <&cpg 615>, <&cpg 19>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx3>;
ports {
#address-cells = <1>;
#size-cells = <0>;

17
arch/arm64/boot/dts/renesas/r8a779f4.dtsi
View File

@ -10,3 +10,20 @@
/ {
compatible = "renesas,r8a779f4", "renesas,r8a779f0";
};
&fuse {
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
ufs_tune: calib@144 {
reg = <0x144 0x08>;
};
};
};
&ufs {
nvmem-cells = <&ufs_tune>;
nvmem-cell-names = "calibration";
};

30
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -2277,13 +2277,20 @@ du_out_dsi1: endpoint {
isp0: isp@fed00000 {
compatible = "renesas,r8a779g0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed00000 0 0x10000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 612>;
reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779G0_PD_A3ISP0>;
resets = <&cpg 612>;
resets = <&cpg 612>, <&cpg 16>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2361,13 +2368,20 @@ isp0vin07: endpoint {
isp1: isp@fed20000 {
compatible = "renesas,r8a779g0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed20000 0 0x10000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 613>;
reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779G0_PD_A3ISP1>;
resets = <&cpg 613>;
resets = <&cpg 613>, <&cpg 17>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx1>;
ports {
#address-cells = <1>;
#size-cells = <0>;

43
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso Normal file
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN
* on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*
* Example usage:
*
* # Localize hwmon sysfs directory that matches the PWM fan,
* # enable the PWM fan, and configure the fan speed manually.
* r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name
* /sys/class/hwmon/hwmon0/name:sensor1_thermal
* /sys/class/hwmon/hwmon1/name:sensor2_thermal
* /sys/class/hwmon/hwmon2/name:sensor3_thermal
* /sys/class/hwmon/hwmon3/name:sensor4_thermal
* /sys/class/hwmon/hwmon4/name:pwmfan
* ^ ^^^^^^
*
* # Select mode 2 , enable fan PWM and regulator and keep them enabled.
* # For details, see Linux Documentation/hwmon/pwm-fan.rst
* r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable
*
* # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed .
* # Fan speed 101 is about 2/5 of the PWM fan speed:
* r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1
*/
/dts-v1/;
/plugin/;
/*
* Override default PWM fan settings. For a list of available properties,
* see schema Documentation/devicetree/bindings/hwmon/pwm-fan.yaml .
*/
&fan {
/* Available cooling levels */
cooling-levels = <0 50 100 150 200 255>;
/* Four pulses of tacho signal per one revolution */
pulses-per-revolution = <4>;
/* PWM period: 100us ~= 10 kHz */
pwms = <&pwm0 0 100000>;
};

666
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts Normal file
View File

@ -0,0 +1,666 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r8a779g3.dtsi"
/ {
model = "Retronix Sparrow Hawk board based on r8a779g3";
compatible = "retronix,sparrow-hawk", "renesas,r8a779g3",
"renesas,r8a779g0";
aliases {
ethernet0 = &avb0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &hscif1;
serial2 = &hscif3;
spi0 = &rpc;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
/* Page 31 / FAN */
fan: pwm-fan {
pinctrl-0 = <&irq4_pins>;
pinctrl-names = "default";
compatible = "pwm-fan";
#cooling-cells = <2>;
interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>;
/*
* The fan model connected to this device can be selected
* by user. Set "cooling-levels" DT property to single 255
* entry to force the fan PWM into constant HIGH, which
* forces the fan to spin at maximum RPM, thus providing
* maximum cooling to this device and protection against
* misconfigured PWM duty cycle to the fan.
*
* User has to configure "pwms" and "pulses-per-revolution"
* DT properties according to fan datasheet first, and then
* extend "cooling-levels = <0 m n ... 255>" property to
* achieve proper fan control compatible with fan model
* installed by user.
*/
cooling-levels = <255>;
pulses-per-revolution = <2>;
pwms = <&pwm0 0 50000>;
};
/*
* Page 15 / LPDDR5
*
* This configuration listed below is for the 8 GiB board variant
* with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board.
*
* A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on
* the board is automatically handled by the bootloader, which
* adjusts the correct DRAM size into the memory nodes below.
*/
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
/* Page 27 / DSI to Display */
mini-dp-con {
compatible = "dp-connector";
label = "CN6";
type = "full-size";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* Page 27 / DSI to Display */
sn65dsi86_refclk: clk-x9 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
/* Page 17 uSD-Slot */
vcc_sdhi: regulator-vcc-sdhi {
compatible = "regulator-gpio";
regulator-name = "SDHI VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 0>, <1800000 1>;
};
};
/* Page 22 / Ether_AVB0 */
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&avb0_phy>;
tx-internal-delay-ps = <2000>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
/* AVB0_PHY_INT_V */
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
/* GP7_10/AVB0_RESETN_V */
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
/* Page 28 / CANFD_IF */
&can_clk {
clock-frequency = <40000000>;
};
/* Page 28 / CANFD_IF */
&canfd {
pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel3 {
status = "okay";
};
channel4 {
status = "okay";
};
};
/* Page 27 / DSI to Display */
&dsi1 {
status = "okay";
ports {
port@1 {
dsi1_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
/* Page 27 / DSI to Display */
&du {
status = "okay";
};
/* Page 5 / R-Car V4H_INT_I2C */
&extal_clk { /* X3 */
clock-frequency = <16666666>;
};
/* Page 5 / R-Car V4H_INT_I2C */
&extalr_clk { /* X2 */
clock-frequency = <32768>;
};
/* Page 26 / 2230 Key M M.2 */
&gpio4 {
/* 9FGV0441 nOE inputs 0 and 1 */
pcie-m2-oe-hog {
gpio-hog;
gpios = <21 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PCIe-CLK-nOE-M2";
};
/* 9FGV0441 nOE inputs 2 and 3 */
pcie-usb-oe-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PCIe-CLK-nOE-USB";
};
};
/* Page 23 / DEBUG */
&hscif0 { /* FTDI ADBUS[3:0] */
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bootph-all;
status = "okay";
};
/* Page 23 / DEBUG */
&hscif1 { /* FTDI BDBUS[3:0] */
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
/* Page 24 / UART */
&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */
pinctrl-0 = <&hscif3_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 24 / I2C SWITCH */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
mux@71 {
compatible = "nxp,pca9544"; /* TCA9544 */
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
vdd-supply = <&reg_3p3v>;
i2c0_mux0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
/* Page 27 / DSI to Display */
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
i2c0_mux1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c0_mux2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c0_mux3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* Page 29 / CSI_IF_CN / CAM_CN0 */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
/* Page 29 / CSI_IF_CN / CAM_CN1 */
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
};
/* Page 31 / IO_CN */
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
};
/* Page 31 / IO_CN */
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
};
/* Page 17 uSD-Slot */
&mmc0 {
pinctrl-0 = <&sd_pins>;
pinctrl-1 = <&sd_uhs_pins>;
pinctrl-names = "default", "state_uhs";
bus-width = <4>;
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vcc_sdhi>;
status = "okay";
};
/* Page 26 / 2230 Key M M.2 */
&pcie0_clkref {
clock-frequency = <100000000>;
};
&pciec0 {
reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* Page 25 / PCIe to USB */
&pcie1_clkref {
clock-frequency = <100000000>;
};
&pciec1 {
/* uPD720201 is PCIe Gen2 x1 device */
num-lanes = <1>;
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
/* Page 22 / Ether_AVB0 */
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins-mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins-mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
/* Page 28 / CANFD_IF */
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
/* Page 28 / CANFD_IF */
canfd3_pins: canfd3 {
groups = "canfd3_data";
function = "canfd3";
};
/* Page 28 / CANFD_IF */
canfd4_pins: canfd4 {
groups = "canfd4_data";
function = "canfd4";
};
/* Page 23 / DEBUG */
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
/* Page 23 / DEBUG */
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
/* Page 24 / UART */
hscif3_pins: hscif3 {
groups = "hscif3_data_a";
function = "hscif3";
};
/* Page 24 / I2C SWITCH */
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
/* Page 29 / CSI_IF_CN / CAM_CN0 */
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
/* Page 29 / CSI_IF_CN / CAM_CN1 */
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
/* Page 31 / IO_CN */
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
/* Page 31 / IO_CN */
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
/* Page 18 / POWER_CORE */
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
/* Page 27 / DSI to Display */
irq0_pins: irq0 {
groups = "intc_ex_irq0_a";
function = "intc_ex";
};
/* Page 31 / FAN */
irq4_pins: irq4 {
groups = "intc_ex_irq4_b";
function = "intc_ex";
};
/* Page 31 / FAN */
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
/* Page 31 / CN7 pin 12 */
pwm1_pins: pwm1 {
groups = "pwm1_b";
function = "pwm1";
};
/* Page 31 / CN7 pin 32 */
pwm6_pins: pwm6 {
groups = "pwm6";
function = "pwm6";
};
/* Page 31 / CN7 pin 33 */
pwm7_pins: pwm7 {
groups = "pwm7";
function = "pwm7";
};
/* Page 16 / QSPI_FLASH */
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
bootph-all;
};
/* Page 6 / SCIF_CLK_SOC_V */
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
/* Page 17 uSD-Slot */
sd_pins: sd {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
/* Page 17 uSD-Slot */
sd_uhs_pins: sd-uhs {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
};
/* Page 31 / FAN */
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 12 */
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 32 */
&pwm6 {
pinctrl-0 = <&pwm6_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 33 */
&pwm7 {
pinctrl-0 = <&pwm7_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 16 / QSPI_FLASH */
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
bootph-all;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1000000>;
read-only;
};
user@1000000 {
reg = <0x1000000 0x2f80000>;
};
env1@3f80000 {
reg = <0x3f80000 0x40000>;
};
env2@3fc0000 {
reg = <0x3fc0000 0x40000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
/* Page 6 / SCIF_CLK_SOC_V */
&scif_clk { /* X12 */
clock-frequency = <24000000>;
};

21
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
View File

@ -1968,13 +1968,20 @@ du_out_dsi0: endpoint {
isp0: isp@fed00000 {
compatible = "renesas,r8a779h0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed00000 0 0x10000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 612>;
reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779H0_PD_A3ISP0>;
resets = <&cpg 612>;
resets = <&cpg 612>, <&cpg 16>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2053,10 +2060,14 @@ isp1: isp@fed20000 {
compatible = "renesas,r8a779h0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed20000 0 0x10000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
reg-names = "cs";
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs";
clocks = <&cpg CPG_MOD 613>;
clock-names = "cs";
power-domains = <&sysc R8A779H0_PD_A3ISP0>;
resets = <&cpg 613>;
reset-names = "cs";
status = "disabled";
ports {

199
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -105,6 +105,35 @@ L3_CA55: cache-controller-0 {
};
};
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-630000000 {
opp-hz = /bits/ 64 <630000000>;
opp-microvolt = <800000>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-microvolt = <800000>;
};
opp-157500000 {
opp-hz = /bits/ 64 <157500000>;
opp-microvolt = <800000>;
};
opp-78750000 {
opp-hz = /bits/ 64 <78750000>;
opp-microvolt = <800000>;
};
opp-19687500 {
opp-hz = /bits/ 64 <19687500>;
opp-microvolt = <800000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -131,6 +160,95 @@ soc: soc {
#size-cells = <2>;
ranges;
icu: interrupt-controller@10400000 {
compatible = "renesas,r9a09g047-icu";
reg = <0 0x10400000 0 0x10000>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"port_irq0", "port_irq1", "port_irq2",
"port_irq3", "port_irq4", "port_irq5",
"port_irq6", "port_irq7", "port_irq8",
"port_irq9", "port_irq10", "port_irq11",
"port_irq12", "port_irq13", "port_irq14",
"port_irq15",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"int-ca55-0", "int-ca55-1",
"int-ca55-2", "int-ca55-3",
"icu-error-ca55",
"gpt-u0-gtciada", "gpt-u0-gtciadb",
"gpt-u1-gtciada", "gpt-u1-gtciadb";
clocks = <&cpg CPG_MOD 0x5>;
power-domains = <&cpg>;
resets = <&cpg 0x36>;
};
pinctrl: pinctrl@10410000 {
compatible = "renesas,r9a09g047-pinctrl";
reg = <0 0x10410000 0 0x10000>;
@ -140,6 +258,7 @@ pinctrl: pinctrl@10410000 {
gpio-ranges = <&pinctrl 0 0 232>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&icu>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
};
@ -401,6 +520,26 @@ i2c8: i2c@11c01000 {
status = "disabled";
};
gpu: gpu@14850000 {
compatible = "renesas,r9a09g047-mali",
"arm,mali-bifrost";
reg = <0x0 0x14850000 0x0 0x10000>;
interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu", "event";
clocks = <&cpg CPG_MOD 0xf0>,
<&cpg CPG_MOD 0xf1>,
<&cpg CPG_MOD 0xf2>;
clock-names = "gpu", "bus", "bus_ace";
power-domains = <&cpg>;
resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>;
reset-names = "rst", "axi_rst", "ace_rst";
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
gic: interrupt-controller@14900000 {
compatible = "arm,gic-v3";
reg = <0x0 0x14900000 0 0x20000>,
@ -410,6 +549,66 @@ gic: interrupt-controller@14900000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
<&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa7>;
power-domains = <&cpg>;
status = "disabled";
sdhi0_vqmmc: vqmmc-regulator {
regulator-name = "SDHI0-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi1: mmc@15c10000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c10000 0 0x10000>;
interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
<&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa8>;
power-domains = <&cpg>;
status = "disabled";
sdhi1_vqmmc: vqmmc-regulator {
regulator-name = "SDHI1-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi2: mmc@15c20000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c20000 0 0x10000>;
interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
<&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa9>;
power-domains = <&cpg>;
status = "disabled";
sdhi2_vqmmc: vqmmc-regulator {
regulator-name = "SDHI2-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
};
timer {

49
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
View File

@ -7,6 +7,11 @@
/dts-v1/;
/* Switch selection settings */
#define SW_SD0_DEV_SEL 0
#define SW_SDIO_M2E 0
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
#include "r9a09g047e57.dtsi"
#include "rzg3e-smarc-som.dtsi"
@ -16,6 +21,16 @@ / {
model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
"renesas,r9a09g047e57", "renesas,r9a09g047";
vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
compatible = "regulator-gpio";
regulator-name = "SD1_PVDD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG3E_GPIO(1, 5) GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
};
};
&pinctrl {
@ -23,9 +38,43 @@ scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG3E_GPIO(1, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1-cd {
pinmux = <RZG3E_PORT_PINMUX(1, 4, 8)>; /* SD1CD */
};
sd1-ctrl {
pinmux = <RZG3E_PORT_PINMUX(G, 0, 1)>, /* SD1CLK */
<RZG3E_PORT_PINMUX(G, 1, 1)>; /* SD1CMD */
};
sd1-data {
pinmux = <RZG3E_PORT_PINMUX(G, 2, 1)>, /* SD1DAT0 */
<RZG3E_PORT_PINMUX(G, 3, 1)>, /* SD1DAT1 */
<RZG3E_PORT_PINMUX(G, 4, 1)>, /* SD1DAT2 */
<RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
};
};
};
&scif0 {
pinctrl-0 = <&scif_pins>;
pinctrl-names = "default";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};

282
arch/arm64/boot/dts/renesas/r9a09g056.dtsi Normal file
View File

@ -0,0 +1,282 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2N SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
#define RZV2N_P0 0
#define RZV2N_P1 1
#define RZV2N_P2 2
#define RZV2N_P3 3
#define RZV2N_P4 4
#define RZV2N_P5 5
#define RZV2N_P6 6
#define RZV2N_P7 7
#define RZV2N_P8 8
#define RZV2N_P9 9
#define RZV2N_PA 10
#define RZV2N_PB 11
#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin)
/ {
compatible = "renesas,r9a09g056";
#address-cells = <2>;
#size-cells = <2>;
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/*
* The default cluster table is based on the assumption that the PLLCA55 clock
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
* 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
* clocked to 1.8GHz as well). The table below should be overridden in the board
* DTS based on the PLLCA55 clock frequency.
*/
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
};
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
};
opp-425000000 {
opp-hz = /bits/ 64 <425000000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
};
opp-212500000 {
opp-hz = /bits/ 64 <212500000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x200>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x300>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-level = <3>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
qextal_clk: qextal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
rtxin_clk: rtxin-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
pinctrl: pinctrl@10410000 {
compatible = "renesas,r9a09g056-pinctrl";
reg = <0 0x10410000 0 0x10000>;
clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 96>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
};
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g056-cpg";
reg = <0 0x10420000 0 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sys: system-controller@10430000 {
compatible = "renesas,r9a09g056-sys";
reg = <0 0x10430000 0 0x10000>;
clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>;
resets = <&cpg 0x30>;
};
scif: serial@11c01400 {
compatible = "renesas,scif-r9a09g056",
"renesas,scif-r9a09g057";
reg = <0 0x11c01400 0 0x400>;
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eri", "rxi", "txi", "bri", "dri",
"tei", "tei-dri", "rxi-edge", "txi-edge";
clocks = <&cpg CPG_MOD 0x8f>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg 0x95>;
status = "disabled";
};
gic: interrupt-controller@14900000 {
compatible = "arm,gic-v3";
reg = <0x0 0x14900000 0 0x20000>,
<0x0 0x14940000 0 0x80000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
<&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa7>;
power-domains = <&cpg>;
status = "disabled";
sdhi0_vqmmc: vqmmc-regulator {
regulator-name = "SDHI0-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi1: mmc@15c10000 {
compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c10000 0 0x10000>;
interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
<&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa8>;
power-domains = <&cpg>;
status = "disabled";
sdhi1_vqmmc: vqmmc-regulator {
regulator-name = "SDHI1-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi2: mmc@15c20000 {
compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c20000 0 0x10000>;
interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
<&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg 0xa9>;
power-domains = <&cpg>;
status = "disabled";
sdhi2_vqmmc: vqmmc-regulator {
regulator-name = "SDHI2-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

114
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts Normal file
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@ -0,0 +1,114 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2N EVK board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r9a09g056.dtsi"
/ {
model = "Renesas RZ/V2N EVK Board based on r9a09g056n48";
compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
aliases {
mmc1 = &sdhi1;
serial0 = &scif;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x1 0xf8000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VqmmC";
gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
};
};
&audio_extal_clk {
clock-frequency = <22579200>;
};
&pinctrl {
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1-cd {
pinmux = <RZV2N_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
};
sd1-clk {
pins = "SD1CLK";
renesas,output-impedance = <3>;
slew-rate = <0>;
};
sd1-dat-cmd {
pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
input-enable;
renesas,output-impedance = <3>;
slew-rate = <0>;
};
};
};
&qextal_clk {
clock-frequency = <24000000>;
};
&rtxin_clk {
clock-frequency = <32768>;
};
&scif {
pinctrl-0 = <&scif_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vqmmc_sdhi1>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};

21
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@ -653,6 +653,13 @@ sdhi0: mmc@15c00000 {
resets = <&cpg 0xa7>;
power-domains = <&cpg>;
status = "disabled";
sdhi0_vqmmc: vqmmc-regulator {
regulator-name = "SDHI0-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi1: mmc@15c10000 {
@ -666,6 +673,13 @@ sdhi1: mmc@15c10000 {
resets = <&cpg 0xa8>;
power-domains = <&cpg>;
status = "disabled";
sdhi1_vqmmc: vqmmc-regulator {
regulator-name = "SDHI1-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi2: mmc@15c20000 {
@ -679,6 +693,13 @@ sdhi2: mmc@15c20000 {
resets = <&cpg 0xa9>;
power-domains = <&cpg>;
status = "disabled";
sdhi2_vqmmc: vqmmc-regulator {
regulator-name = "SDHI2-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
};

18
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
View File

@ -5,6 +5,15 @@
* Copyright (C) 2024 Renesas Electronics Corp.
*/
/*
* Please set the switch position SW_OPT_MUX.1 on the carrier board and the
* corresponding macro SW_SDIO_M2E on the board DTS:
*
* SW_SDIO_M2E:
* 0 - SMARC SDIO signal is connected to uSD1
* 1 - SMARC SDIO signal is connected to M.2 Key E connector
*/
/ {
model = "Renesas RZ SMARC Carrier-II Board";
compatible = "renesas,smarc2-evk";
@ -16,9 +25,18 @@ chosen {
aliases {
serial3 = &scif0;
mmc1 = &sdhi1;
};
};
&scif0 {
status = "okay";
};
&sdhi1 {
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};

2
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@ -327,7 +327,7 @@ &sbc {
status = "okay";
flash@0 {
compatible = "micron,mt25qu512a", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
m25p,fast-read;
spi-max-frequency = <50000000>;

2
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@ -246,7 +246,7 @@ &sbc {
status = "okay";
flash@0 {
compatible = "micron,mt25qu512a", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
m25p,fast-read;
spi-max-frequency = <50000000>;

207
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
View File

@ -5,20 +5,177 @@
* Copyright (C) 2024 Renesas Electronics Corp.
*/
/*
* Please set the switch position SYS.1 on the SoM and the corresponding macro
* SW_SD0_DEV_SEL on the board DTS:
*
* SW_SD0_DEV_SEL:
* 0 - SD0 is connected to eMMC (default)
* 1 - SD0 is connected to uSD0 card
*/
/ {
compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
aliases {
i2c2 = &i2c2;
mmc0 = &sdhi0;
mmc2 = &sdhi2;
};
memory@48000000 {
device_type = "memory";
/* First 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0xf8000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd0p8v_others: regulator-vdd0p8v-others {
compatible = "regulator-fixed";
regulator-name = "fixed-0.8V";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* 32.768kHz crystal */
x3: x3-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&audio_extal_clk {
clock-frequency = <48000000>;
};
&gpu {
status = "okay";
mali-supply = <&reg_vdd0p8v_others>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
clock-frequency = <1000000>;
status = "okay";
raa215300: pmic@12 {
compatible = "renesas,raa215300";
reg = <0x12>, <0x6f>;
reg-names = "main", "rtc";
clocks = <&x3>;
clock-names = "xin";
pinctrl-0 = <&rtc_irq_pin>;
pinctrl-names = "default";
interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
};
};
&pinctrl {
i2c2_pins: i2c {
pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
};
rtc_irq_pin: rtc-irq {
pins = "PS1";
bias-pull-up;
};
sdhi0_emmc_pins: sd0-emmc {
sd0-ctrl {
pins = "SD0CLK", "SD0CMD";
renesas,output-impedance = <3>;
};
sd0-data {
pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
"SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
renesas,output-impedance = <3>;
};
sd0-rst {
pins = "SD0RSTN";
renesas,output-impedance = <3>;
};
};
sdhi0_usd_pins: sd0-usd {
sd0-cd {
pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
};
sd0-ctrl {
pins = "SD0CLK", "SD0CMD";
renesas,output-impedance = <3>;
};
sd0-data {
pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
renesas,output-impedance = <3>;
};
sd0-iovs {
pins = "SD0IOVS";
renesas,output-impedance = <3>;
};
sd0-pwen {
pins = "SD0PWEN";
renesas,output-impedance = <3>;
};
};
sdhi2_pins: sd2 {
sd2-cd {
pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
};
sd2-ctrl {
pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
<RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
};
sd2-data {
pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
<RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
<RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
<RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
};
sd2-iovs {
pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
};
sd2-pwen {
pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
};
};
};
&qextal_clk {
clock-frequency = <24000000>;
};
@ -27,6 +184,56 @@ &rtxin_clk {
clock-frequency = <32768>;
};
#if (SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_usd_pins>;
pinctrl-1 = <&sdhi0_usd_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&sdhi0_vqmmc>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi0_vqmmc {
status = "okay";
};
#else
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&sdhi2_vqmmc>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi2_vqmmc {
status = "okay";
};
&wdt1 {
status = "okay";
};

24
include/dt-bindings/clock/renesas,r9a09g056-cpg.h Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Core Clock list */
#define R9A09G056_SYS_0_PCLK 0
#define R9A09G056_CA55_0_CORE_CLK0 1
#define R9A09G056_CA55_0_CORE_CLK1 2
#define R9A09G056_CA55_0_CORE_CLK2 3
#define R9A09G056_CA55_0_CORE_CLK3 4
#define R9A09G056_CA55_0_PERIPHCLK 5
#define R9A09G056_CM33_CLK0 6
#define R9A09G056_CST_0_SWCLKTCK 7
#define R9A09G056_IOTOP_0_SHCLK 8
#define R9A09G056_USB2_0_CLK_CORE0 9
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */