arm64: dts: renesas: r8a779h0: Add ISP core function block

The first ISP instance on V4M has both a channel select and core
function block, describe the core region in addition to the existing cs
region. While at it update the second ISP to match the new bindings and
add the reg-names and interrupt-names property.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250423163113.2961049-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Niklas Söderlund 2025-04-23 18:31:10 +02:00 committed by Geert Uytterhoeven
parent c1f22633c2
commit 9f78a29caa

View File

@ -1968,13 +1968,20 @@ du_out_dsi0: endpoint {
isp0: isp@fed00000 {
compatible = "renesas,r8a779h0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed00000 0 0x10000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 612>;
reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
reg-names = "cs", "core";
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs", "core";
clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
clock-names = "cs", "core";
power-domains = <&sysc R8A779H0_PD_A3ISP0>;
resets = <&cpg 612>;
resets = <&cpg 612>, <&cpg 16>;
reset-names = "cs", "core";
status = "disabled";
renesas,vspx = <&vspx0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2053,10 +2060,14 @@ isp1: isp@fed20000 {
compatible = "renesas,r8a779h0-isp",
"renesas,rcar-gen4-isp";
reg = <0 0xfed20000 0 0x10000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
reg-names = "cs";
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cs";
clocks = <&cpg CPG_MOD 613>;
clock-names = "cs";
power-domains = <&sysc R8A779H0_PD_A3ISP0>;
resets = <&cpg 613>;
reset-names = "cs";
status = "disabled";
ports {