From 9c1d49dd0975cd91529417a70a34817e489d954b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 20 Mar 2025 16:41:16 +0000 Subject: [PATCH 01/14] arm64: dts: renesas: r9a09g047: Add CANFD node Add CANFD node to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250320164121.193857-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 9ab83e949c0e..876f70fed433 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -301,6 +301,66 @@ scif0: serial@11c01400 { status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From f2858ea240d35ed35dc87108cf8b06685e89a421 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 20 Mar 2025 16:41:17 +0000 Subject: [PATCH 02/14] arm64: dts: renesas: r9a09g047e57-smarc: Enable CANFD Enable CANFD on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250320164121.193857-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 31 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 4 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 14 +++++++-- 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 5d7983812c70..7e1daaabce8a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,6 +8,8 @@ /dts-v1/; /* Switch selection settings */ +#define SW_LCD_EN 0 +#define SW_PDM_EN 0 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 @@ -33,7 +35,36 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { }; }; +&canfd { + pinctrl-0 = <&canfd_pins>; + pinctrl-names = "default"; + +#if (!SW_PDM_EN) + channel1 { + status = "okay"; + }; +#endif + +#if (!SW_LCD_EN) + channel4 { + status = "okay"; + }; +#endif +}; + &pinctrl { + canfd_pins: canfd { + can1_pins: can1 { + pinmux = , /* RX */ + ; /* TX */ + }; + + can4_pins: can4 { + pinmux = , /* RX */ + ; /* TX */ + }; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index fd82df8adc1e..1d3a844174b3 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -29,6 +29,10 @@ aliases { }; }; +&canfd { + status = "okay"; +}; + &scif0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 7c7c7e5f4361..43d79158d81a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -6,12 +6,20 @@ */ /* - * Please set the switch position SYS.1 on the SoM and the corresponding macro - * SW_SD0_DEV_SEL on the board DTS: + * Please set the below switch position on the SoM and the corresponding macro + * on the board DTS: * - * SW_SD0_DEV_SEL: + * Switch position SYS.1, Macro SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card + * + * Switch position SYS.5, Macro SW_LCD_EN: + * 0 - Select Misc. Signals routing + * 1 - Select LCD + * + * Switch position BOOT.6, Macro SW_PDM_EN: + * 0 - Select CAN routing + * 1 - Select PDM */ / { From 99256644c8c9523e27312f6318058481943281ab Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 20 Mar 2025 16:41:18 +0000 Subject: [PATCH 03/14] arm64: dts: renesas: r9a09g047e57-smarc: Enable CAN Transceiver Enable TCAN1046V-Q1 CAN Transceiver populated on RZ/G3E SMARC EVK by modelling it as two instances of tcan1042. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250320164121.193857-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 22 ++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 25 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 7e1daaabce8a..1f5e61a73c35 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,6 +8,8 @@ /dts-v1/; /* Switch selection settings */ +#define SW_GPIO8_CAN0_STB 0 +#define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 #define SW_SD0_DEV_SEL 0 @@ -42,16 +44,36 @@ &canfd { #if (!SW_PDM_EN) channel1 { status = "okay"; +#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) + phys = <&can_transceiver1>; +#endif }; #endif #if (!SW_LCD_EN) channel4 { status = "okay"; +#if (SW_GPIO8_CAN0_STB) + phys = <&can_transceiver0>; +#endif }; #endif }; +#if (!SW_LCD_EN) && (SW_GPIO8_CAN0_STB) +&can_transceiver0 { + standby-gpios = <&pinctrl RZG3E_GPIO(5, 4) GPIO_ACTIVE_HIGH>; + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_GPIO9_CAN1_STB) +&can_transceiver1 { + standby-gpios = <&pinctrl RZG3E_GPIO(5, 5) GPIO_ACTIVE_HIGH>; + status = "okay"; +}; +#endif + &pinctrl { canfd_pins: canfd { can1_pins: can1 { diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 1d3a844174b3..afdc1940e24a 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -12,6 +12,17 @@ * SW_SDIO_M2E: * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector + * + * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the + * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS: + * + * SW_GPIO8_CAN0_STB: + * 0 - Connect to GPIO8 PMOD (default) + * 1 - Connect to CAN0 transceiver STB pin + * + * SW_GPIO9_CAN1_STB: + * 0 - Connect to GPIO9 PMOD (default) + * 1 - Connect to CAN1 transceiver STB pin */ / { @@ -27,6 +38,20 @@ aliases { serial3 = &scif0; mmc1 = &sdhi1; }; + + can_transceiver0: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + status = "disabled"; + }; + + can_transceiver1: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + status = "disabled"; + }; }; &canfd { From 06534edc0d366b9904c221de77068616d7b5af32 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 14 Apr 2025 12:01:13 +0200 Subject: [PATCH 04/14] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Add GMAC1 port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This port bypasses the switch and is directly connected to the GMAC. Co-developed-by: Niklas Söderlund Signed-off-by: Niklas Söderlund Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250414100206.7185-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a06g032-rzn1d400-eb.dts | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index e539df514d1e..7f721720f647 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -15,6 +15,44 @@ / { "renesas,r9a06g032"; }; +&gmac1 { + pinctrl-0 = <&pins_eth0>, <&pins_mdio0>; + pinctrl-names = "default"; + + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy_mii0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_mii0: ethernet-phy@8 { + reg = <8>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + }; + }; + }; + }; +}; + &i2c2 { /* Sensors are different across revisions. All are LM75B compatible */ sensor@49 { @@ -23,6 +61,11 @@ sensor@49 { }; }; +&mii_conv1 { + renesas,miic-input = ; + status = "okay"; +}; + &mii_conv2 { renesas,miic-input = ; status = "okay"; @@ -34,6 +77,23 @@ &mii_conv3 { }; &pinctrl { + pins_eth0: pins-eth0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <6>; + bias-disable; + }; + pins_eth1: pins-eth1 { pinmux = , , @@ -68,6 +128,11 @@ pins_eth2: pins-eth2 { bias-disable; }; + pins_mdio0: pins-mdio0 { + pinmux = , + ; + }; + pins_sdio1: pins-sdio1 { pinmux = , , From ca764d5321a2cee7c4901b981bb0be06d8d9a9d7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 17 Apr 2025 23:23:36 +0000 Subject: [PATCH 05/14] arm64: dts: renesas: sparrow-hawk: Add MSIOF Sound support Sparrow Hawk has Headset (CONN3) AUX_IN (CONN4) for Sound input/output which is using MSIOF. Support it. Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/87plha2wzr.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/874ixxcg3w.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779g3-sparrow-hawk.dts | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index b109095a0d87..6955eafd8d6a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -4,6 +4,37 @@ * * Copyright (C) 2025 Marek Vasut */ +/* + * DA7212 Codec settings + * + * for Playback + * > amixer set "Headphone" 40% + * > amixer set "Headphone" on + * > amixer set "Mixout Left DAC Left" on + * > amixer set "Mixout Right DAC Right" on + * > aplay xxx.wav + * + * for Capture (Aux/Mic) + * + * on/off (B) + * CONN3 (HeadSet) ---+----> MSIOF1 + * | + * CONN4 AUX ---------+ on/off (A) + * + * > amixer set "Mixin PGA" on + * > amixer set "Mixin PGA" 50% + * > amixer set "ADC" on + * > amixer set "ADC" 80% + * > amixer set "Aux" on ^ + * > amixer set "Aux" 80% | (A) + * > amixer set "Mixin Left Aux Left" on | + * > amixer set "Mixin Right Aux Right" on v + * > amixer set "Mic 1" on ^ + * > amixer set "Mic 1" 80% | (B) + * > amixer set "Mixin Left Mic 1" on | + * > amixer set "Mixin Right Mic 1" on v + * > arecord -f cd xxx.wav + */ /dts-v1/; #include @@ -133,6 +164,12 @@ sn65dsi86_refclk: clk-x9 { clock-frequency = <38400000>; }; + /* Page 30 / Audio_Codec */ + sound_card: sound { + compatible = "audio-graph-card2"; + links = <&msiof1_snd>; + }; + /* Page 17 uSD-Slot */ vcc_sdhi: regulator-vcc-sdhi { compatible = "regulator-gpio"; @@ -145,6 +182,10 @@ vcc_sdhi: regulator-vcc-sdhi { }; }; +&audio_clkin { + clock-frequency = <24576000>; +}; + /* Page 22 / Ether_AVB0 */ &avb0 { pinctrl-0 = <&avb0_pins>; @@ -334,6 +375,29 @@ i2c0_mux1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; + + /* Page 30 / Audio_Codec */ + codec@1a { + compatible = "dlg,da7212"; + + #sound-dai-cells = <0>; + reg = <0x1a>; + + clocks = <&rcar_sound>; + clock-names = "mclk"; + + VDDA-supply = <®_1p8v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + port { + da7212_endpoint: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&msiof1_snd_endpoint>; + }; + }; + }; }; i2c0_mux2: i2c@2 { @@ -404,6 +468,23 @@ &mmc0 { status = "okay"; }; +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* ignore DT warning */ + /delete-property/#address-cells; + /delete-property/#size-cells; + + msiof1_snd: port { + msiof1_snd_endpoint: endpoint { + remote-endpoint = <&da7212_endpoint>; + }; + }; +}; + /* Page 26 / 2230 Key M M.2 */ &pcie0_clkref { clock-frequency = <100000000>; @@ -584,6 +665,31 @@ sd_uhs_pins: sd-uhs { function = "mmc"; power-source = <1800>; }; + + /* Page 30 / Audio_Codec */ + msiof1_pins: sound { + groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd"; + function = "msiof1"; + }; + + /* Page 30 / Audio_Codec */ + sound_clk_pins: sound-clk { + groups = "audio_clkin", "audio_clkout"; + function = "audio_clk"; + }; +}; + +/* Page 30 / Audio_Codec */ +&rcar_sound { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + /* It is used for ADG output as DA7212_MCLK */ + + /* audio_clkout */ + clock-frequency = <12288000>; /* 48 kHz groups */ + + status = "okay"; }; /* Page 31 / FAN */ From 672eebe1cf665a277a8e18b00aa1ffafbef57768 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 24 Apr 2025 06:40:44 +0100 Subject: [PATCH 06/14] arm64: dts: renesas: r9a07g044: Add GPT support Add GPT support by adding pwm node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424054050.28310-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 115 +++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6b1c77cd8261..ecaa9c4f305c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -244,6 +244,121 @@ mtu3: timer@10001200 { status = "disabled"; }; + gpt: pwm@10048000 { + compatible = "renesas,r9a07g044-gpt", + "renesas,rzg2l-gpt"; + reg = <0 0x10048000 0 0x800>; + #pwm-cells = <3>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", + "cmpe0", "cmpf0", "adtrga0", "adtrgb0", + "ovf0", "unf0", + "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", + "cmpe1", "cmpf1", "adtrga1", "adtrgb1", + "ovf1", "unf1", + "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", + "cmpe2", "cmpf2", "adtrga2", "adtrgb2", + "ovf2", "unf2", + "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", + "cmpe3", "cmpf3", "adtrga3", "adtrgb3", + "ovf3", "unf3", + "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", + "cmpe4", "cmpf4", "adtrga4", "adtrgb4", + "ovf4", "unf4", + "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", + "cmpe5", "cmpf5", "adtrga5", "adtrgb5", + "ovf5", "unf5", + "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", + "cmpe6", "cmpf6", "adtrga6", "adtrgb6", + "ovf6", "unf6", + "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", + "cmpe7", "cmpf7", "adtrga7", "adtrgb7", + "ovf7", "unf7"; + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; + resets = <&cpg R9A07G044_GPT_RST_C>; + power-domains = <&cpg>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g044-ssi", "renesas,rz-ssi"; From f2aa064b21e89a06908557b6aa72f493a2b33915 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 24 Apr 2025 06:40:45 +0100 Subject: [PATCH 07/14] arm64: dts: renesas: r9a07g054: Add GPT support Add GPT support by adding pwm node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424054050.28310-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 115 +++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 01f59914dd09..669eca74da0a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -244,6 +244,121 @@ mtu3: timer@10001200 { status = "disabled"; }; + gpt: pwm@10048000 { + compatible = "renesas,r9a07g054-gpt", + "renesas,rzg2l-gpt"; + reg = <0 0x10048000 0 0x800>; + #pwm-cells = <3>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", + "cmpe0", "cmpf0", "adtrga0", "adtrgb0", + "ovf0", "unf0", + "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", + "cmpe1", "cmpf1", "adtrga1", "adtrgb1", + "ovf1", "unf1", + "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", + "cmpe2", "cmpf2", "adtrga2", "adtrgb2", + "ovf2", "unf2", + "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", + "cmpe3", "cmpf3", "adtrga3", "adtrgb3", + "ovf3", "unf3", + "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", + "cmpe4", "cmpf4", "adtrga4", "adtrgb4", + "ovf4", "unf4", + "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", + "cmpe5", "cmpf5", "adtrga5", "adtrgb5", + "ovf5", "unf5", + "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", + "cmpe6", "cmpf6", "adtrga6", "adtrgb6", + "ovf6", "unf6", + "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", + "cmpe7", "cmpf7", "adtrga7", "adtrgb7", + "ovf7", "unf7"; + clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>; + resets = <&cpg R9A07G054_GPT_RST_C>; + power-domains = <&cpg>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g054-ssi", "renesas,rz-ssi"; From e00ad79244eff5181a117214f2b54b478df9b3d7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 24 Apr 2025 06:40:46 +0100 Subject: [PATCH 08/14] arm64: dts: renesas: rzg2l-smarc: Enable GPT on carrier board The GPT4 IOs are available on the carrier board's PMOD0 connector (J1). Enable the GPT on the carrier board by adding the GPT pinmux and node on the carrier board dtsi file. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424054050.28310-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +++++++ arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 5 +++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 8 ++++++++ 4 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 568d49cfe44a..b36749f94ccb 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -27,6 +27,13 @@ #error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" #endif +/* + * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the + * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1" + * below. + */ +#define PMOD0_GPT 0 + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index b3e6016880dd..43c456ffa63c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -26,6 +26,13 @@ #error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" #endif +/* + * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the + * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1" + * below. + */ +#define PMOD0_GPT 0 + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index e9f244c33d55..2616dbde4dd5 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -38,6 +38,11 @@ can1-stb-hog { line-name = "can1_stb"; }; + gpt_pins: gpt { + pinmux = , /* GTIOC4A */ + ; /* GTIOC4B */ + }; + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 789f7b0b5ebc..b76b55e7f09d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -104,6 +104,14 @@ codec_endpoint: endpoint { }; }; +#if PMOD0_GPT +&gpt { + pinctrl-0 = <&gpt_pins>; + pinctrl-names = "default"; + status = "okay"; +}; +#endif /* PMOD0_GPT */ + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; From a510da373ab48608bb7d88b96433898a50afed9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 10:47:48 +0200 Subject: [PATCH 09/14] arm64: dts: renesas: beacon-renesom: Align wifi node name with bindings Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: r8a774a1-beacon-rzg2m-kit.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424084748.105255-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 1489bc8d2f4e..d40a7224f9c3 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -300,7 +300,7 @@ &sdhi2 { #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupts-extended = <&gpio1 27 IRQ_TYPE_LEVEL_LOW>; From 0d2da0943f289f3264bb10f39cd44241949c0a23 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 24 Apr 2025 12:27:30 +0200 Subject: [PATCH 10/14] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe 9-pin D-sub serial port A simple CTS/RTS capable UART on a good old D-sub connector. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424102805.22803-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index 7f721720f647..b3de325fb47f 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -147,6 +147,14 @@ pins_sdio1_clk: pins-sdio1-clk { pinmux = ; drive-strength = <12>; }; + + pins_uart2: pins-uart2 { + pinmux = , + , + , + ; + bias-disable; + }; }; &sdio1 { @@ -223,3 +231,10 @@ &switch_port3 { phy-handle = <&switch0phy1>; status = "okay"; }; + +&uart2 { + pinctrl-0 = <&pins_uart2>; + pinctrl-names = "default"; + status = "okay"; + uart-has-rtscts; +}; From 218a67626bf497f77d285ed180199ea6791d5537 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 25 Apr 2025 12:01:31 +0200 Subject: [PATCH 11/14] ARM: dts: renesas: r9a06g032-rzn1d400-db: Enable USB device port Can be used via the microUSB connector CN9. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250425100129.11942-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 322e4c95ad3d..328cb35547d7 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -282,6 +282,10 @@ &uart0 { status = "okay"; }; +&udc { + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From 8ffec7d62c6956199f442dac3b2d5d02231c3977 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 7 May 2025 15:31:55 +0200 Subject: [PATCH 12/14] arm64: dts: renesas: white-hawk-single: Improve Ethernet TSN description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add the missing "ethernet3" alias for the Ethernet TSN port, so U-Boot will fill its local-mac-address property based on the "eth3addr" environment variable (if set), avoiding a random MAC address being assigned by the OS, - Rename the numerical Ethernet PHY label to "tsn0_phy", to avoid future conflicts, and for consistency with the "avbN_phy" labels. Fixes: 3d8e475bd7a724a9 ("arm64: dts: renesas: white-hawk-single: Wire-up Ethernet TSN") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/367f10a18aa196ff1c96734dd9bd5634b312c421.1746624368.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/white-hawk-single.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi index 20e8232f2f32..976a3ab44e5a 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi @@ -11,6 +11,10 @@ / { model = "Renesas White Hawk Single board"; compatible = "renesas,white-hawk-single"; + + aliases { + ethernet3 = &tsn0; + }; }; &hscif0 { @@ -53,7 +57,7 @@ &tsn0 { pinctrl-0 = <&tsn0_pins>; pinctrl-names = "default"; phy-mode = "rgmii"; - phy-handle = <&phy3>; + phy-handle = <&tsn0_phy>; status = "okay"; mdio { @@ -63,7 +67,7 @@ mdio { reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; reset-post-delay-us = <4000>; - phy3: ethernet-phy@0 { + tsn0_phy: ethernet-phy@0 { compatible = "ethernet-phy-id002b.0980", "ethernet-phy-ieee802.3-c22"; reg = <0>; From abbf127283aceeda6c16d2243d6683e3dc3509d6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 8 May 2025 09:43:13 +0200 Subject: [PATCH 13/14] ARM: dts: renesas: r9a06g032-rzn1d400-db: Add pinmux for the CPLD The CPLD has no dedicated driver, so apply the pinmux settings with the pinmux driver instead. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250508074311.20343-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 328cb35547d7..2de047393652 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -170,6 +170,9 @@ &mii_conv5 { }; &pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pins_cpld>; + pins_can0: pins_can0 { pinmux = , /* CAN0_TXD */ ; /* CAN0_RXD */ @@ -182,6 +185,13 @@ pins_can1: pins_can1 { drive-strength = <6>; }; + pins_cpld: pins-cpld { + pinmux = , + , + , + ; + }; + pins_eth3: pins_eth3 { pinmux = , , From b280613d480aa170e51029d5582bb4b666982b7c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 8 May 2025 09:43:14 +0200 Subject: [PATCH 14/14] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable USB host port Can be used via the USB connector J20. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250508074311.20343-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index b3de325fb47f..97a339b30d76 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -76,6 +76,10 @@ &mii_conv3 { status = "okay"; }; +&pci_usb { + status = "okay"; +}; + &pinctrl { pins_eth0: pins-eth0 { pinmux = ,