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ARM development for 7.1-rc1
Several development updates for 7.1-rc1: - fix a race condition handling PG_dcache_clean - further cleanups for the fault handling, allowing RT to be enabled - fixing nzones validation in adfs filesystem driver - fix for module unwinding -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmnrfHEACgkQ9OeQG+St rGTtMA/+JmEQuVvtJ4ZJ+PhFYdI/VVPTpTwf4tP1dhlLEKaeX4vzlw09+mW/dYeM jH65rkQ3wcLC4gRH7ZI1SRMm6n0lAf0ROLjpwagd+4U+xnhLCmIHxo8FM2v3Rmyl 34WnCmWitiEtUN41t0EfbUBxDoX5pV42vpPkYIdnQtLkjObCcXsVFMhegBPCTfp2 UOozgH7yNlkFwWEOCEacNne22MmAheOU0R4Jb/OiFAaE3z4i/9+nFoHd7NCKpmDf hgWaOalg+jsclxn5kyE0KbraP7Uvx44eX8OeQk1rdvL+F9ItGFXtXKD7FUUj+71/ S5yHT3YrRYvAEM1GDKAieZhVWFxKPm5osnlJwrrrnfLWR7JvwrsU7SGS8FqSsqqf i/Ie5rY1hV9faXJikY8MDSzKC7gwdX0wtZ8JZanZtGwFlPvI17oaE4K3hbiD13Dk WIJpd7kfYEWG0SjWtyrW1E2plqy3lfVN4MZfjW2ID18uo0PwVtgE5GFf/HFGxugN WLV+/DhSkc40EUC4bVflWDLtnJYhsQYCJoHwZXVI8YpNK+tShia0BVCSj+Llv8Tv f33Ae7IARZad+ty2MsTW1oG0zcIjHI8A4OIoRfbRwf3z9Bs8S3o6chlTOi7YYV5y fbSxCg9AIYRcUZ0ACsnrIgrVd/YF57FD8AvJ/BHvTm7nVTeoLKY= =arB6 -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux Pull ARM updates from Russell King: - fix a race condition handling PG_dcache_clean - further cleanups for the fault handling, allowing RT to be enabled - fixing nzones validation in adfs filesystem driver - fix for module unwinding * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux: ARM: 9463/1: Allow to enable RT ARM: 9472/1: fix race condition on PG_dcache_clean in __sync_icache_dcache() ARM: 9471/1: module: fix unwind section relocation out of range error fs/adfs: validate nzones in adfs_validate_bblk() ARM: provide individual is_translation_fault() and is_permission_fault() ARM: move FSR fault status definitions before fsr_fs() ARM: use BIT() and GENMASK() for fault status register fields ARM: move is_permission_fault() and is_translation_fault() to fault.h ARM: move vmalloc() lazy-page table population ARM: ensure interrupts are enabled in __do_user_fault()
This commit is contained in:
Linus Torvalds
commit
129d6eb266
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@ -42,6 +42,7 @@ config ARM
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select ARCH_SUPPORTS_CFI
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select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
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select ARCH_SUPPORTS_PER_VMA_LOCK
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select ARCH_SUPPORTS_RT
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select ARCH_USE_BUILTIN_BSWAP
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select ARCH_USE_CMPXCHG_LOCKREF
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select ARCH_USE_MEMTEST
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@ -225,6 +225,18 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
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mod->arch.init.plt = s;
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else if (s->sh_type == SHT_SYMTAB)
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syms = (Elf32_Sym *)s->sh_addr;
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#if defined(CONFIG_ARM_UNWIND) && !defined(CONFIG_VMSPLIT_3G)
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else if (s->sh_type == ELF_SECTION_UNWIND ||
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(strncmp(".ARM.extab", secstrings + s->sh_name, 10) == 0)) {
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/*
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* To avoid the possible relocation out of range issue for
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* R_ARM_PREL31, mark unwind section .ARM.extab and .ARM.exidx as
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* executable so they will be allocated along with .text section to
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* meet +/-1GB range requirement of the R_ARM_PREL31 relocation
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*/
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s->sh_flags |= SHF_EXECINSTR;
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}
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#endif
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}
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if (!mod->arch.core.plt || !mod->arch.init.plt) {
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@ -115,32 +115,6 @@ static inline bool is_write_fault(unsigned int fsr)
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return (fsr & FSR_WRITE) && !(fsr & FSR_CM);
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}
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static inline bool is_translation_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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#ifdef CONFIG_ARM_LPAE
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if ((fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL)
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return true;
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#else
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if (fs == FS_L1_TRANS || fs == FS_L2_TRANS)
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return true;
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#endif
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return false;
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}
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static inline bool is_permission_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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#ifdef CONFIG_ARM_LPAE
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if ((fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL)
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return true;
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#else
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if (fs == FS_L1_PERM || fs == FS_L2_PERM)
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return true;
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#endif
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return false;
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}
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static void die_kernel_fault(const char *msg, struct mm_struct *mm,
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unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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@ -190,7 +164,8 @@ __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
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/*
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* Something tried to access memory that isn't in our memory map..
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* User mode accesses just cause a SIGSEGV
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* User mode accesses just cause a SIGSEGV. Ensure interrupts are enabled
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* for preempt RT.
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*/
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static void
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__do_user_fault(unsigned long addr, unsigned int fsr, unsigned int sig,
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@ -198,6 +173,8 @@ __do_user_fault(unsigned long addr, unsigned int fsr, unsigned int sig,
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{
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struct task_struct *tsk = current;
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local_irq_enable();
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#ifdef CONFIG_DEBUG_USER
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if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) ||
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((user_debug & UDBG_BUS) && (sig == SIGBUS))) {
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@ -258,6 +235,70 @@ static inline bool ttbr0_usermode_access_allowed(struct pt_regs *regs)
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}
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#endif
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/*
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* Handle a vmalloc fault, copying the non-leaf page table entries from
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* init_mm.pgd. Any kernel context can trigger this, so we must not sleep
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* or enable interrupts. Having two CPUs execute this for the same page is
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* no problem, we'll just copy the same data twice.
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*
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* Returns false on failure.
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*/
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static bool __kprobes __maybe_unused vmalloc_fault(unsigned long addr)
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{
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unsigned int index;
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pgd_t *pgd, *pgd_k;
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p4d_t *p4d, *p4d_k;
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pud_t *pud, *pud_k;
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pmd_t *pmd, *pmd_k;
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index = pgd_index(addr);
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pgd = cpu_get_pgd() + index;
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pgd_k = init_mm.pgd + index;
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p4d = p4d_offset(pgd, addr);
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p4d_k = p4d_offset(pgd_k, addr);
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if (p4d_none(*p4d_k))
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return false;
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if (!p4d_present(*p4d))
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set_p4d(p4d, *p4d_k);
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pud = pud_offset(p4d, addr);
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pud_k = pud_offset(p4d_k, addr);
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if (pud_none(*pud_k))
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return false;
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if (!pud_present(*pud))
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set_pud(pud, *pud_k);
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pmd = pmd_offset(pud, addr);
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pmd_k = pmd_offset(pud_k, addr);
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#ifdef CONFIG_ARM_LPAE
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/*
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* Only one hardware entry per PMD with LPAE.
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*/
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index = 0;
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#else
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/*
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* On ARM one Linux PGD entry contains two hardware entries (see page
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* tables layout in pgtable.h). We normally guarantee that we always
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* fill both L1 entries. But create_mapping() doesn't follow the rule.
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* It can create inidividual L1 entries, so here we have to call
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* pmd_none() check for the entry really corresponded to address, not
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* for the first of pair.
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*/
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index = (addr >> SECTION_SHIFT) & 1;
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#endif
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if (pmd_none(pmd_k[index]))
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return false;
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copy_pmd(pmd, pmd_k);
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return true;
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}
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static int __kprobes
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do_kernel_address_page_fault(struct mm_struct *mm, unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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@ -268,6 +309,7 @@ do_kernel_address_page_fault(struct mm_struct *mm, unsigned long addr,
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* should not be faulting in kernel space, which includes the
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* vector/khelper page. Handle the branch predictor hardening
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* while interrupts are still disabled, then send a SIGSEGV.
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* Note that __do_user_fault() will enable interrupts.
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*/
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harden_branch_predictor();
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__do_user_fault(addr, fsr, SIGSEGV, SEGV_MAPERR, regs);
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@ -492,10 +534,9 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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* directly to do_kernel_address_page_fault() to handle.
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*
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* Otherwise, we're probably faulting in the vmalloc() area, so try to fix
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* that up. Note that we must not take any locks or enable interrupts in
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* this case.
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* that up via vmalloc_fault().
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*
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* If vmalloc() fixup fails, that means the non-leaf page tables did not
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* If vmalloc_fault() fails, that means the non-leaf page tables did not
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* contain an entry for this address, so handle this via
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* do_kernel_address_page_fault().
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*/
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@ -504,65 +545,12 @@ static int __kprobes
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do_translation_fault(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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unsigned int index;
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pgd_t *pgd, *pgd_k;
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p4d_t *p4d, *p4d_k;
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pud_t *pud, *pud_k;
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pmd_t *pmd, *pmd_k;
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if (addr < TASK_SIZE)
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return do_page_fault(addr, fsr, regs);
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if (user_mode(regs))
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goto bad_area;
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index = pgd_index(addr);
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pgd = cpu_get_pgd() + index;
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pgd_k = init_mm.pgd + index;
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p4d = p4d_offset(pgd, addr);
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p4d_k = p4d_offset(pgd_k, addr);
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if (p4d_none(*p4d_k))
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goto bad_area;
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if (!p4d_present(*p4d))
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set_p4d(p4d, *p4d_k);
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pud = pud_offset(p4d, addr);
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pud_k = pud_offset(p4d_k, addr);
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if (pud_none(*pud_k))
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goto bad_area;
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if (!pud_present(*pud))
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set_pud(pud, *pud_k);
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pmd = pmd_offset(pud, addr);
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pmd_k = pmd_offset(pud_k, addr);
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#ifdef CONFIG_ARM_LPAE
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/*
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* Only one hardware entry per PMD with LPAE.
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*/
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index = 0;
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#else
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/*
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* On ARM one Linux PGD entry contains two hardware entries (see page
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* tables layout in pgtable.h). We normally guarantee that we always
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* fill both L1 entries. But create_mapping() doesn't follow the rule.
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* It can create inidividual L1 entries, so here we have to call
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* pmd_none() check for the entry really corresponded to address, not
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* for the first of pair.
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*/
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index = (addr >> SECTION_SHIFT) & 1;
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#endif
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if (pmd_none(pmd_k[index]))
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goto bad_area;
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copy_pmd(pmd, pmd_k);
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if (!user_mode(regs) && vmalloc_fault(addr))
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return 0;
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bad_area:
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do_kernel_address_page_fault(current->mm, addr, fsr, regs);
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return 0;
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@ -5,12 +5,9 @@
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/*
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* Fault status register encodings. We steal bit 31 for our own purposes.
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*/
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#define FSR_LNX_PF (1 << 31)
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#define FSR_CM (1 << 13)
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#define FSR_WRITE (1 << 11)
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#define FSR_FS4 (1 << 10)
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#define FSR_FS3_0 (15)
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#define FSR_FS5_0 (0x3f)
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#define FSR_LNX_PF BIT(31)
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#define FSR_CM BIT(13)
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#define FSR_WRITE BIT(11)
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#ifdef CONFIG_ARM_LPAE
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#define FSR_FS_AEA 17
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@ -18,10 +15,26 @@
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#define FS_PERM_NOLL 0xC
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#define FS_MMU_NOLL_MASK 0x3C
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#define FSR_FS5_0 GENMASK(5, 0)
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static inline int fsr_fs(unsigned int fsr)
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{
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return fsr & FSR_FS5_0;
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}
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static inline bool is_translation_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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return (fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL;
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}
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static inline bool is_permission_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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return (fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL;
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}
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#else
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#define FSR_FS_AEA 22
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#define FS_L1_TRANS 0x5
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@ -29,10 +42,27 @@ static inline int fsr_fs(unsigned int fsr)
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#define FS_L1_PERM 0xD
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#define FS_L2_PERM 0xF
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#define FSR_FS4 BIT(10)
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#define FSR_FS3_0 GENMASK(3, 0)
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static inline int fsr_fs(unsigned int fsr)
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{
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return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
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}
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static inline bool is_translation_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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return fs == FS_L1_TRANS || fs == FS_L2_TRANS;
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}
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static inline bool is_permission_fault(unsigned int fsr)
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{
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int fs = fsr_fs(fsr);
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return fs == FS_L1_PERM || fs == FS_L2_PERM;
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}
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#endif
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void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
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@ -304,8 +304,10 @@ void __sync_icache_dcache(pte_t pteval)
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else
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mapping = NULL;
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if (!test_and_set_bit(PG_dcache_clean, &folio->flags.f))
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if (!test_bit(PG_dcache_clean, &folio->flags.f)) {
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__flush_dcache_folio(mapping, folio);
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set_bit(PG_dcache_clean, &folio->flags.f);
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}
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if (pte_exec(pteval))
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__flush_icache_all();
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@ -317,6 +317,9 @@ static int adfs_validate_bblk(struct super_block *sb, struct buffer_head *bh,
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if (adfs_checkdiscrecord(dr))
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return -EILSEQ;
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if ((dr->nzones | dr->nzones_high << 8) == 0)
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return -EILSEQ;
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*drp = dr;
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return 0;
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}
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