From 59e4f3b45b96a24fc9b7a89e5f8a2168b30f95af Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 12:17:00 +0000 Subject: [PATCH 01/10] ARM: ensure interrupts are enabled in __do_user_fault() __do_user_fault() may be called from fault handling paths where the interrupts are enabled or disabled. E.g. do_page_fault() calls this with interrupts enabled, whereas do_sect_fault()->do_bad_area() will call this with interrupts disabled. Since this is a userspace fault, we know that interrupts were enabled in the parent context, so call local_irq_enable() here to give a consistent interrupt state. This is necessary for force_sig_info() when PREEMPT_RT is enabled. Reported-by: Yadi.hu Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index ed4330cc3f4e..6c27ebd49093 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -190,7 +190,8 @@ __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr, /* * Something tried to access memory that isn't in our memory map.. - * User mode accesses just cause a SIGSEGV + * User mode accesses just cause a SIGSEGV. Ensure interrupts are enabled + * for preempt RT. */ static void __do_user_fault(unsigned long addr, unsigned int fsr, unsigned int sig, @@ -198,6 +199,8 @@ __do_user_fault(unsigned long addr, unsigned int fsr, unsigned int sig, { struct task_struct *tsk = current; + local_irq_enable(); + #ifdef CONFIG_DEBUG_USER if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) || ((user_debug & UDBG_BUS) && (sig == SIGBUS))) { @@ -268,6 +271,7 @@ do_kernel_address_page_fault(struct mm_struct *mm, unsigned long addr, * should not be faulting in kernel space, which includes the * vector/khelper page. Handle the branch predictor hardening * while interrupts are still disabled, then send a SIGSEGV. + * Note that __do_user_fault() will enable interrupts. */ harden_branch_predictor(); __do_user_fault(addr, fsr, SIGSEGV, SEGV_MAPERR, regs); From 78900204851708bbe761c3acf641ad60f15c922f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 12:39:42 +0000 Subject: [PATCH 02/10] ARM: move vmalloc() lazy-page table population Split the vmalloc() lazy-page table population from do_translation_fault() into a new vmalloc_fault() function. Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.c | 126 ++++++++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 58 deletions(-) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 6c27ebd49093..0f3b6cc516c1 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -261,6 +261,70 @@ static inline bool ttbr0_usermode_access_allowed(struct pt_regs *regs) } #endif +/* + * Handle a vmalloc fault, copying the non-leaf page table entries from + * init_mm.pgd. Any kernel context can trigger this, so we must not sleep + * or enable interrupts. Having two CPUs execute this for the same page is + * no problem, we'll just copy the same data twice. + * + * Returns false on failure. + */ +static bool __kprobes __maybe_unused vmalloc_fault(unsigned long addr) +{ + unsigned int index; + pgd_t *pgd, *pgd_k; + p4d_t *p4d, *p4d_k; + pud_t *pud, *pud_k; + pmd_t *pmd, *pmd_k; + + index = pgd_index(addr); + + pgd = cpu_get_pgd() + index; + pgd_k = init_mm.pgd + index; + + p4d = p4d_offset(pgd, addr); + p4d_k = p4d_offset(pgd_k, addr); + + if (p4d_none(*p4d_k)) + return false; + if (!p4d_present(*p4d)) + set_p4d(p4d, *p4d_k); + + pud = pud_offset(p4d, addr); + pud_k = pud_offset(p4d_k, addr); + + if (pud_none(*pud_k)) + return false; + if (!pud_present(*pud)) + set_pud(pud, *pud_k); + + pmd = pmd_offset(pud, addr); + pmd_k = pmd_offset(pud_k, addr); + +#ifdef CONFIG_ARM_LPAE + /* + * Only one hardware entry per PMD with LPAE. + */ + index = 0; +#else + /* + * On ARM one Linux PGD entry contains two hardware entries (see page + * tables layout in pgtable.h). We normally guarantee that we always + * fill both L1 entries. But create_mapping() doesn't follow the rule. + * It can create inidividual L1 entries, so here we have to call + * pmd_none() check for the entry really corresponded to address, not + * for the first of pair. + */ + index = (addr >> SECTION_SHIFT) & 1; +#endif + if (pmd_none(pmd_k[index])) + return false; + + copy_pmd(pmd, pmd_k); + + return true; +} + static int __kprobes do_kernel_address_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -496,10 +560,9 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) * directly to do_kernel_address_page_fault() to handle. * * Otherwise, we're probably faulting in the vmalloc() area, so try to fix - * that up. Note that we must not take any locks or enable interrupts in - * this case. + * that up via vmalloc_fault(). * - * If vmalloc() fixup fails, that means the non-leaf page tables did not + * If vmalloc_fault() fails, that means the non-leaf page tables did not * contain an entry for this address, so handle this via * do_kernel_address_page_fault(). */ @@ -508,65 +571,12 @@ static int __kprobes do_translation_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { - unsigned int index; - pgd_t *pgd, *pgd_k; - p4d_t *p4d, *p4d_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - if (addr < TASK_SIZE) return do_page_fault(addr, fsr, regs); - if (user_mode(regs)) - goto bad_area; + if (!user_mode(regs) && vmalloc_fault(addr)) + return 0; - index = pgd_index(addr); - - pgd = cpu_get_pgd() + index; - pgd_k = init_mm.pgd + index; - - p4d = p4d_offset(pgd, addr); - p4d_k = p4d_offset(pgd_k, addr); - - if (p4d_none(*p4d_k)) - goto bad_area; - if (!p4d_present(*p4d)) - set_p4d(p4d, *p4d_k); - - pud = pud_offset(p4d, addr); - pud_k = pud_offset(p4d_k, addr); - - if (pud_none(*pud_k)) - goto bad_area; - if (!pud_present(*pud)) - set_pud(pud, *pud_k); - - pmd = pmd_offset(pud, addr); - pmd_k = pmd_offset(pud_k, addr); - -#ifdef CONFIG_ARM_LPAE - /* - * Only one hardware entry per PMD with LPAE. - */ - index = 0; -#else - /* - * On ARM one Linux PGD entry contains two hardware entries (see page - * tables layout in pgtable.h). We normally guarantee that we always - * fill both L1 entries. But create_mapping() doesn't follow the rule. - * It can create inidividual L1 entries, so here we have to call - * pmd_none() check for the entry really corresponded to address, not - * for the first of pair. - */ - index = (addr >> SECTION_SHIFT) & 1; -#endif - if (pmd_none(pmd_k[index])) - goto bad_area; - - copy_pmd(pmd, pmd_k); - return 0; - -bad_area: do_kernel_address_page_fault(current->mm, addr, fsr, regs); return 0; From 9c46fcaf2efa78e814e102c5828cf5c825a133ec Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 15:25:24 +0000 Subject: [PATCH 03/10] ARM: move is_permission_fault() and is_translation_fault() to fault.h is_permission_fault() and is_translation_fault() are both conditional on the FSR encodings, which are dependent on LPAE. We define the constants in fault.h. Move these inline functions to fault.h to be near the FSR definitions. Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.c | 26 -------------------------- arch/arm/mm/fault.h | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 0f3b6cc516c1..e62cc4be5adf 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -115,32 +115,6 @@ static inline bool is_write_fault(unsigned int fsr) return (fsr & FSR_WRITE) && !(fsr & FSR_CM); } -static inline bool is_translation_fault(unsigned int fsr) -{ - int fs = fsr_fs(fsr); -#ifdef CONFIG_ARM_LPAE - if ((fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL) - return true; -#else - if (fs == FS_L1_TRANS || fs == FS_L2_TRANS) - return true; -#endif - return false; -} - -static inline bool is_permission_fault(unsigned int fsr) -{ - int fs = fsr_fs(fsr); -#ifdef CONFIG_ARM_LPAE - if ((fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL) - return true; -#else - if (fs == FS_L1_PERM || fs == FS_L2_PERM) - return true; -#endif - return false; -} - static void die_kernel_fault(const char *msg, struct mm_struct *mm, unsigned long addr, unsigned int fsr, struct pt_regs *regs) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index e8f8c1902544..e95f44757dc9 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -35,6 +35,32 @@ static inline int fsr_fs(unsigned int fsr) } #endif +static inline bool is_translation_fault(unsigned int fsr) +{ + int fs = fsr_fs(fsr); +#ifdef CONFIG_ARM_LPAE + if ((fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL) + return true; +#else + if (fs == FS_L1_TRANS || fs == FS_L2_TRANS) + return true; +#endif + return false; +} + +static inline bool is_permission_fault(unsigned int fsr) +{ + int fs = fsr_fs(fsr); +#ifdef CONFIG_ARM_LPAE + if ((fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL) + return true; +#else + if (fs == FS_L1_PERM || fs == FS_L2_PERM) + return true; +#endif + return false; +} + void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs); void early_abt_enable(void); asmlinkage void do_DataAbort(unsigned long addr, unsigned int fsr, From 5548e8a4663d9decc8215c53e4a41c704f183cbb Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 15:34:42 +0000 Subject: [PATCH 04/10] ARM: use BIT() and GENMASK() for fault status register fields Modernise the fault status field definitions by using BIT() and GENMASK(). Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index e95f44757dc9..d2bdedaefe14 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -5,12 +5,12 @@ /* * Fault status register encodings. We steal bit 31 for our own purposes. */ -#define FSR_LNX_PF (1 << 31) -#define FSR_CM (1 << 13) -#define FSR_WRITE (1 << 11) -#define FSR_FS4 (1 << 10) -#define FSR_FS3_0 (15) -#define FSR_FS5_0 (0x3f) +#define FSR_LNX_PF BIT(31) +#define FSR_CM BIT(13) +#define FSR_WRITE BIT(11) +#define FSR_FS4 BIT(10) +#define FSR_FS3_0 GENMASK(3, 0) +#define FSR_FS5_0 GENMASK(5, 0) #ifdef CONFIG_ARM_LPAE #define FSR_FS_AEA 17 From a542de4451093f310d20e3d65d62ab4f4d38241f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 15:36:09 +0000 Subject: [PATCH 05/10] ARM: move FSR fault status definitions before fsr_fs() The FSR's fault status bits depend on whether LPAE is enabled. Rather than always exposing both LPAE and non-LPAE to all code, move them inside the ifdef blocks dependent on LPAE to restrict their visibility. No code other than fsr_fs() makes use of these. Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index d2bdedaefe14..44c0fad29cce 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -8,9 +8,6 @@ #define FSR_LNX_PF BIT(31) #define FSR_CM BIT(13) #define FSR_WRITE BIT(11) -#define FSR_FS4 BIT(10) -#define FSR_FS3_0 GENMASK(3, 0) -#define FSR_FS5_0 GENMASK(5, 0) #ifdef CONFIG_ARM_LPAE #define FSR_FS_AEA 17 @@ -18,6 +15,8 @@ #define FS_PERM_NOLL 0xC #define FS_MMU_NOLL_MASK 0x3C +#define FSR_FS5_0 GENMASK(5, 0) + static inline int fsr_fs(unsigned int fsr) { return fsr & FSR_FS5_0; @@ -29,6 +28,9 @@ static inline int fsr_fs(unsigned int fsr) #define FS_L1_PERM 0xD #define FS_L2_PERM 0xF +#define FSR_FS4 BIT(10) +#define FSR_FS3_0 GENMASK(3, 0) + static inline int fsr_fs(unsigned int fsr) { return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6; From d1fed2d600905e7f007d8c88c936b768d45c09d6 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Fri, 5 Dec 2025 16:26:04 +0000 Subject: [PATCH 06/10] ARM: provide individual is_translation_fault() and is_permission_fault() Provide individual LPAE and non-LPAE definitions for both these functions, rather than having ifdefs inside the function body. This places the functions closer to their associated definitions. Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.h | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index 44c0fad29cce..207f1b06941d 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -21,6 +21,20 @@ static inline int fsr_fs(unsigned int fsr) { return fsr & FSR_FS5_0; } + +static inline bool is_translation_fault(unsigned int fsr) +{ + int fs = fsr_fs(fsr); + + return (fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL; +} + +static inline bool is_permission_fault(unsigned int fsr) +{ + int fs = fsr_fs(fsr); + + return (fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL; +} #else #define FSR_FS_AEA 22 #define FS_L1_TRANS 0x5 @@ -35,33 +49,21 @@ static inline int fsr_fs(unsigned int fsr) { return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6; } -#endif static inline bool is_translation_fault(unsigned int fsr) { int fs = fsr_fs(fsr); -#ifdef CONFIG_ARM_LPAE - if ((fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL) - return true; -#else - if (fs == FS_L1_TRANS || fs == FS_L2_TRANS) - return true; -#endif - return false; + + return fs == FS_L1_TRANS || fs == FS_L2_TRANS; } static inline bool is_permission_fault(unsigned int fsr) { int fs = fsr_fs(fsr); -#ifdef CONFIG_ARM_LPAE - if ((fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL) - return true; -#else - if (fs == FS_L1_PERM || fs == FS_L2_PERM) - return true; -#endif - return false; + + return fs == FS_L1_PERM || fs == FS_L2_PERM; } +#endif void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs); void early_abt_enable(void); From dd9d3e16c2d5fa166e13dce07413be51f42c8f5d Mon Sep 17 00:00:00 2001 From: Bae Yeonju Date: Sat, 21 Mar 2026 13:45:02 +0900 Subject: [PATCH 07/10] fs/adfs: validate nzones in adfs_validate_bblk() Reject ADFS disc records with a zero zone count during boot block validation, before the disc record is used. When nzones is 0, adfs_read_map() passes it to kmalloc_array(0, ...) which returns ZERO_SIZE_PTR, and adfs_map_layout() then writes to dm[-1], causing an out-of-bounds write before the allocated buffer. adfs_validate_dr0() already rejects nzones != 1 for old-format images. Add the equivalent check to adfs_validate_bblk() for new-format images so that a crafted image with nzones == 0 is rejected at probe time. Found by syzkaller. Fixes: f6f14a0d71b0 ("fs/adfs: map: move map-specific sb initialisation to map.c") Signed-off-by: Bae Yeonju Signed-off-by: Russell King (Oracle) --- fs/adfs/super.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/adfs/super.c b/fs/adfs/super.c index 2c5b2076acf9..a4cd0a5159dd 100644 --- a/fs/adfs/super.c +++ b/fs/adfs/super.c @@ -317,6 +317,9 @@ static int adfs_validate_bblk(struct super_block *sb, struct buffer_head *bh, if (adfs_checkdiscrecord(dr)) return -EILSEQ; + if ((dr->nzones | dr->nzones_high << 8) == 0) + return -EILSEQ; + *drp = dr; return 0; } From 5a21253b3073df578ee074da2f9427cbb4c3146a Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 2 Apr 2026 02:43:25 +0100 Subject: [PATCH 08/10] ARM: 9471/1: module: fix unwind section relocation out of range error In an armv7 system that uses non-3G/1G split and with more than 512MB physical memory, driver load may fail with following error: section 29 reloc 0 sym '': relocation 42 out of range (0xc2ab9be8 -> 0x7fad5998) This happens when relocation R_ARM_PREL31 from the unwind section .ARM.extab and .ARM.exidx are allocated from the VMALLOC space while .text section is from MODULES_VADDR space. It exceeds the +/-1GB relocation requirement of R_ARM_PREL31 hence triggers the error. The fix is to mark .ARM.extab and .ARM.exidx sections as executable so they can be allocated along with .text section and always meet range requirement. Co-developed-by: Ard Biesheuvel Signed-off-by: Ard Biesheuvel Signed-off-by: William Zhang Signed-off-by: Russell King (Oracle) --- arch/arm/kernel/module-plts.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/kernel/module-plts.c b/arch/arm/kernel/module-plts.c index 354ce16d83cb..b5338fe59706 100644 --- a/arch/arm/kernel/module-plts.c +++ b/arch/arm/kernel/module-plts.c @@ -225,6 +225,18 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, mod->arch.init.plt = s; else if (s->sh_type == SHT_SYMTAB) syms = (Elf32_Sym *)s->sh_addr; +#if defined(CONFIG_ARM_UNWIND) && !defined(CONFIG_VMSPLIT_3G) + else if (s->sh_type == ELF_SECTION_UNWIND || + (strncmp(".ARM.extab", secstrings + s->sh_name, 10) == 0)) { + /* + * To avoid the possible relocation out of range issue for + * R_ARM_PREL31, mark unwind section .ARM.extab and .ARM.exidx as + * executable so they will be allocated along with .text section to + * meet +/-1GB range requirement of the R_ARM_PREL31 relocation + */ + s->sh_flags |= SHF_EXECINSTR; + } +#endif } if (!mod->arch.core.plt || !mod->arch.init.plt) { From 75f9a484e817adea211c73f89ed938a2b2f90953 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Wed, 15 Apr 2026 18:12:48 +0100 Subject: [PATCH 09/10] ARM: 9472/1: fix race condition on PG_dcache_clean in __sync_icache_dcache() This bug was already discovered and fixed for arm64 in commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()"). Verified with added instrumentation to track dcache flushes in a ring buffer, as shown by the (distilled) output: kernel: SIGILL at b6b80ac0 cpu 1 pid 32663 linux_pte=8eff659f hw_pte=8eff6e7e young=1 exec=1 kernel: dcache flush START cpu0 pfn=8eff6 ts=48629557020154 kernel: dcache flush SKIPPED cpu1 pfn=8eff6 ts=48629557020154 kernel: dcache flush FINISH cpu0 pfn=8eff6 ts=48629557036154 audisp-syslog: comm="journalctl" exe="/usr/bin/journalctl" sig=4 [...] Discussions in the mailing list mentioned that arch/arm is also affected but the fix was never applied to it [1][2]. Apply the change now, since the race condition can cause sporadic SIGILL's and SEGV's especially while under high memory pressure. Link: https://lore.kernel.org/all/adzMOdySgMIePcue@willie-the-truck [1] Link: https://lore.kernel.org/all/20210514095001.13236-1-catalin.marinas@arm.com [2] Signed-off-by: Brian Ruley Reviewed-by: Will Deacon Cc: Fixes: 6012191aa9c6 ("ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches") Signed-off-by: Will Deacon Signed-off-by: Russell King (Oracle) --- arch/arm/mm/flush.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 19470d938b23..4d7ef5cc36b6 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -304,8 +304,10 @@ void __sync_icache_dcache(pte_t pteval) else mapping = NULL; - if (!test_and_set_bit(PG_dcache_clean, &folio->flags.f)) + if (!test_bit(PG_dcache_clean, &folio->flags.f)) { __flush_dcache_folio(mapping, folio); + set_bit(PG_dcache_clean, &folio->flags.f); + } if (pte_exec(pteval)) __flush_icache_all(); From c6e61c06d6061750597e79c598acb5dead44c35b Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Tue, 11 Nov 2025 16:54:38 +0100 Subject: [PATCH 10/10] ARM: 9463/1: Allow to enable RT All known issues have been adressed. Allow to select RT. Acked-by: Linus Walleij Reviewed-by: Arnd Bergmann Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Russell King (Oracle) --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ec33376f8e2b..71fc5dd4123f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -42,6 +42,7 @@ config ARM select ARCH_SUPPORTS_CFI select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE select ARCH_SUPPORTS_PER_VMA_LOCK + select ARCH_SUPPORTS_RT select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF select ARCH_USE_MEMTEST