mirror of
https://github.com/torvalds/linux.git
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4ee64205ff
of effort from Brian Masney. Now the only option is to use determine_rate(),
which is good because that takes a struct argument instead of just a couple
unsigned longs, allowing us to easily modify the way we determine and set rates
in the clk tree.
Beyond that core framework change we've got the typical pile of new SoC clk
driver additions, fixes for clk data and/or adding missing clks because the
consumer driver using those clks wasn't ready, etc. The usual suspects are all
here: Qualcomm, Samsung, Mediatek, and Rockchip along with some newcomers
making RISC-V SoCs like ESWIN's eic700 and Tenstorrent's Atlantis. The clk
driver side of this looks pretty normal.
Core:
- Remove the round_rate() clk op (yay!)
New Drivers:
- ESWIN eic700 SoC clk support
- Econet EN751221 SoC clock/reset support
- Global TCSR, RPMh, and display clock controller support for
the Qualcomm Eliza platform
- TCSR, the multiple global, and the RPMh clock controller
support for the Qualcomm Nord platform
- GPU clock controller support for Qualcomm SM8750
- Video and GPU clock controller support for Qualcomm Glymur
- Global clock controller support for Qualcomm IPQ5210
- Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
controllers on the SoC
- ExynosAutov920: Add G3D (GPU) clock controller
- Clock driver for the Rockchip RV1103B SoC
- Initial support for the Renesas RZ/G3L (R9A08G046) SoC
- Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC
-----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmnmb1QUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSUcUg/+PCWUrRlcgboA/xCl+qdfa7Pxd3X6
W6Z0IFwPrF6kZQnhlIIn3JlRcHixWilwNPgd02h5QK/2gA+Fa+T3h2+SE4oNW/qY
dZm2W8qDxRIB2+/okuUaDOp0crybtRKHkph9jW1YJo+EDLRhwAVE1SKbr/uyZiAk
1mr0lk8ZXbvhE/VoQysMjoZ8ITBEQiOwJEBNma6Oufl6dPEdSnaTKWkJZsUc3xjM
kFx666wNDVqwVobX2q3J6mb3/CyPEIpyFeOgAFVkRcVdPf53Xz7BijYkS2wtPclM
E58PKIjqk1TMt9nIdo5QuHZ5Og7nPFTQ9W1R0Qo/JGfjWnqqWTwCkEOXWWgTVD6x
F/gctH+X9JkQEsXid6P4HAdFqOm2UhoUJJ+yTcwXphaQXCctG/kYRW0dbxu8N/z6
hGpOKKeTmkioHIZoUW4Ap4L9futQWVmd45J9w6MGxF4QZL9apL2ILJ7jxhefxFH6
YDb8srZ50Mqco18TERxvxMhK5kKiyzz7uL927O9pofmRPwzSKlwIKgILhVKNJff2
TbCvOKi5oFpRizH/HmjVJ4SbKjWXrwbI6vTxy59FgKnAsmcwg1NQVBDu6Wo4ohtL
HVe94hPE55q8585D5f6xhfM0MTmE73prZxmb57FtXMJbHFDwYt50v4W95ToAOz4O
wN9cQVEL1vm6hx4=
=RdCb
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We've finally gotten rid of the struct clk_ops::round_rate() code
after months of effort from Brian Masney. Now the only option is to
use determine_rate(), which is good because that takes a struct
argument instead of just a couple unsigned longs, allowing us to
easily modify the way we determine and set rates in the clk tree.
Beyond that core framework change we've got the typical pile of new
SoC clk driver additions, fixes for clk data and/or adding missing
clks because the consumer driver using those clks wasn't ready, etc.
The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
pretty normal.
Core:
- Remove the round_rate() clk op (yay!)
New Drivers:
- ESWIN eic700 SoC clk support
- Econet EN751221 SoC clock/reset support
- Global TCSR, RPMh, and display clock controller support for the
Qualcomm Eliza platform
- TCSR, the multiple global, and the RPMh clock controller support
for the Qualcomm Nord platform
- GPU clock controller support for Qualcomm SM8750
- Video and GPU clock controller support for Qualcomm Glymur
- Global clock controller support for Qualcomm IPQ5210
- Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
controllers on the SoC
- ExynosAutov920: Add G3D (GPU) clock controller
- Clock driver for the Rockchip RV1103B SoC
- Initial support for the Renesas RZ/G3L (R9A08G046) SoC
- Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
clk: visconti: pll: initialize clk_init_data to zero
clk: fsl-sai: Add MCLK generation support
clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
clk: fsl-sai: Add i.MX8M support with 8 byte register offset
clk: fsl-sai: Sort the headers
dt-bindings: clock: fsl-sai: Document i.MX8M support
clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
clk: qcom: rpmh: Add support for Nord rpmh clocks
clk: qcom: Add TCSR clock driver for Nord SoC
dt-bindings: clock: qcom: Add Nord Global Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
clk: qcom: Constify list of critical CBCR registers
clk: qcom: Constify qcom_cc_driver_data
clk: qcom: videocc-glymur: Constify qcom_cc_desc
clk: qcom: Add a driver for SM8750 GPU clocks
dt-bindings: clock: qcom: Add SM8750 GPU clocks
clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
...
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|---|---|---|
| .. | ||
| actions,s500-reset.h | ||
| actions,s700-reset.h | ||
| actions,s900-reset.h | ||
| airoha,en7523-reset.h | ||
| airoha,en7581-reset.h | ||
| altr,rst-mgr-a10.h | ||
| altr,rst-mgr-a10sr.h | ||
| altr,rst-mgr-s10.h | ||
| altr,rst-mgr.h | ||
| amlogic,c3-reset.h | ||
| amlogic,meson-a1-audio-reset.h | ||
| amlogic,meson-a1-reset.h | ||
| amlogic,meson-axg-audio-arb.h | ||
| amlogic,meson-axg-reset.h | ||
| amlogic,meson-g12a-audio-reset.h | ||
| amlogic,meson-g12a-reset.h | ||
| amlogic,meson-gxbb-reset.h | ||
| amlogic,meson-s4-reset.h | ||
| amlogic,meson8b-clkc-reset.h | ||
| amlogic,meson8b-reset.h | ||
| aspeed,ast2700-scu.h | ||
| axg-aoclkc.h | ||
| bcm6328-reset.h | ||
| bcm6358-reset.h | ||
| bcm6362-reset.h | ||
| bcm6368-reset.h | ||
| bcm63268-reset.h | ||
| bitmain,bm1880-reset.h | ||
| bt1-ccu.h | ||
| canaan,k230-rst.h | ||
| cix,sky1-s5-system-control.h | ||
| cix,sky1-system-control.h | ||
| cortina,gemini-reset.h | ||
| delta,tn48m-reset.h | ||
| econet,en751221-scu.h | ||
| eswin,eic7700-reset.h | ||
| fsl,imx8ulp-sim-lpav.h | ||
| g12a-aoclkc.h | ||
| gxbb-aoclkc.h | ||
| hisi,hi6220-resets.h | ||
| imx7-reset.h | ||
| imx8mp-reset-audiomix.h | ||
| imx8mp-reset.h | ||
| imx8mq-reset.h | ||
| k210-rst.h | ||
| mediatek,mt6735-infracfg.h | ||
| mediatek,mt6735-mfgcfg.h | ||
| mediatek,mt6735-pericfg.h | ||
| mediatek,mt6735-vdecsys.h | ||
| mediatek,mt6735-wdt.h | ||
| mediatek,mt6795-resets.h | ||
| mediatek,mt7988-resets.h | ||
| mediatek,mt8196-resets.h | ||
| mt2701-resets.h | ||
| mt2712-resets.h | ||
| mt7621-reset.h | ||
| mt7622-reset.h | ||
| mt7629-resets.h | ||
| mt7986-resets.h | ||
| mt8135-resets.h | ||
| mt8173-resets.h | ||
| mt8183-resets.h | ||
| mt8186-resets.h | ||
| mt8188-resets.h | ||
| mt8192-resets.h | ||
| mt8195-resets.h | ||
| nuvoton,ma35d1-reset.h | ||
| nuvoton,npcm7xx-reset.h | ||
| nvidia,tegra114-car.h | ||
| nvidia,tegra264.h | ||
| pistachio-resets.h | ||
| qcom,gcc-apq8084.h | ||
| qcom,gcc-ipq806x.h | ||
| qcom,gcc-ipq5018.h | ||
| qcom,gcc-ipq6018.h | ||
| qcom,gcc-mdm9615.h | ||
| qcom,gcc-msm8660.h | ||
| qcom,gcc-msm8916.h | ||
| qcom,gcc-msm8939.h | ||
| qcom,gcc-msm8960.h | ||
| qcom,gcc-msm8974.h | ||
| qcom,ipq5210-gcc.h | ||
| qcom,ipq5424-gcc.h | ||
| qcom,ipq5424-nsscc.h | ||
| qcom,ipq9574-gcc.h | ||
| qcom,ipq9574-nsscc.h | ||
| qcom,mmcc-apq8084.h | ||
| qcom,mmcc-msm8960.h | ||
| qcom,mmcc-msm8974.h | ||
| qcom,qca8k-nsscc.h | ||
| qcom,sar2130p-gpucc.h | ||
| qcom,sdm845-aoss.h | ||
| qcom,sdm845-pdc.h | ||
| qcom,sm8350-videocc.h | ||
| qcom,sm8450-gpucc.h | ||
| qcom,sm8650-gpucc.h | ||
| qcom,x1e80100-gpucc.h | ||
| raspberrypi,firmware-reset.h | ||
| realtek,rtd1195.h | ||
| realtek,rtd1295.h | ||
| rockchip,rk3506-cru.h | ||
| rockchip,rk3528-cru.h | ||
| rockchip,rk3562-cru.h | ||
| rockchip,rk3576-cru.h | ||
| rockchip,rk3588-cru.h | ||
| rockchip,rv1126b-cru.h | ||
| sama7g5-reset.h | ||
| snps,hsdk-reset.h | ||
| sophgo,sg2042-reset.h | ||
| spacemit,k3-resets.h | ||
| st,stm32mp21-rcc.h | ||
| st,stm32mp25-rcc.h | ||
| starfive-jh7100.h | ||
| starfive,jh7110-crg.h | ||
| stericsson,db8500-prcc-reset.h | ||
| stih407-resets.h | ||
| stm32mp1-resets.h | ||
| stm32mp13-resets.h | ||
| sun4i-a10-ccu.h | ||
| sun5i-ccu.h | ||
| sun6i-a31-ccu.h | ||
| sun8i-a23-a33-ccu.h | ||
| sun8i-a83t-ccu.h | ||
| sun8i-de2.h | ||
| sun8i-h3-ccu.h | ||
| sun8i-r-ccu.h | ||
| sun8i-r40-ccu.h | ||
| sun8i-v3s-ccu.h | ||
| sun9i-a80-ccu.h | ||
| sun9i-a80-de.h | ||
| sun9i-a80-usb.h | ||
| sun20i-d1-ccu.h | ||
| sun20i-d1-r-ccu.h | ||
| sun50i-a64-ccu.h | ||
| sun50i-a100-ccu.h | ||
| sun50i-a100-r-ccu.h | ||
| sun50i-h6-ccu.h | ||
| sun50i-h6-r-ccu.h | ||
| sun50i-h616-ccu.h | ||
| sun55i-a523-ccu.h | ||
| sun55i-a523-mcu-ccu.h | ||
| sun55i-a523-r-ccu.h | ||
| suniv-ccu-f1c100s.h | ||
| sunplus,sp7021-reset.h | ||
| tegra124-car.h | ||
| tegra186-reset.h | ||
| tegra194-reset.h | ||
| tegra210-car.h | ||
| tegra234-reset.h | ||
| thead,th1520-reset.h | ||
| ti-syscon.h | ||
| toshiba,tmpv770x.h | ||
| xlnx-versal-resets.h | ||
| xlnx-zynqmp-resets.h | ||