linux/drivers/iommu/riscv
Jason Gunthorpe 082ad5ed07 iommu/riscv: Add NAPOT range invalidation support
Use the RISC-V IOMMU Address Range Invalidation extension
(capabilities.S, spec section 9.3) to invalidate an IOVA range with
a single IOTINVAL.VMA command using NAPOT-encoded addressing.

One iommu_iotlb_gather maps to one NAPOT invalidation command. The
smallest power-of-two aligned range covering the gather is used since
over-invalidation is always safe.

S and NL seem to be orthogonal in the spec, so if NL is not
supported then global invalidation is probably always going to happen
as wiping a large range without a table change is not common.

Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Tested-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-05-19 10:48:09 +02:00
..
iommu-bits.h iommu/riscv: Add NAPOT range invalidation support 2026-05-19 10:48:09 +02:00
iommu-pci.c iommu/riscv: Add shutdown function for iommu driver 2025-01-06 12:38:11 +01:00
iommu-platform.c iommu/riscv: Fix signedness bug 2026-03-27 19:55:52 +01:00
iommu.c iommu/riscv: Add NAPOT range invalidation support 2026-05-19 10:48:09 +02:00
iommu.h iommu/riscv: Add shutdown function for iommu driver 2025-01-06 12:38:11 +01:00
Kconfig iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST 2026-03-17 13:14:24 +01:00
Makefile iommu: make inclusion of riscv directory conditional 2025-05-16 08:46:47 +02:00