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bdf4d82806
Update kcpuid's CSV file to version 3.1, as generated by x86-cpuid-db. Summary of the v3.1 changes: * Fix a few typos that were found during the kernel CPUID data model review. Also include fixes found using an LLM agent review. * Rename thrd_director_nclasses to hw_feedback_nclasses as it's the name used in Intel SDM. See https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.rst for more info. Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/cbe9ff395b3269e112ff7ca414d726ffd7bf0787.1780506200.git.m.wieczorretman@pm.me
1196 lines
92 KiB
Plaintext
1196 lines
92 KiB
Plaintext
# SPDX-License-Identifier: CC0-1.0
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# Generator: x86-cpuid-db v3.1
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#
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# Auto-generated file.
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# Please submit all updates and bugfixes to https://x86-cpuid.org
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#
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# The basic row format is:
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# LEAF, SUBLEAVES, reg, bits, short_name , long_description
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# Leaf 0H
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# Maximum standard leaf + CPU vendor string
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0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf
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0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
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0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
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0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
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# Leaf 1H
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# CPU FMS (Family/Model/Stepping) + standard feature flags
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0x1, 0, eax, 3:0, stepping , Stepping ID
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0x1, 0, eax, 7:4, base_model , Base CPU model ID
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0x1, 0, eax, 11:8, base_family_id , Base CPU family ID
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0x1, 0, eax, 13:12, cpu_type , CPU type
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0x1, 0, eax, 19:16, ext_model , Extended CPU model ID
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0x1, 0, eax, 27:20, ext_family , Extended CPU family ID
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0x1, 0, ebx, 7:0, brand_id , Brand index
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0x1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size
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0x1, 0, ebx, 23:16, n_logical_cpu , Logical CPU count
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0x1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
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0x1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)
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0x1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
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0x1, 0, ecx, 2, dtes64 , 64-bit DS save area
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0x1, 0, ecx, 3, monitor , MONITOR/MWAIT support
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0x1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store
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0x1, 0, ecx, 5, vmx , Virtual Machine Extensions
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0x1, 0, ecx, 6, smx , Safer Mode Extensions
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0x1, 0, ecx, 7, est , Enhanced Intel SpeedStep
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0x1, 0, ecx, 8, tm2 , Thermal Monitor 2
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0x1, 0, ecx, 9, ssse3 , Supplemental SSE3
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0x1, 0, ecx, 10, cid , L1 Context ID
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0x1, 0, ecx, 11, sdbg , Silicon Debug
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0x1, 0, ecx, 12, fma , FMA extensions using YMM state
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0x1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support
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0x1, 0, ecx, 14, xtpr , xTPR Update Control
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0x1, 0, ecx, 15, pdcm , Perfmon and Debug Capability
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0x1, 0, ecx, 17, pcid , Process-context identifiers
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0x1, 0, ecx, 18, dca , Direct Cache Access
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0x1, 0, ecx, 19, sse4_1 , SSE4.1
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0x1, 0, ecx, 20, sse4_2 , SSE4.2
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0x1, 0, ecx, 21, x2apic , X2APIC support
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0x1, 0, ecx, 22, movbe , MOVBE instruction support
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0x1, 0, ecx, 23, popcnt , POPCNT instruction support
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0x1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
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0x1, 0, ecx, 25, aes , AES instructions
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0x1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
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0x1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS
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0x1, 0, ecx, 28, avx , AVX instructions support
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0x1, 0, ecx, 29, f16c , Half-precision floating-point conversion support
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0x1, 0, ecx, 30, rdrand , RDRAND instruction support
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0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
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0x1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
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0x1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
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0x1, 0, edx, 2, de , Debugging Extensions
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0x1, 0, edx, 3, pse , Page Size Extension
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0x1, 0, edx, 4, tsc , Time Stamp Counter
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0x1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)
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0x1, 0, edx, 6, pae , Physical Address Extensions
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0x1, 0, edx, 7, mce , Machine Check Exception
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0x1, 0, edx, 8, cx8 , CMPXCHG8B instruction
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0x1, 0, edx, 9, apic , APIC on-chip
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0x1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
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0x1, 0, edx, 12, mtrr , Memory Type Range Registers
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0x1, 0, edx, 13, pge , Page Global Extensions
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0x1, 0, edx, 14, mca , Machine Check Architecture
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0x1, 0, edx, 15, cmov , Conditional Move Instruction
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0x1, 0, edx, 16, pat , Page Attribute Table
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0x1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
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0x1, 0, edx, 18, pn , Processor Serial Number
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0x1, 0, edx, 19, clflush , CLFLUSH instruction
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0x1, 0, edx, 21, dts , Debug Store
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0x1, 0, edx, 22, acpi , Thermal monitor and clock control
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0x1, 0, edx, 23, mmx , MMX instructions
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0x1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
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0x1, 0, edx, 25, sse , SSE instructions
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0x1, 0, edx, 26, sse2 , SSE2 instructions
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0x1, 0, edx, 27, ss , Self Snoop
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0x1, 0, edx, 28, ht , Hyper-threading
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0x1, 0, edx, 29, tm , Thermal Monitor
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0x1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now reserved
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0x1, 0, edx, 31, pbe , Pending Break Enable
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# Leaf 2H
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# Intel cache and TLB information one-byte descriptors
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0x2, 0, eax, 7:0, iteration_count , Number of times this leaf must be queried
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0x2, 0, eax, 15:8, desc1 , Descriptor #1
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0x2, 0, eax, 23:16, desc2 , Descriptor #2
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0x2, 0, eax, 30:24, desc3 , Descriptor #3
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0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
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0x2, 0, ebx, 7:0, desc4 , Descriptor #4
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0x2, 0, ebx, 15:8, desc5 , Descriptor #5
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0x2, 0, ebx, 23:16, desc6 , Descriptor #6
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0x2, 0, ebx, 30:24, desc7 , Descriptor #7
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0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
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0x2, 0, ecx, 7:0, desc8 , Descriptor #8
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0x2, 0, ecx, 15:8, desc9 , Descriptor #9
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0x2, 0, ecx, 23:16, desc10 , Descriptor #10
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0x2, 0, ecx, 30:24, desc11 , Descriptor #11
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0x2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
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0x2, 0, edx, 7:0, desc12 , Descriptor #12
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0x2, 0, edx, 15:8, desc13 , Descriptor #13
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0x2, 0, edx, 23:16, desc14 , Descriptor #14
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0x2, 0, edx, 30:24, desc15 , Descriptor #15
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0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
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# Leaf 4H
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# Intel deterministic cache parameters
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0x4, 31:0, eax, 4:0, cache_type , Cache type field
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0x4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
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0x4, 31:0, eax, 8, cache_self_init , Self-initializing cache level
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0x4, 31:0, eax, 9, fully_associative , Fully-associative cache
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0x4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache
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0x4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package
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0x4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
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0x4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
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0x4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
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0x4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
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0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
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0x4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
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0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)
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# Leaf 5H
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# MONITOR/MWAIT instructions
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0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
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0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
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0x5, 0, ecx, 0, mwait_ext , MONITOR/MWAIT extensions
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0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break event for MWAIT
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0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states
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0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states
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0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states
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0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states
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0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states
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0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states
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0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states
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0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states
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# Leaf 6H
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# Thermal and power management
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0x6, 0, eax, 0, dtherm , Digital temperature sensor
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0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost
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0x6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)
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0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event
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0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension
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0x6, 0, eax, 6, pts , Package thermal management
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0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers
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0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR)
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0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32])
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0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference
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0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request
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0x6, 0, eax, 13, hdc_base_regs , HDC base registers
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0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0
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0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change
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0x6, 0, eax, 16, hwp_peci_override , HWP PECI override
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0x6, 0, eax, 17, hwp_flexible , Flexible HWP
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0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode
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0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs
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0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP request is supported
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0x6, 0, eax, 22, hwp_ctl , IA32_HWP_CTL MSR
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0x6, 0, eax, 23, thread_director , Intel thread director
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0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25
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0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
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0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
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0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR
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0x6, 0, ecx, 15:8, hw_feedback_nclasses , Number of Intel Thread Director classes
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0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting
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0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
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0x6, 0, edx, 11:8, feedback_sz , Feedback interface structure size, in 4K pages
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0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU hardware feedback interface index
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# Leaf 7H
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# Extended CPU features
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0x7, 0, eax, 31:0, leaf7_n_subleaves , Number of leaf 0x7 subleaves
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0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write
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0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR
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0x7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions)
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0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
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0x7, 0, ebx, 4, hle , Hardware Lock Elision
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0x7, 0, ebx, 5, avx2 , AVX2 instruction set
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0x7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions
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0x7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
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0x7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2
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0x7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB
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0x7, 0, ebx, 10, invpcid , INVPCID instruction (Invalidate Processor Context ID)
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0x7, 0, ebx, 11, rtm , Intel restricted transactional memory
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0x7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache monitoring
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0x7, 0, ebx, 13, zero_fcs_fds , Deprecated FPU CS/DS (stored as zero)
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0x7, 0, ebx, 14, mpx , Intel memory protection extensions
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0x7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcement
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0x7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
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0x7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions
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0x7, 0, ebx, 18, rdseed , RDSEED instruction
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0x7, 0, ebx, 19, adx , ADCX/ADOX instructions
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0x7, 0, ebx, 20, smap , Supervisor mode access prevention
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0x7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add
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0x7, 0, ebx, 23, clflushopt , CLFLUSHOPT instruction
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0x7, 0, ebx, 24, clwb , CLWB instruction
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0x7, 0, ebx, 25, intel_pt , Intel processor trace
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0x7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions
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0x7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instructions
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0x7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instructions
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0x7, 0, ebx, 29, sha_ni , SHA/SHA256 instructions
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0x7, 0, ebx, 30, avx512bw , AVX-512 byte/word instructions
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0x7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extensions
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0x7, 0, ecx, 0, prefetchwt1 , PREFETCHWT1 (Intel Xeon Phi only)
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0x7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instructions
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0x7, 0, ecx, 2, umip , User mode instruction protection
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0x7, 0, ecx, 3, pku , Protection keys for user-space
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0x7, 0, ecx, 4, ospke , OS protection keys enable
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0x7, 0, ecx, 5, waitpkg , WAITPKG instructions
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0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instructions group 2
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0x7, 0, ecx, 7, cet_ss , CET shadow stack features
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0x7, 0, ecx, 8, gfni , Galois field new instructions
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0x7, 0, ecx, 9, vaes , Vector AES instructions
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0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction
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0x7, 0, ecx, 11, avx512_vnni , Vector neural network instructions
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0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms
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0x7, 0, ecx, 13, tme , Intel total memory encryption
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0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DWORD/QWORD
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0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging)
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0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
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0x7, 0, ecx, 22, rdpid , RDPID instruction
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0x7, 0, ecx, 23, key_locker , Intel key locker
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0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection
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0x7, 0, ecx, 25, cldemote , CLDEMOTE instruction
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0x7, 0, ecx, 27, movdiri , MOVDIRI instruction
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0x7, 0, ecx, 28, movdir64b , MOVDIR64B instruction
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0x7, 0, ecx, 29, enqcmd , Enqueue stores (ENQCMD{,S})
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0x7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration
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0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages
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0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services
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0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
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0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision
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0x7, 0, edx, 4, fsrm , Fast short REP MOVSB
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0x7, 0, edx, 5, uintr , User interrupts
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0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
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0x7, 0, edx, 9, srbds_ctrl , SRBDS mitigation MSR
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0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode
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0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
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0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit
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0x7, 0, edx, 14, serialize , SERIALIZE instruction
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0x7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part'
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0x7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking
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0x7, 0, edx, 18, pconfig , PCONFIG instruction
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0x7, 0, edx, 19, arch_lbr , Intel architectural LBRs
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0x7, 0, edx, 20, ibt , CET indirect branch tracking
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0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16
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0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
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0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture
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0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer
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0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions)
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0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors
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0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR
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0x7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR
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0x7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR
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0x7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable
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0x7, 1, eax, 4, avx_vnni , AVX-VNNI instructions
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0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions
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0x7, 1, eax, 6, lass , Linear address space separation
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0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions
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0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23
|
|
0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB
|
|
0x7, 1, eax, 11, fsrs , Fast short REP STOSB
|
|
0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB
|
|
0x7, 1, eax, 17, fred , FRED: Flexible return and event delivery transitions
|
|
0x7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS
|
|
0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing)
|
|
0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data
|
|
0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations
|
|
0x7, 1, eax, 22, hreset , HRESET (Thread director history reset)
|
|
0x7, 1, eax, 23, avx_ifma , Integer fused multiply add
|
|
0x7, 1, eax, 26, lam , Linear address masking
|
|
0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions
|
|
0x7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPIN{,_CTL} MSRs)
|
|
0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
|
|
0x7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
|
|
0x7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from Granite Rapids)
|
|
0x7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions
|
|
0x7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use
|
|
0x7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
|
|
0x7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
|
|
0x7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
|
|
0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
|
|
0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
|
|
0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
|
|
0x7, 2, edx, 6, uclock_disable , UC-lock disable
|
|
|
|
# Leaf 9H
|
|
# Intel DCA (Direct Cache Access)
|
|
|
|
0x9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS
|
|
|
|
# Leaf AH
|
|
# Intel PMU (Performance Monitoring Unit)
|
|
|
|
0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID
|
|
0xa, 0, eax, 15:8, num_counters_gp , Number of general-purpose PMU counters per logical CPU
|
|
0xa, 0, eax, 23:16, bit_width_gp , Bitwidth of PMU general-purpose counters
|
|
0xa, 0, eax, 31:24, events_mask_len , Length of CPUID(0xa).EBX bit vector
|
|
0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available
|
|
0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available
|
|
0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available
|
|
0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available
|
|
0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available
|
|
0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available
|
|
0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available
|
|
0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available
|
|
0xa, 0, ebx, 8, no_backend_bound , Topdown backend bound not available
|
|
0xa, 0, ebx, 9, no_bad_speculation , Topdown bad speculation not available
|
|
0xa, 0, ebx, 10, no_frontend_bound , Topdown frontend bound not available
|
|
0xa, 0, ebx, 11, no_retiring , Topdown retiring not available
|
|
0xa, 0, ebx, 12, no_lbr_inserts , LBR inserts not available
|
|
0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap
|
|
0xa, 0, edx, 4:0, num_counters_fixed , Number of fixed PMU counters
|
|
0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth of PMU fixed counters
|
|
0xa, 0, edx, 15, anythread_deprecation , AnyThread mode deprecation
|
|
|
|
# Leaf BH
|
|
# CPU extended topology v1
|
|
|
|
0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
|
|
0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
|
|
0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID)
|
|
0xb, 1:0, ecx, 15:8, domain_type , This domain type
|
|
0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
|
|
|
|
# Leaf DH
|
|
# CPU extended state
|
|
|
|
0xd, 0, eax, 0, xcr0_x87 , XCR0.X87
|
|
0xd, 0, eax, 1, xcr0_sse , XCR0.SSE
|
|
0xd, 0, eax, 2, xcr0_avx , XCR0.AVX
|
|
0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS: MPX BND0-BND3 registers
|
|
0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers
|
|
0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK: AVX-512 k0-k7 registers
|
|
0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 registers
|
|
0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 registers
|
|
0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU: XSAVE PKRU registers
|
|
0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U: CET user state
|
|
0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S: CET supervisor state
|
|
0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG: AMX can manage TILECONFIG
|
|
0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA: AMX can manage TILEDATA
|
|
0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XRSTOR area byte size, for XCR0 enabled features
|
|
0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTOR area max byte size, all CPU features
|
|
0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP: Light-weight Profiling
|
|
0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction
|
|
0xd, 1, eax, 1, xsavec , XSAVEC instruction
|
|
0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1
|
|
0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR)
|
|
0xd, 1, eax, 4, xfd , Extended feature disable
|
|
0xd, 1, ebx, 31:0, xsave_sz_xcr0_xss , XSAVES/XSAVEC area byte size, for XCR0|XSS enabled features
|
|
0xd, 1, ecx, 8, xss_pt , PT state
|
|
0xd, 1, ecx, 10, xss_pasid , PASID state
|
|
0xd, 1, ecx, 11, xss_cet_u , CET user state
|
|
0xd, 1, ecx, 12, xss_cet_s , CET supervisor state
|
|
0xd, 1, ecx, 13, xss_hdc , HDC state
|
|
0xd, 1, ecx, 14, xss_uintr , UINTR state
|
|
0xd, 1, ecx, 15, xss_lbr , LBR state
|
|
0xd, 1, ecx, 16, xss_hwp , HWP state
|
|
0xd, 63:2, eax, 31:0, xsave_sz , Subleaf-N feature save area size, in bytes
|
|
0xd, 63:2, ebx, 31:0, xsave_offset , Subleaf-N feature save area offset, in bytes
|
|
0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit (otherwise XCR0)
|
|
0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N XSAVE area is 64-byte aligned
|
|
|
|
# Leaf FH
|
|
# Intel RDT / AMD PQoS resource monitoring
|
|
|
|
0xf, 0, ebx, 31:0, core_rmid_max , RMID max within this core (0-based)
|
|
0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring
|
|
0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based)
|
|
0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit
|
|
0xf, 1, eax, 9, io_rdt_cmt , non-CPU agent supporting Intel RDT CMT present
|
|
0xf, 1, eax, 10, io_rdt_mbm , non-CPU agent supporting Intel RDT MBM present
|
|
0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes
|
|
0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID
|
|
0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring
|
|
0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring
|
|
0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring
|
|
|
|
# Leaf 10H
|
|
# Intel RDT / AMD PQoS allocation
|
|
|
|
0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology
|
|
0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology
|
|
0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation
|
|
0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation
|
|
0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT allocation units bitmap
|
|
0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent
|
|
0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT Code and Data Prioritization
|
|
0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value
|
|
0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max Class of Service
|
|
0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation
|
|
0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls
|
|
0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear
|
|
0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service
|
|
|
|
# Leaf 12H
|
|
# Intel SGX (Software Guard Extensions)
|
|
|
|
0x12, 0, eax, 0, sgx1 , SGX1 leaf functions
|
|
0x12, 0, eax, 1, sgx2 , SGX2 leaf functions
|
|
0x12, 0, eax, 5, enclv_leaves , ENCLV leaves
|
|
0x12, 0, eax, 6, encls_leaves , ENCLS leaves
|
|
0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2
|
|
0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN
|
|
0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA
|
|
0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: Enclave #PF and #GP reporting
|
|
0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: Enclave #CP reporting
|
|
0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2)
|
|
0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2)
|
|
0x12, 1, eax, 0, secs_attr_init , Enclave initialized by EINIT
|
|
0x12, 1, eax, 1, secs_attr_debug , Enclave permits debugger read/write
|
|
0x12, 1, eax, 2, secs_attr_mode64bit , Enclave runs in 64-bit mode
|
|
0x12, 1, eax, 4, secs_attr_provisionkey , Provisioning key
|
|
0x12, 1, eax, 5, secs_attr_einittoken_key, EINIT token key
|
|
0x12, 1, eax, 6, secs_attr_cet , CET attributes
|
|
0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing
|
|
0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications
|
|
0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87
|
|
0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SSE
|
|
0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX
|
|
0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers)
|
|
0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers)
|
|
0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (AVX-512 k0-k7 registers)
|
|
0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZMM7/15 registers)
|
|
0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM31 registers)
|
|
0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (XSAVE PKRU registers)
|
|
0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (AMX can manage TILECONFIG)
|
|
0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (AMX can manage TILEDATA)
|
|
0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type
|
|
0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base address, bits[12:31]
|
|
0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base address, bits[32:51]
|
|
0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding
|
|
0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC section size, bits[12:31]
|
|
0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51]
|
|
|
|
# Leaf 14H
|
|
# Intel Processor Trace
|
|
|
|
0x14, 0, eax, 31:0, pt_max_subleaf , Maximum leaf 0x14 subleaf
|
|
0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible
|
|
0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode
|
|
0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation
|
|
0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression
|
|
0x14, 0, ebx, 4, ptwrite , PTWRITE instruction
|
|
0x14, 0, ebx, 5, power_event_trace , Power Event Trace
|
|
0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation
|
|
0x14, 0, ebx, 7, event_trace , Event Trace packet generation
|
|
0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable
|
|
0x14, 0, ecx, 0, topa_output , ToPA output scheme
|
|
0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
|
|
0x14, 0, ecx, 2, single_range_output , Single-range output
|
|
0x14, 0, ecx, 3, trace_transport_output , Trace Transport subsystem output
|
|
0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)
|
|
0x14, 1, eax, 2:0, num_address_ranges , Number of configurable address ranges
|
|
0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap
|
|
0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap
|
|
0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap
|
|
|
|
# Leaf 15H
|
|
# Intel TSC (Time Stamp Counter)
|
|
|
|
0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio
|
|
0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio
|
|
0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz
|
|
|
|
# Leaf 16H
|
|
# Intel processor frequency
|
|
|
|
0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz
|
|
0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz
|
|
0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz
|
|
|
|
# Leaf 17H
|
|
# Intel SoC vendor attributes
|
|
|
|
0x17, 0, eax, 31:0, soc_max_subleaf , Maximum leaf 0x17 subleaf
|
|
0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID
|
|
0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumeration scheme (not Intel)
|
|
0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor
|
|
0x17, 0, edx, 31:0, soc_stepping_id , SoC project stepping ID, assigned by vendor
|
|
0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
|
|
0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
|
|
0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
|
|
0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)
|
|
|
|
# Leaf 18H
|
|
# Intel deterministic address translation (TLB) parameters
|
|
|
|
0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum leaf 0x18 subleaf
|
|
0x18, 31:0, ebx, 0, tlb_4k_page , TLB supports 4KB-page entries
|
|
0x18, 31:0, ebx, 1, tlb_2m_page , TLB supports 2MB-page entries
|
|
0x18, 31:0, ebx, 2, tlb_4m_page , TLB supports 4MB-page entries
|
|
0x18, 31:0, ebx, 3, tlb_1g_page , TLB supports 1GB-page entries
|
|
0x18, 31:0, ebx, 10:8, hard_partitioning , Partitioning between logical CPUs
|
|
0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity
|
|
0x18, 31:0, ecx, 31:0, n_sets , Number of sets
|
|
0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
|
|
0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
|
|
0x18, 31:0, edx, 8, is_fully_associative , Fully-associative
|
|
0x18, 31:0, edx, 25:14, tlb_max_addressable_ids, Max number of addressable IDs - 1
|
|
|
|
# Leaf 19H
|
|
# Intel key locker
|
|
|
|
0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key locker restriction
|
|
0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction
|
|
0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction
|
|
0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions
|
|
0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions
|
|
0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups
|
|
0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter
|
|
0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization
|
|
|
|
# Leaf 1AH
|
|
# Intel hybrid CPUs identification (e.g. Atom, Core)
|
|
|
|
0x1a, 0, eax, 23:0, core_native_model , This core's native model ID
|
|
0x1a, 0, eax, 31:24, core_type , This core's type
|
|
|
|
# Leaf 1BH
|
|
# Intel PCONFIG (Platform configuration)
|
|
|
|
0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type
|
|
0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID
|
|
0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supported PCONFIG target ID
|
|
0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID
|
|
|
|
# Leaf 1CH
|
|
# Intel LBR (Last Branch Record)
|
|
|
|
0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask
|
|
0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may be cleared on MWAIT C-state > C1
|
|
0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP (otherwise effective IP)
|
|
0x1c, 0, ebx, 0, lbr_cpl , CPL filtering
|
|
0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering
|
|
0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode
|
|
0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit
|
|
0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry)
|
|
0x1c, 0, ecx, 2, lbr_branch_type , Branch type field
|
|
0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , PMU-events logging support
|
|
|
|
# Leaf 1DH
|
|
# Intel AMX (Advanced Matrix Extensions) tile information
|
|
|
|
0x1d, 0, eax, 31:0, amx_max_palette , Highest palette ID / subleaf ID
|
|
0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes
|
|
0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes
|
|
0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes
|
|
0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles
|
|
0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows
|
|
|
|
# Leaf 1EH
|
|
# Intel TMUL (Tile-matrix Multiply)
|
|
|
|
0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns)
|
|
0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maximum SIMD dimension, N (column bytes)
|
|
|
|
# Leaf 1FH
|
|
# Intel extended topology v2
|
|
|
|
0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
|
|
0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
|
|
0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
|
|
0x1f, 5:0, ecx, 15:8, domain_type , This domain type
|
|
0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
|
|
|
|
# Leaf 20H
|
|
# Intel HRESET (History Reset)
|
|
|
|
0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1
|
|
0x20, 0, ebx, 0, hreset_thread_director , Intel thread director HRESET
|
|
|
|
# Leaf 21H
|
|
# Intel TD (Trust Domain)
|
|
|
|
0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
|
|
0x21, 0, ecx, 31:0, tdx_vendorid_2 , TDX vendor ID string bytes 8 - 11
|
|
0x21, 0, edx, 31:0, tdx_vendorid_1 , TDX vendor ID string bytes 4 - 7
|
|
|
|
# Leaf 23H
|
|
# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)
|
|
|
|
0x23, 0, eax, 0, subleaf_0 , Subleaf 0, this subleaf
|
|
0x23, 0, eax, 1, counters_subleaf , Subleaf 1, PMU counter bitmaps
|
|
0x23, 0, eax, 2, acr_subleaf , Subleaf 2, Auto Counter Reload bitmaps
|
|
0x23, 0, eax, 3, events_subleaf , Subleaf 3, PMU event bitmaps
|
|
0x23, 0, eax, 4, pebs_caps_subleaf , Subleaf 4, PEBS capabilities
|
|
0x23, 0, eax, 5, pebs_subleaf , Subleaf 5, Arch PEBS bitmaps
|
|
0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 bit
|
|
0x23, 0, ebx, 1, eq , IA32_PERFEVTSELx MSRs EQ bit
|
|
0x23, 0, ebx, 2, rdpmc_user_disable , RDPMC userspace disable
|
|
0x23, 1, eax, 31:0, gp_counters , Bitmap of general-purpose PMU counters
|
|
0x23, 1, ebx, 31:0, fixed_counters , Bitmap of fixed PMU counters
|
|
0x23, 2, eax, 31:0, acr_gp_reload , Bitmap of general-purpose counters that can be reloaded
|
|
0x23, 2, ebx, 31:0, acr_fixed_reload , Bitmap of fixed counters that can be reloaded
|
|
0x23, 2, ecx, 31:0, acr_gp_trigger , Bitmap of general-purpose counters that can trigger reloads
|
|
0x23, 2, edx, 31:0, acr_fixed_trigger , Bitmap of fixed counters that can trigger reloads
|
|
0x23, 3, eax, 0, core_cycles_evt , Core cycles event
|
|
0x23, 3, eax, 1, insn_retired_evt , Instructions retired event
|
|
0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event
|
|
0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event
|
|
0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event
|
|
0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event
|
|
0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event
|
|
0x23, 3, eax, 7, td_slots_evt , Topdown slots event
|
|
0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event
|
|
0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event
|
|
0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event
|
|
0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event
|
|
0x23, 4, ebx, 3, allow_in_record , ALLOW_IN_RECORD bit in MSRs
|
|
0x23, 4, ebx, 4, counters_gp , Counters group sub-group general-purpose counters
|
|
0x23, 4, ebx, 5, counters_fixed , Counters group sub-group fixed-function counters
|
|
0x23, 4, ebx, 6, counters_metrics , Counters group sub-group performance metrics
|
|
0x23, 4, ebx, 9:8, lbr , LBR group
|
|
0x23, 4, ebx, 23:16, xer , XER group
|
|
0x23, 4, ebx, 29, gpr , GPR group
|
|
0x23, 4, ebx, 30, aux , AUX group
|
|
0x23, 5, eax, 31:0, pebs_gp , Architectural PEBS general-purpose counters
|
|
0x23, 5, ebx, 31:0, pebs_pdist_gp , Architectural PEBS PDIST general-purpose counters
|
|
0x23, 5, ecx, 31:0, pebs_fixed , Architectural PEBS fixed counters
|
|
0x23, 5, edx, 31:0, pebs_pdist_fixed , Architectural PEBS PDIST fixed counters
|
|
|
|
# Leaf 40000000H
|
|
# Maximum hypervisor leaf + hypervisor vendor string
|
|
|
|
0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor leaf
|
|
0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3
|
|
0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7
|
|
0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
|
|
|
|
# Leaf 80000000H
|
|
# Maximum extended leaf + CPU vendor string
|
|
|
|
0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended CPUID leaf
|
|
0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3
|
|
0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11
|
|
0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
|
|
|
|
# Leaf 80000001H
|
|
# Extended CPU features
|
|
|
|
0x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID
|
|
0x80000001, 0, eax, 7:4, e_base_model , Base processor model
|
|
0x80000001, 0, eax, 11:8, e_base_family , Base processor family
|
|
0x80000001, 0, eax, 13:12, e_base_type , Base processor type (Transmeta)
|
|
0x80000001, 0, eax, 19:16, e_ext_model , Extended processor model
|
|
0x80000001, 0, eax, 27:20, e_ext_family , Extended processor family
|
|
0x80000001, 0, ebx, 15:0, brand_id , Brand ID
|
|
0x80000001, 0, ebx, 31:28, pkg_type , Package type
|
|
0x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
|
|
0x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No HT)
|
|
0x80000001, 0, ecx, 2, svm , Secure Virtual Machine
|
|
0x80000001, 0, ecx, 3, extapic , Extended APIC space
|
|
0x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV CR0 means MOV CR8
|
|
0x80000001, 0, ecx, 5, abm , LZCNT advanced bit manipulation
|
|
0x80000001, 0, ecx, 6, sse4a , SSE4A support
|
|
0x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode
|
|
0x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PREFETCH/PREFETCHW support
|
|
0x80000001, 0, ecx, 9, osvw , OS visible workaround
|
|
0x80000001, 0, ecx, 10, ibs , Instruction based sampling
|
|
0x80000001, 0, ecx, 11, xop , XOP: extended operation (AVX instructions)
|
|
0x80000001, 0, ecx, 12, skinit , SKINIT/STGI support
|
|
0x80000001, 0, ecx, 13, wdt , Watchdog timer support
|
|
0x80000001, 0, ecx, 15, lwp , Lightweight profiling
|
|
0x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction
|
|
0x80000001, 0, ecx, 17, tce , Translation cache extension
|
|
0x80000001, 0, ecx, 19, nodeid_msr , NodeId MSR (0xc001100c)
|
|
0x80000001, 0, ecx, 21, tbm , Trailing bit manipulations
|
|
0x80000001, 0, ecx, 22, topoext , Topology Extensions (leaf 0x8000001d)
|
|
0x80000001, 0, ecx, 23, perfctr_core , Core performance counter extensions
|
|
0x80000001, 0, ecx, 24, perfctr_nb , NB/DF performance counter extensions
|
|
0x80000001, 0, ecx, 26, bpext , Data access breakpoint extension
|
|
0x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter
|
|
0x80000001, 0, ecx, 28, perfctr_llc , LLC (L3) performance counter extensions
|
|
0x80000001, 0, ecx, 29, mwaitx , MWAITX/MONITORX support
|
|
0x80000001, 0, ecx, 30, addr_mask_ext , Breakpoint address mask extension (to bit 31)
|
|
0x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
|
|
0x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
|
|
0x80000001, 0, edx, 2, e_de , Debugging Extensions
|
|
0x80000001, 0, edx, 3, e_pse , Page Size Extension
|
|
0x80000001, 0, edx, 4, e_tsc , Time Stamp Counter
|
|
0x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR and WRMSR support)
|
|
0x80000001, 0, edx, 6, pae , Physical Address Extensions
|
|
0x80000001, 0, edx, 7, mce , Machine Check Exception
|
|
0x80000001, 0, edx, 8, cx8 , CMPXCHG8B instruction
|
|
0x80000001, 0, edx, 9, apic , APIC on-chip
|
|
0x80000001, 0, edx, 11, syscall , SYSCALL and SYSRET instructions
|
|
0x80000001, 0, edx, 12, mtrr , Memory Type Range Registers
|
|
0x80000001, 0, edx, 13, pge , Page Global Extensions
|
|
0x80000001, 0, edx, 14, mca , Machine Check Architecture
|
|
0x80000001, 0, edx, 15, cmov , Conditional Move Instruction
|
|
0x80000001, 0, edx, 16, pat , Page Attribute Table
|
|
0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
|
|
0x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit
|
|
0x80000001, 0, edx, 20, nx , No-execute page protection
|
|
0x80000001, 0, edx, 22, mmxext , AMD MMX extensions
|
|
0x80000001, 0, edx, 23, e_mmx , MMX instructions
|
|
0x80000001, 0, edx, 24, e_fxsr , FXSAVE and FXRSTOR instructions
|
|
0x80000001, 0, edx, 25, fxsr_opt , FXSAVE and FXRSTOR optimizations
|
|
0x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
|
|
0x80000001, 0, edx, 27, rdtscp , RDTSCP instruction
|
|
0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
|
|
0x80000001, 0, edx, 30, 3dnowext , AMD 3DNow extensions
|
|
0x80000001, 0, edx, 31, 3dnow , 3DNow instructions
|
|
|
|
# Leaf 80000002H
|
|
# CPU brand ID string, bytes 0 - 15
|
|
|
|
0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3
|
|
0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7
|
|
0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11
|
|
0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
|
|
|
|
# Leaf 80000003H
|
|
# CPU brand ID string, bytes 16 - 31
|
|
|
|
0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19
|
|
0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23
|
|
0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27
|
|
0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
|
|
|
|
# Leaf 80000004H
|
|
# CPU brand ID string, bytes 32 - 47
|
|
|
|
0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35
|
|
0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39
|
|
0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43
|
|
0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
|
|
|
|
# Leaf 80000005H
|
|
# AMD/Transmeta L1 cache and TLB
|
|
|
|
0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entries, 2M and 4M pages
|
|
0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB associativity, 2M and 4M pages
|
|
0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB #entries, 2M and 4M pages
|
|
0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB associativity, 2M and 4M pages
|
|
0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages
|
|
0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB associativity, 4K pages
|
|
0x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB #entries, 4K pages
|
|
0x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB associativity, 4K pages
|
|
0x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes
|
|
0x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcache lines per tag
|
|
0x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcache associativity
|
|
0x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcache size, in KB
|
|
0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes
|
|
0x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache lines per tag
|
|
0x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache associativity
|
|
0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB
|
|
|
|
# Leaf 80000006H
|
|
# (Mostly AMD) L2/L3 cache and TLB
|
|
|
|
0x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #entries, 2M and 4M pages
|
|
0x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB associativity, 2M and 4M pages
|
|
0x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB #entries, 2M and 4M pages
|
|
0x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB associativity, 2M and 4M pages
|
|
0x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB #entries, 4K pages
|
|
0x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB associativity, 4K pages
|
|
0x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB #entries, 4K pages
|
|
0x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB associativity, 4K pages
|
|
0x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes
|
|
0x80000006, 0, ecx, 11:8, l2_nlines , L2 cache number of lines per tag
|
|
0x80000006, 0, ecx, 15:12, l2_assoc , L2 cache associativity
|
|
0x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache size, in KB
|
|
0x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes
|
|
0x80000006, 0, edx, 11:8, l3_nlines , L3 cache number of lines per tag
|
|
0x80000006, 0, edx, 15:12, l3_assoc , L3 cache associativity
|
|
0x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range
|
|
|
|
# Leaf 80000007H
|
|
# CPU power management (mostly AMD) and AMD RAS
|
|
|
|
0x80000007, 0, ebx, 0, overflow_recov , MCA overflow conditions not fatal
|
|
0x80000007, 0, ebx, 1, succor , Software containment of uncorrectable errors
|
|
0x80000007, 0, ebx, 2, hw_assert , Hardware assert MSRs
|
|
0x80000007, 0, ebx, 3, smca , Scalable MCA (MCAX MSRs)
|
|
0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU power sample time ratio
|
|
0x80000007, 0, edx, 0, digital_temp , Digital temperature sensor
|
|
0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling
|
|
0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! voltage scaling
|
|
0x80000007, 0, edx, 3, thermal_trip , THERMTRIP (Thermal Trip)
|
|
0x80000007, 0, edx, 4, hw_thermal_control , Hardware thermal control
|
|
0x80000007, 0, edx, 5, sw_thermal_control , Software thermal control
|
|
0x80000007, 0, edx, 6, 100mhz_steps , 100 MHz multiplier control
|
|
0x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
|
|
0x80000007, 0, edx, 8, constant_tsc , TSC ticks at constant rate across all P and C states
|
|
0x80000007, 0, edx, 9, cpb , Core performance boost
|
|
0x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency interface
|
|
0x80000007, 0, edx, 11, proc_feedback , Processor feedback interface (deprecated)
|
|
0x80000007, 0, edx, 12, acc_power , Processor power reporting interface
|
|
0x80000007, 0, edx, 13, connected_standby , CPU Connected Standby support
|
|
0x80000007, 0, edx, 14, rapl , Runtime Average Power Limit interface
|
|
|
|
# Leaf 80000008H
|
|
# CPU capacity parameters and extended feature flags (mostly AMD)
|
|
|
|
0x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits
|
|
0x80000008, 0, eax, 15:8, virt_addr_bits , Max virtual address bits
|
|
0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits
|
|
0x80000008, 0, ebx, 0, clzero , CLZERO instruction
|
|
0x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR
|
|
0x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRSTOR always saves/restores FPU error pointers
|
|
0x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate
|
|
0x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level)
|
|
0x80000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit)
|
|
0x80000008, 0, ebx, 8, mcommit , MCOMMIT instruction
|
|
0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD instruction
|
|
0x80000008, 0, ebx, 12, amd_ibpb , Indirect Branch Prediction Barrier
|
|
0x80000008, 0, ebx, 13, wbinvd_int , Interruptible WBINVD/WBNOINVD
|
|
0x80000008, 0, ebx, 14, amd_ibrs , Indirect Branch Restricted Speculation
|
|
0x80000008, 0, ebx, 15, amd_stibp , Single Thread Indirect Branch Prediction mode
|
|
0x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred
|
|
0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred
|
|
0x80000008, 0, ebx, 18, ibrs_fast , IBRS is preferred over software solution
|
|
0x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provides same mode protection
|
|
0x80000008, 0, ebx, 20, no_efer_lmsle , Long-Mode Segment Limit Enable unsupported
|
|
0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set
|
|
0x80000008, 0, ebx, 23, amd_ppin , Protected Processor Inventory Number
|
|
0x80000008, 0, ebx, 24, amd_ssbd , Speculative Store Bypass Disable
|
|
0x80000008, 0, ebx, 25, virt_ssbd , virtualized SSBD (Speculative Store Bypass Disable)
|
|
0x80000008, 0, ebx, 26, amd_ssb_no , SSBD is not needed (fixed in hardware)
|
|
0x80000008, 0, ebx, 27, cppc , Collaborative Processor Performance Control
|
|
0x80000008, 0, ebx, 28, amd_psfd , Predictive Store Forward Disable
|
|
0x80000008, 0, ebx, 29, btc_no , CPU not affected by Branch Type Confusion
|
|
0x80000008, 0, ebx, 30, ibpb_ret , IBPB clears RSB/RAS too
|
|
0x80000008, 0, ebx, 31, brs , Branch Sampling
|
|
0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1
|
|
0x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of thread core ID bits (shift) in APIC ID
|
|
0x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size
|
|
0x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB maximum page count
|
|
0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input)
|
|
|
|
# Leaf 8000000AH
|
|
# AMD SVM (Secure Virtual Machine)
|
|
|
|
0x8000000a, 0, eax, 7:0, svm_version , SVM revision number
|
|
0x8000000a, 0, ebx, 31:0, svm_nasid , Number of address space identifiers (ASID)
|
|
0x8000000a, 0, ecx, 4, pml , Page Modification Logging (PML)
|
|
0x8000000a, 0, edx, 0, npt , Nested paging
|
|
0x8000000a, 0, edx, 1, lbrv , LBR virtualization
|
|
0x8000000a, 0, edx, 2, svm_lock , SVM lock
|
|
0x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT
|
|
0x8000000a, 0, edx, 4, tsc_scale , MSR-based TSC rate control
|
|
0x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support
|
|
0x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control
|
|
0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
|
|
0x8000000a, 0, edx, 10, pausefilter , Pause intercept filter
|
|
0x8000000a, 0, edx, 12, pfthreshold , Pause filter threshold
|
|
0x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller
|
|
0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VMSAVE/VMLOAD (nested virtualization)
|
|
0x8000000a, 0, edx, 16, vgif , Virtualize the Global Interrupt Flag
|
|
0x8000000a, 0, edx, 17, gmet , Guest mode execution trap
|
|
0x8000000a, 0, edx, 18, x2avic , Virtual x2APIC
|
|
0x8000000a, 0, edx, 19, sss_check , Supervisor Shadow Stack restrictions
|
|
0x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SPEC_CTRL
|
|
0x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
|
|
0x8000000a, 0, edx, 23, h_mce_override , Host MCE override
|
|
0x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB
|
|
0x8000000a, 0, edx, 25, vnmi , NMI virtualization
|
|
0x8000000a, 0, edx, 26, ibs_virt , IBS Virtualization
|
|
0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended LVT offset fault change
|
|
0x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME address check
|
|
|
|
# Leaf 80000019H
|
|
# AMD TLB characteristics for 1GB pages
|
|
|
|
0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages
|
|
0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages
|
|
0x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages
|
|
0x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages
|
|
0x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages
|
|
0x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages
|
|
0x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages
|
|
0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages
|
|
|
|
# Leaf 8000001AH
|
|
# AMD instruction optimizations
|
|
|
|
0x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
|
|
0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
|
|
0x8000001a, 0, eax, 2, fp_256 , Internal FP/SSE exec data path is 256-bits wide
|
|
|
|
# Leaf 8000001BH
|
|
# AMD IBS (Instruction-Based Sampling)
|
|
|
|
0x8000001b, 0, eax, 0, ibs_flags , IBS feature flags
|
|
0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling
|
|
0x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling
|
|
0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter
|
|
0x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode
|
|
0x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting
|
|
0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits
|
|
0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication
|
|
0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication
|
|
0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR
|
|
0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR
|
|
0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering (Zen4+)
|
|
|
|
# Leaf 8000001CH
|
|
# AMD LWP (Lightweight Profiling)
|
|
|
|
0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP is available to application programs
|
|
0x8000001c, 0, eax, 1, os_lwpval , OS: LWPVAL instruction
|
|
0x8000001c, 0, eax, 2, os_lwp_ire , OS: Instructions Retired Event
|
|
0x8000001c, 0, eax, 3, os_lwp_bre , OS: Branch Retired Event
|
|
0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcache Miss Event
|
|
0x8000001c, 0, eax, 5, os_lwp_cnh , OS: CPU Clocks Not Halted event
|
|
0x8000001c, 0, eax, 6, os_lwp_rnh , OS: CPU Reference clocks Not Halted event
|
|
0x8000001c, 0, eax, 29, os_lwp_cont , OS: LWP sampling in continuous mode
|
|
0x8000001c, 0, eax, 30, os_lwp_ptsc , OS: Performance Time Stamp Counter in event records
|
|
0x8000001c, 0, eax, 31, os_lwp_int , OS: Interrupt on threshold overflow
|
|
0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , Control Block size, in quadwords
|
|
0x8000001c, 0, ebx, 15:8, lwp_event_sz , Event record size, in bytes
|
|
0x8000001c, 0, ebx, 23:16, lwp_max_events , Max EventID supported
|
|
0x8000001c, 0, ebx, 31:24, lwp_event_offset , Control Block events area offset
|
|
0x8000001c, 0, ecx, 4:0, lwp_latency_max , Cache latency counters number of bits
|
|
0x8000001c, 0, ecx, 5, lwp_data_addr , Cache miss events report data cache address
|
|
0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache latency rounding amount
|
|
0x8000001c, 0, ecx, 15:9, lwp_version , LWP version
|
|
0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event record units
|
|
0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered
|
|
0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP)
|
|
0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events: filter by cache level
|
|
0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events: filter by latency
|
|
0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP available
|
|
0x8000001c, 0, edx, 1, hw_lwpval , HW: LWPVAL available
|
|
0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Instructions Retired Event
|
|
0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Branch Retired Event
|
|
0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcache Miss Event
|
|
0x8000001c, 0, edx, 5, hw_lwp_cnh , HW: Clocks Not Halted event
|
|
0x8000001c, 0, edx, 6, hw_lwp_rnh , HW: Reference clocks Not Halted event
|
|
0x8000001c, 0, edx, 29, hw_lwp_cont , HW: LWP sampling in continuous mode
|
|
0x8000001c, 0, edx, 30, hw_lwp_ptsc , HW: Performance Time Stamp Counter in event records
|
|
0x8000001c, 0, edx, 31, hw_lwp_int , HW: Interrupt on threshold overflow
|
|
|
|
# Leaf 8000001DH
|
|
# AMD deterministic cache parameters
|
|
|
|
0x8000001d, 31:0, eax, 4:0, cache_type , Cache type field
|
|
0x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)
|
|
0x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level
|
|
0x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache
|
|
0x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number of logical CPUs sharing cache
|
|
0x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
|
|
0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
|
|
0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
|
|
0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
|
|
0x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
|
|
0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
|
|
|
|
# Leaf 8000001EH
|
|
# AMD CPU topology
|
|
|
|
0x8000001e, 0, eax, 31:0, ext_apic_id , Extended APIC ID
|
|
0x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID
|
|
0x8000001e, 0, ebx, 15:8, core_nthreads , #Threads per core (zero-based)
|
|
0x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU
|
|
0x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in invoking logical CPU's package/socket
|
|
|
|
# Leaf 8000001FH
|
|
# AMD encrypted memory capabilities (SME/SEV)
|
|
|
|
0x8000001f, 0, eax, 0, sme , Secure Memory Encryption
|
|
0x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization
|
|
0x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR
|
|
0x8000001f, 0, eax, 3, sev_es , SEV Encrypted State
|
|
0x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging
|
|
0x8000001f, 0, eax, 5, vm_permission_levels , VMPL
|
|
0x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction
|
|
0x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadow stack
|
|
0x8000001f, 0, eax, 8, secure_tsc , Secure TSC
|
|
0x8000001f, 0, eax, 9, v_tsc_aux , Hardware virtualizes TSC_AUX
|
|
0x8000001f, 0, eax, 10, sme_coherent , Cache coherency enforcement across encryption domains
|
|
0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor
|
|
0x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported
|
|
0x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported
|
|
0x8000001f, 0, eax, 14, debug_swap , SEV-ES: Full debug state swap
|
|
0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host
|
|
0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption
|
|
0x8000001f, 0, eax, 17, vmgexit_parameter , SEV_FEATURES: VmgexitParameter
|
|
0x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR
|
|
0x8000001f, 0, eax, 19, virt_ibs , SEV-ES guests: IBS state virtualization
|
|
0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection
|
|
0x8000001f, 0, eax, 25, smt_protection , SMT protection
|
|
0x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR
|
|
0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs
|
|
0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number to enable memory encryption
|
|
0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space in bits
|
|
0x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL)
|
|
0x8000001f, 0, ecx, 31:0, enc_guests_max , Max number of simultaneous encrypted guests
|
|
0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum ASID for SEV-enabled SEV-ES-disabled guest
|
|
|
|
# Leaf 80000020H
|
|
# AMD PQoS (Platform QoS) extended features
|
|
|
|
0x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support
|
|
0x80000020, 0, ebx, 2, smba , Slow Memory Bandwidth Allocation support
|
|
0x80000020, 0, ebx, 3, bmec , Bandwidth Monitoring Event Configuration support
|
|
0x80000020, 0, ebx, 4, l3rr , L3 Range Reservation support
|
|
0x80000020, 0, ebx, 5, abmc , Assignable Bandwidth Monitoring Counters
|
|
0x80000020, 0, ebx, 6, sdciae , Smart Data Cache Injection (SDCI) Allocation Enforcement
|
|
0x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size
|
|
0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)
|
|
0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enforcement limit size
|
|
0x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)
|
|
0x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events available
|
|
0x80000020, 3, ecx, 0, bmec_local_reads , Local NUMA reads can be tracked
|
|
0x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked
|
|
0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes can be tracked
|
|
0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes can be tracked
|
|
0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can be tracked
|
|
0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can be tracked
|
|
0x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS victims to all types of memory can be tracked
|
|
|
|
# Leaf 80000021H
|
|
# AMD extended CPU features 2
|
|
|
|
0x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints
|
|
0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
|
|
0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC
|
|
0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock
|
|
0x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base
|
|
0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
|
|
0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
|
|
0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available
|
|
0x80000021, 0, eax, 10, fsrs , Fast Short REP STOSB
|
|
0x80000021, 0, eax, 11, fsrc , Fast Short REP CMPSB
|
|
0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR
|
|
0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
|
|
0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0
|
|
0x80000021, 0, eax, 18, epsf , Enhanced Predictive Store Forwarding
|
|
0x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS
|
|
0x80000021, 0, eax, 24, eraps , Enhanced Return Address Predictor Security
|
|
0x80000021, 0, eax, 27, sbpb , Selective Branch Predictor Barrier
|
|
0x80000021, 0, eax, 28, ibpb_brtype , Branch predictions flushed from CPU branch predictor
|
|
0x80000021, 0, eax, 29, srso_no , No SRSO vulnerability
|
|
0x80000021, 0, eax, 30, srso_uk_no , No SRSO at user-kernel boundary
|
|
0x80000021, 0, eax, 31, srso_msr_fix , MSR BP_CFG[BpSpecReduce] SRSO mitigation
|
|
0x80000021, 0, ebx, 15:0, microcode_patch_size , Microcode patch size, in 16-byte units
|
|
0x80000021, 0, ebx, 23:16, rap_size , Return Address Predictor size
|
|
|
|
# Leaf 80000022H
|
|
# AMD extended performance monitoring
|
|
|
|
0x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2
|
|
0x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack)
|
|
0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack
|
|
0x80000022, 0, ebx, 3:0, n_pmc_core , Number of core performance counters
|
|
0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of LBR stack entries
|
|
0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of northbridge performance counters
|
|
0x80000022, 0, ebx, 21:16, n_pmc_umc , Number of UMC performance counters
|
|
0x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMCs bitmask
|
|
|
|
# Leaf 80000023H
|
|
# AMD multi-key encrypted memory
|
|
|
|
0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode
|
|
0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , Total number of available encryption keys
|
|
|
|
# Leaf 80000026H
|
|
# AMD extended CPU topology
|
|
|
|
0x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
|
|
0x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core has a power efficiency ranking
|
|
0x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domain level has hybrid (E, P) cores
|
|
0x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Core' domain has asymmetric cores count
|
|
0x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number of logical CPUs at this domain instance
|
|
0x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This core's static power efficiency ranking
|
|
0x80000026, 3:0, ebx, 27:24, core_native_model_id , This core's native model ID
|
|
0x80000026, 3:0, ebx, 31:28, core_type , This core's type
|
|
0x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
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0x80000026, 3:0, ecx, 15:8, domain_type , This domain type
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0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
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# Leaf 80860000H
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# Maximum Transmeta leaf + CPU vendor string
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0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum Transmeta leaf
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0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta vendor ID string bytes 0 - 3
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0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta vendor ID string bytes 8 - 11
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0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta vendor ID string bytes 4 - 7
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# Leaf 80860001H
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# Transmeta extended CPU features
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0x80860001, 0, eax, 3:0, stepping , Stepping ID
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0x80860001, 0, eax, 7:4, base_model , Base CPU model ID
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0x80860001, 0, eax, 11:8, base_family_id , Base CPU family ID
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0x80860001, 0, eax, 13:12, cpu_type , CPU type
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0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revision ID, mask minor
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0x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revision ID, mask major
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0x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revision ID, minor
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0x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revision ID, major
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0x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nominal frequency, in MHz
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0x80860001, 0, edx, 0, recovery , Recovery CMS is active (after bad flush)
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0x80860001, 0, edx, 1, longrun , LongRun power management capabilities
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0x80860001, 0, edx, 3, lrti , LongRun Table Interface
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# Leaf 80860002H
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# Transmeta CMS (Code Morphing Software)
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0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revision ID
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0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revision ID, mask component 2
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0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revision ID, mask component 1
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0x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revision ID, minor
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0x80860002, 0, ebx, 31:24, cms_rev_major , CMS revision ID, major
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0x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revision ID, mask component 3
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# Leaf 80860003H
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# Transmeta CPU information string, bytes 0 - 15
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0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info string bytes 0 - 3
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0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info string bytes 4 - 7
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0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info string bytes 8 - 11
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0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info string bytes 12 - 15
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# Leaf 80860004H
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# Transmeta CPU information string, bytes 16 - 31
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0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info string bytes 16 - 19
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0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info string bytes 20 - 23
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0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info string bytes 24 - 27
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0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info string bytes 28 - 31
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# Leaf 80860005H
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# Transmeta CPU information string, bytes 32 - 47
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0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info string bytes 32 - 35
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0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info string bytes 36 - 39
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0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info string bytes 40 - 43
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0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info string bytes 44 - 47
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# Leaf 80860006H
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# Transmeta CPU information string, bytes 48 - 63
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0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info string bytes 48 - 51
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0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info string bytes 52 - 55
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0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info string bytes 56 - 59
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0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info string bytes 60 - 63
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# Leaf 80860007H
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# Transmeta live CPU information
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0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current CPU frequency, in MHz
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0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current CPU voltage, in millivolts
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0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current CPU performance percentage, 0 - 100
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0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current CPU gate delay, in femtoseconds
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# Leaf C0000000H
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# Maximum Centaur/Zhaoxin leaf
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0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum Centaur/Zhaoxin leaf
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# Leaf C0000001H
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# Centaur/Zhaoxin extended CPU features
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0xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 instructions
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0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 enabled
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0xc0000001, 0, edx, 2, xstore , Random Number Generator
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0xc0000001, 0, edx, 3, xstore_en , RNG enabled
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0xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 and SM4 instructions
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0xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/SM4 enabled
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0xc0000001, 0, edx, 6, ace , Advanced Cryptography Engine
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0xc0000001, 0, edx, 7, ace_en , ACE enabled
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0xc0000001, 0, edx, 8, ace2 , Advanced Cryptography Engine v2
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0xc0000001, 0, edx, 9, ace2_en , ACE v2 enabled
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0xc0000001, 0, edx, 10, phe , PadLock Hash Engine
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0xc0000001, 0, edx, 11, phe_en , PHE enabled
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0xc0000001, 0, edx, 12, pmm , PadLock Montgomery Multiplier
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0xc0000001, 0, edx, 13, pmm_en , PMM enabled
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0xc0000001, 0, edx, 16, parallax , Parallax auto adjust processor voltage
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0xc0000001, 0, edx, 17, parallax_en , Parallax enabled
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0xc0000001, 0, edx, 20, tm3 , Thermal Monitor v3
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0xc0000001, 0, edx, 21, tm3_en , TM v3 enabled
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0xc0000001, 0, edx, 25, phe2 , PadLock Hash Engine v2 (SHA384/SHA512)
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0xc0000001, 0, edx, 26, phe2_en , PHE v2 enabled
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0xc0000001, 0, edx, 27, rsa , RSA instructions (XMODEXP/MONTMUL2)
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0xc0000001, 0, edx, 28, rsa_en , RSA instructions enabled
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