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383d0fb894
XGBE_PTP_ACT_CLK_FREQ and XGBE_V2_PTP_ACT_CLK_FREQ were 10x too
large (500MHz/1GHz instead of 50MHz/100MHz), causing the computed
addend to overflow the 32-bit tstamp_addend. In the general case
this would result in the clock advancing at the wrong rate. For v2
(PCI), ptpclk_rate is hardcoded to 125MHz, so the addend formula
(ACT_CLK_FREQ << 32) / ptpclk_rate yields exactly 8 * 2^32, and
when stored to the 32-bit tstamp_addend the value is zero. With
addend = 0 the hardware accumulator never overflows and the PTP
clock is fully stopped. For v1 (platform), ptpclk_rate is read from
ACPI/DT so the exact overflow behavior depends on the
firmware-reported frequency.
Define the constants as NSEC_PER_SEC / SSINC so the relationship is
explicit and cannot drift out of sync.
Fixes:
|
||
|---|---|---|
| .. | ||
| pds_core | ||
| xgbe | ||
| 7990.c | ||
| 7990.h | ||
| a2065.c | ||
| a2065.h | ||
| amd8111e.c | ||
| amd8111e.h | ||
| ariadne.c | ||
| ariadne.h | ||
| atarilance.c | ||
| au1000_eth.c | ||
| au1000_eth.h | ||
| declance.c | ||
| hplance.c | ||
| hplance.h | ||
| Kconfig | ||
| Makefile | ||
| mvme147.c | ||
| pcnet32.c | ||
| sun3lance.c | ||
| sunlance.c | ||