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declance: Include the offending address with DMA errors

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The address latched in the I/O ASIC LANCE DMA Pointer Register uses the
TURBOchannel bus address encoding and therefore bits 33:29 of location
referred occupy bits 4:0, bits 28:2 are left-shifted by 3, and bits 1:0
are hardwired to zero.  In reality no TURBOchannel system exceeds 1GiB
of RAM though, so the address reported will always fit in 8 hex digits.

Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Link: https://patch.msgid.link/alpine.DEB.2.21.2603291839220.60268@angie.orcam.me.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Maciej W. Rozycki 2026-03-29 19:07:41 +01:00 committed by Jakub Kicinski
parent ee769323b1
commit aae5efaeb8
1 changed files with 3 additions and 1 deletions
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4
drivers/net/ethernet/amd/declance.c
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@ -726,8 +726,10 @@ static void lance_tx(struct net_device *dev)
static irqreturn_t lance_dma_merr_int(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
u64 ldp = ioasic_read(IO_REG_LANCE_DMA_P);
pr_err_ratelimited("%s: DMA error\n", dev->name);
pr_err_ratelimited("%s: DMA error at %#010llx\n", dev->name,
(ldp & 0x1f) << 29 | (ldp & 0xffffffe0) >> 3);
return IRQ_HANDLED;
}