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cbfd04ca56
Add support for reading and writing the oversampling ratio through the IIO oversampling_ratio attribute. The hardware supports averaging 2, 4, 8, or 16 samples, plus a ratio of 1 (no averaging). Temperature and supply channels share oversampling configuration at the type level (all temperature channels share one ratio, all supply channels share another), exposed through info_mask_shared_by_type. The hardware encoding uses sample_count / 2 in a 4-bit field within the CONFIG register. Per-channel averaging enable registers must also be updated to activate or deactivate averaging. Signed-off-by: Salih Erim <salih.erim@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
121 lines
3.6 KiB
C
121 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Versal SysMon driver
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*
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* Copyright (C) 2019 - 2022, Xilinx, Inc.
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* Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
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*/
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#ifndef _VERSAL_SYSMON_H_
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#define _VERSAL_SYSMON_H_
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#include <linux/bits.h>
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#include <linux/mutex.h>
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#include <linux/spinlock_types.h>
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#include <linux/workqueue.h>
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struct device;
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struct regmap;
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/* Register offsets (sorted by address) */
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#define SYSMON_NPI_LOCK 0x000C
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#define SYSMON_ISR 0x0044
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#define SYSMON_IMR 0x0048
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#define SYSMON_IER 0x004C
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#define SYSMON_IDR 0x0050
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#define SYSMON_CONFIG 0x0100
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#define SYSMON_TEMP_MAX 0x1030
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#define SYSMON_TEMP_MIN 0x1034
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#define SYSMON_SUPPLY_BASE 0x1040
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#define SYSMON_ALARM_FLAG 0x1018
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#define SYSMON_ALARM_REG 0x1940
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#define SYSMON_SUPPLY_EN_AVG_BASE 0x1958
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#define SYSMON_TEMP_TH_LOW 0x1970
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#define SYSMON_TEMP_TH_UP 0x1974
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#define SYSMON_SUPPLY_TH_LOW 0x1980
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#define SYSMON_SUPPLY_TH_UP 0x1C80
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#define SYSMON_TEMP_EV_CFG 0x1F84
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#define SYSMON_TEMP_MIN_MIN 0x1F8C
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#define SYSMON_TEMP_MAX_MAX 0x1F90
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#define SYSMON_STATUS_RESET 0x1F94
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#define SYSMON_TEMP_SAT_BASE 0x1FAC
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#define SYSMON_TEMP_EN_AVG_BASE 0x24B4
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#define SYSMON_MAX_REG 0x24C0
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/* NPI unlock value written to SYSMON_NPI_LOCK */
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#define SYSMON_NPI_UNLOCK_CODE 0xF9E8D7C6
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/* Register stride: 4 bytes per 32-bit register */
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#define SYSMON_REG_STRIDE 4
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#define SYSMON_SUPPLY_IDX_MAX 159
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#define SYSMON_TEMP_SAT_MAX 64
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#define SYSMON_NO_OF_EVENTS 32
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#define SYSMON_INTR_ALL_MASK GENMASK(31, 0)
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/* ISR/IMR temperature alarm mask (bit 9) */
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#define SYSMON_TEMP_INTR_MASK BIT(9)
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/* SYSMON_CONFIG: supply oversampling ratio */
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#define SYSMON_CONFIG_SUPPLY_OSR GENMASK(17, 14)
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/* SYSMON_CONFIG: temperature satellite oversampling ratio */
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#define SYSMON_CONFIG_TEMP_SAT_OSR GENMASK(27, 24)
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/* Per-channel averaging enable register counts */
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#define SYSMON_SUPPLY_EN_AVG_COUNT 5
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#define SYSMON_TEMP_EN_AVG_COUNT 2
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/* Supply voltage conversion register fields */
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#define SYSMON_MANTISSA_MASK GENMASK(15, 0)
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#define SYSMON_FMT_MASK BIT(16)
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#define SYSMON_MODE_MASK GENMASK(18, 17)
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/* Q8.7 fractional shift */
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#define SYSMON_FRACTIONAL_SHIFT 7U
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#define SYSMON_SUPPLY_MANTISSA_BITS 16
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/* Bits per alarm register */
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#define SYSMON_ALARM_BITS_PER_REG 32
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#define SYSMON_UNMASK_WORK_DELAY_MS 500
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/**
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* struct sysmon - Driver data for Versal SysMon
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* @regmap: register map for hardware access
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* @lock: protects read-modify-write sequences on threshold registers
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* and cached state that spans multiple regmap calls
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* @irq_lock: protects interrupt mask register updates (MMIO path only)
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* @masked_temp: currently masked temperature alarm bits
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* @temp_mask: temperature interrupt configuration mask
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* @temp_hysteresis: cached DEVICE_TEMP hysteresis in millicelsius
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* @sysmon_unmask_work: re-enables events after alarm condition clears
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* @temp_oversampling: current temp oversampling ratio
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* @supply_oversampling: current supply oversampling ratio
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*/
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struct sysmon {
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struct regmap *regmap;
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/*
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* Protects read-modify-write sequences on threshold registers
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* and cached state (oversampling ratios, hysteresis values)
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* that spans multiple regmap calls.
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*/
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struct mutex lock;
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/*
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* Protects interrupt mask register updates. Only used on the
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* MMIO path (fast_io regmap); I2C has no IRQ and never reaches
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* the event code that takes this lock.
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*/
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spinlock_t irq_lock;
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unsigned int masked_temp;
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unsigned int temp_mask;
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int temp_hysteresis;
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struct delayed_work sysmon_unmask_work;
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unsigned int temp_oversampling;
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unsigned int supply_oversampling;
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};
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int devm_versal_sysmon_core_probe(struct device *dev, struct regmap *regmap);
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#endif /* _VERSAL_SYSMON_H_ */
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