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2dbf9b7562
Add low-level DPLL channel operations for ToD read/write/adjust, output phase step, delta frequency offset write and TIE (Time Interval Error) write. These serve as building blocks for the PTP clock callbacks added in the next patch. ToD operations use a wait-before-write pattern to avoid blocking after each operation. The tod_ready_wait helper selects the poll timeout based on the current ToD command - write operations use a longer timeout (1000 ms) than reads (30 ms). The ToD read captures system timestamps (ptp_system_timestamp) around the HW command and completion poll to support cross-timestamping. The TIE write operation provides sub-picosecond resolution phase adjustment for modes where the DPLL is tracking a reference (AUTO and REFLOCK). Add output step-time mask to struct zl3073x_dev and zl3073x_dev_out_is_stepped() helper to check if an output participates in step-time operations. Reviewed-by: Petr Oros <poros@redhat.com> Tested-by: Chris du Quesnay <Chris.duQuesnay@microchip.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Link: https://patch.msgid.link/20260814082656.306534-3-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
420 lines
14 KiB
C
420 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ZL3073X_REGS_H
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#define _ZL3073X_REGS_H
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/limits.h>
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/*
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* Hardware limits for ZL3073x chip family
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*/
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#define ZL3073X_MAX_CHANNELS 5
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#define ZL3073X_NUM_REFS 10
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#define ZL3073X_NUM_OUTS 10
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#define ZL3073X_NUM_SYNTHS 5
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#define ZL3073X_NUM_INPUT_PINS ZL3073X_NUM_REFS
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#define ZL3073X_NUM_OUTPUT_PINS (ZL3073X_NUM_OUTS * 2)
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#define ZL3073X_NUM_PINS (ZL3073X_NUM_INPUT_PINS + \
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ZL3073X_NUM_OUTPUT_PINS)
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#define ZL3073X_NCO_PIN_ID ZL3073X_NUM_PINS
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/*
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* Register address structure:
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* ===========================
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* 25 19 18 16 15 7 6 0
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* +------------------------------------------+
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* | max_offset | size | page | page_offset |
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* +------------------------------------------+
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*
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* page_offset ... <0x00..0x7F>
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* page .......... HW page number
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* size .......... register byte size (1, 2, 4 or 6)
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* max_offset .... maximal offset for indexed registers
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* (for non-indexed regs max_offset == page_offset)
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*/
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#define ZL_REG_OFFSET_MASK GENMASK(6, 0)
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#define ZL_REG_PAGE_MASK GENMASK(15, 7)
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#define ZL_REG_SIZE_MASK GENMASK(18, 16)
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#define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19)
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#define ZL_REG_ADDR_MASK GENMASK(15, 0)
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#define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg)
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#define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg)
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#define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg)
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#define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg)
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#define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg)
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/**
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* ZL_REG_IDX - define indexed register
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* @_idx: index of register to access
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* @_page: register page
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* @_offset: register offset in page
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* @_size: register byte size (1, 2, 4 or 6)
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* @_items: number of register indices
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* @_stride: stride between items in bytes
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*
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* All parameters except @_idx should be constant.
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*/
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#define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \
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(FIELD_PREP(ZL_REG_OFFSET_MASK, \
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(_offset) + (_idx) * (_stride)) | \
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FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \
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FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \
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FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \
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(_offset) + ((_items) - 1) * (_stride)))
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/**
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* ZL_REG - define simple (non-indexed) register
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* @_page: register page
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* @_offset: register offset in page
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* @_size: register byte size (1, 2, 4 or 6)
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*
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* All parameters should be constant.
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*/
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#define ZL_REG(_page, _offset, _size) \
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ZL_REG_IDX(0, _page, _offset, _size, 1, 0)
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/**************************
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* Register Page 0, General
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**************************/
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#define ZL_REG_INFO ZL_REG(0, 0x00, 1)
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#define ZL_INFO_READY BIT(7)
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#define ZL_REG_ID ZL_REG(0, 0x01, 2)
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#define ZL_REG_REVISION ZL_REG(0, 0x03, 2)
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#define ZL_REG_FW_VER ZL_REG(0, 0x05, 2)
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#define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4)
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#define ZL_REG_RESET_STATUS ZL_REG(0, 0x18, 1)
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#define ZL_REG_RESET_STATUS_RESET BIT(0)
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#define ZL_REG_DIE_TEMP_STATUS ZL_REG(0, 0x44, 2)
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/*************************
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* Register Page 2, Status
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*************************/
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#define ZL_REG_REF_MON_STATUS(_idx) \
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ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1)
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#define ZL_REF_MON_STATUS_OK 0
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#define ZL_REF_MON_STATUS_LOS BIT(0)
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#define ZL_REF_MON_STATUS_SCM BIT(1)
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#define ZL_REF_MON_STATUS_CFM BIT(2)
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#define ZL_REF_MON_STATUS_GST BIT(3)
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#define ZL_REF_MON_STATUS_PFM BIT(4)
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#define ZL_REF_MON_STATUS_ESYNC BIT(6)
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#define ZL_REF_MON_STATUS_SPLIT_XO BIT(7)
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#define ZL_REG_DPLL_MON_STATUS(_idx) \
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ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1)
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#define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0)
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#define ZL_DPLL_MON_STATUS_STATE_ACQUIRING 0
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#define ZL_DPLL_MON_STATUS_STATE_LOCK 1
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#define ZL_DPLL_MON_STATUS_STATE_HOLDOVER 2
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#define ZL_DPLL_MON_STATUS_HO_READY BIT(2)
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#define ZL_REG_DPLL_REFSEL_STATUS(_idx) \
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ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1)
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#define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0)
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#define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4)
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#define ZL_DPLL_REFSEL_STATUS_STATE_LOCK 4
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#define ZL_REG_REF_FREQ(_idx) \
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ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4)
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/**********************
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* Register Page 4, Ref
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**********************/
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#define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1)
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#define ZL_REF_PHASE_ERR_READ_RQST_RD BIT(0)
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#define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1)
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#define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0)
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#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ 1
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#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF 2
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#define ZL_REF_FREQ_MEAS_CTRL_DPLL_FREQ_OFF 3
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#define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1)
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#define ZL_REF_FREQ_MEAS_MASK_3_0(_ref) BIT(_ref)
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#define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1)
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#define ZL_REF_FREQ_MEAS_MASK_4(_ref) BIT((_ref) - 8)
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#define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1)
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#define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN BIT(0)
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#define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX GENMASK(6, 4)
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#define ZL_REG_REF_PHASE(_idx) \
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ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6)
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/***********************
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* Register Page 5, DPLL
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***********************/
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#define ZL_REG_DPLL_MODE_REFSEL(_idx) \
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ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4)
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#define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0)
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#define ZL_DPLL_MODE_REFSEL_MODE_FREERUN 0
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#define ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER 1
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#define ZL_DPLL_MODE_REFSEL_MODE_REFLOCK 2
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#define ZL_DPLL_MODE_REFSEL_MODE_AUTO 3
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#define ZL_DPLL_MODE_REFSEL_MODE_NCO 4
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#define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4)
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#define ZL_REG_DPLL_CTRL(_idx) \
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ZL_REG_IDX(_idx, 5, 0x05, 1, ZL3073X_MAX_CHANNELS, 4)
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#define ZL_DPLL_CTRL_TIE_CLEAR BIT(0)
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#define ZL_DPLL_CTRL_TOD_STEP_RST BIT(2)
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#define ZL_DPLL_CTRL_NCO_AUTO_READ BIT(7)
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#define ZL_REG_DPLL_DF_READ(_idx) \
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ZL_REG_IDX(_idx, 5, 0x28, 1, ZL3073X_MAX_CHANNELS, 1)
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#define ZL_DPLL_DF_READ_SEM BIT(4)
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#define ZL_DPLL_DF_READ_REF_OFST BIT(3)
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#define ZL_DPLL_DF_READ_CMD GENMASK(2, 0)
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#define ZL_DPLL_DF_READ_CMD_ACC_I 4
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#define ZL_REG_DPLL_TIE_CTRL ZL_REG(5, 0x30, 1)
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#define ZL_DPLL_TIE_CTRL_OP GENMASK(2, 0)
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#define ZL_DPLL_TIE_CTRL_OP_WR 4
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#define ZL_REG_DPLL_TIE_CTRL_MASK ZL_REG(5, 0x31, 1)
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#define ZL_REG_DPLL_TOD_CTRL(_idx) \
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ZL_REG_IDX(_idx, 5, 0x38, 1, ZL3073X_MAX_CHANNELS, 1)
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#define ZL_DPLL_TOD_CTRL_SEM BIT(4)
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#define ZL_DPLL_TOD_CTRL_CMD GENMASK(3, 0)
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#define ZL_DPLL_TOD_CTRL_CMD_WR_NEXT_1HZ 1
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#define ZL_DPLL_TOD_CTRL_CMD_RD_CURRENT 8
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#define ZL_DPLL_TOD_CTRL_CMD_RD_NEXT_1HZ 9
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#define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1)
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#define ZL_DPLL_MEAS_CTRL_EN BIT(0)
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#define ZL_DPLL_MEAS_CTRL_AVG_FACTOR GENMASK(7, 4)
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#define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1)
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#define ZL_DPLL_MEAS_IDX GENMASK(2, 0)
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#define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1)
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#define ZL_REG_DPLL_PHASE_ERR_DATA(_idx) \
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ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6)
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/*******************************
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* Register Pages 6-7, DPLL Data
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*
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* Per-channel registers with stride 0x20. Channels 0-3 reside on page 6,
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* channel 4 on page 7.
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*******************************/
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#define ZL_REG_DPLL_DF_OFFSET_03(_idx) \
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ZL_REG_IDX(_idx, 6, 0x00, 6, 4, 0x20)
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#define ZL_REG_DPLL_DF_OFFSET_4 ZL_REG(7, 0x00, 6)
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#define ZL_REG_DPLL_DF_OFFSET(_idx) \
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((_idx) < 4 ? ZL_REG_DPLL_DF_OFFSET_03(_idx) : ZL_REG_DPLL_DF_OFFSET_4)
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#define ZL_DPLL_DF_OFFSET_UNKNOWN S64_MIN
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#define ZL_REG_DPLL_TIE_DATA_03(_idx) \
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ZL_REG_IDX(_idx, 6, 0x0C, 6, 4, 0x20)
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#define ZL_REG_DPLL_TIE_DATA_4 ZL_REG(7, 0x0C, 6)
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#define ZL_REG_DPLL_TIE_DATA(_idx) \
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((_idx) < 4 ? ZL_REG_DPLL_TIE_DATA_03(_idx) : ZL_REG_DPLL_TIE_DATA_4)
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#define ZL_REG_DPLL_TOD_SEC_03(_idx) \
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ZL_REG_IDX(_idx, 6, 0x12, 6, 4, 0x20)
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#define ZL_REG_DPLL_TOD_SEC_4 ZL_REG(7, 0x12, 6)
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#define ZL_REG_DPLL_TOD_SEC(_idx) \
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((_idx) < 4 ? ZL_REG_DPLL_TOD_SEC_03(_idx) : ZL_REG_DPLL_TOD_SEC_4)
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#define ZL_REG_DPLL_TOD_NS_03(_idx) \
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ZL_REG_IDX(_idx, 6, 0x18, 4, 4, 0x20)
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#define ZL_REG_DPLL_TOD_NS_4 ZL_REG(7, 0x18, 4)
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#define ZL_REG_DPLL_TOD_NS(_idx) \
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((_idx) < 4 ? ZL_REG_DPLL_TOD_NS_03(_idx) : ZL_REG_DPLL_TOD_NS_4)
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/***********************************
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* Register Page 9, Synth and Output
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***********************************/
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#define ZL_REG_SYNTH_CTRL(_idx) \
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ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1)
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#define ZL_SYNTH_CTRL_EN BIT(0)
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#define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4)
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#define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1)
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#define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1)
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#define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1)
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#define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2)
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#define ZL_REG_OUTPUT_CTRL(_idx) \
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ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1)
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#define ZL_OUTPUT_CTRL_EN BIT(0)
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#define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4)
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#define ZL_REG_OUTPUT_STEP_TIME_MASK ZL_REG(9, 0x36, 2)
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#define ZL_REG_OUTPUT_PHASE_STEP_CTRL ZL_REG(9, 0x38, 1)
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#define ZL_OUTPUT_PHASE_STEP_CTRL_DPLL GENMASK(6, 4)
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#define ZL_OUTPUT_PHASE_STEP_CTRL_TOD_STEP BIT(3)
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#define ZL_OUTPUT_PHASE_STEP_CTRL_OP GENMASK(1, 0)
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#define ZL_OUTPUT_PHASE_STEP_CTRL_OP_NONE 0
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#define ZL_OUTPUT_PHASE_STEP_CTRL_OP_RESET 1
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#define ZL_OUTPUT_PHASE_STEP_CTRL_OP_READ 2
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#define ZL_OUTPUT_PHASE_STEP_CTRL_OP_WRITE 3
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#define ZL_REG_OUTPUT_PHASE_STEP_NUMBER ZL_REG(9, 0x39, 1)
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#define ZL_REG_OUTPUT_PHASE_STEP_MASK ZL_REG(9, 0x3a, 2)
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#define ZL_REG_OUTPUT_PHASE_STEP_DATA ZL_REG(9, 0x3c, 4)
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/*******************************
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* Register Page 10, Ref Mailbox
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*******************************/
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#define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2)
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#define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1)
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#define ZL_REF_MB_SEM_WR BIT(0)
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#define ZL_REF_MB_SEM_RD BIT(1)
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#define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2)
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#define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2)
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#define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2)
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#define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2)
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#define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1)
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#define ZL_REF_CONFIG_ENABLE BIT(0)
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#define ZL_REF_CONFIG_DIFF_EN BIT(2)
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#define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6)
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#define ZL_REG_REF_PHASE_OFFSET_COMP_32 ZL_REG(10, 0x28, 4)
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#define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1)
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#define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0)
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#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0
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#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR 1
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#define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75 2
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#define ZL_REF_SYNC_CTRL_PAIR GENMASK(7, 4)
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#define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4)
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#define ZL_REF_ESYNC_DIV_1HZ 0
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/********************************
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* Register Page 12, DPLL Mailbox
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********************************/
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#define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2)
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#define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1)
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#define ZL_DPLL_MB_SEM_WR BIT(0)
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#define ZL_DPLL_MB_SEM_RD BIT(1)
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#define ZL_REG_DPLL_REF_PRIO(_idx) \
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ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1)
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#define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0)
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#define ZL_DPLL_REF_PRIO_REF_N GENMASK(7, 4)
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#define ZL_DPLL_REF_PRIO_MAX 14
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#define ZL_DPLL_REF_PRIO_NONE 15
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/*********************************
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* Register Page 13, Synth Mailbox
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*********************************/
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#define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2)
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#define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1)
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#define ZL_SYNTH_MB_SEM_WR BIT(0)
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#define ZL_SYNTH_MB_SEM_RD BIT(1)
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#define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2)
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#define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4)
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#define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2)
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#define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2)
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/**********************************
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* Register Page 14, Output Mailbox
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**********************************/
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#define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2)
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#define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1)
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#define ZL_OUTPUT_MB_SEM_WR BIT(0)
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#define ZL_OUTPUT_MB_SEM_RD BIT(1)
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#define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1)
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#define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0)
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#define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL 0
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#define ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC 1
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4)
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS 1
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DIFF 2
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LOWVCM 3
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2 4
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1P 5
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1N 6
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_INV 7
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV 12
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#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV 15
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#define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4)
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#define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4)
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#define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4)
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#define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4)
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#define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4)
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/*
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* Register Page 255 - HW registers access
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*/
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#define ZL_REG_HWREG_OP ZL_REG(0xff, 0x00, 1)
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#define ZL_HWREG_OP_WRITE 0x28
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#define ZL_HWREG_OP_READ 0x29
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#define ZL_HWREG_OP_PENDING BIT(1)
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#define ZL_REG_HWREG_ADDR ZL_REG(0xff, 0x04, 4)
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#define ZL_REG_HWREG_WRITE_DATA ZL_REG(0xff, 0x08, 4)
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#define ZL_REG_HWREG_READ_DATA ZL_REG(0xff, 0x0c, 4)
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/*
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* Registers available in flash mode
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*/
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#define ZL_REG_FLASH_HASH ZL_REG(0, 0x78, 4)
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#define ZL_REG_FLASH_FAMILY ZL_REG(0, 0x7c, 1)
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#define ZL_REG_FLASH_RELEASE ZL_REG(0, 0x7d, 1)
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#define ZL_REG_HOST_CONTROL ZL_REG(1, 0x02, 1)
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#define ZL_HOST_CONTROL_ENABLE BIT(0)
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#define ZL_REG_IMAGE_START_ADDR ZL_REG(1, 0x04, 4)
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#define ZL_REG_IMAGE_SIZE ZL_REG(1, 0x08, 4)
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#define ZL_REG_FLASH_INDEX_READ ZL_REG(1, 0x0c, 4)
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#define ZL_REG_FLASH_INDEX_WRITE ZL_REG(1, 0x10, 4)
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#define ZL_REG_FILL_PATTERN ZL_REG(1, 0x14, 4)
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#define ZL_REG_WRITE_FLASH ZL_REG(1, 0x18, 1)
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#define ZL_WRITE_FLASH_OP GENMASK(2, 0)
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#define ZL_WRITE_FLASH_OP_DONE 0x0
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#define ZL_WRITE_FLASH_OP_SECTORS 0x2
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#define ZL_WRITE_FLASH_OP_PAGE 0x3
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#define ZL_WRITE_FLASH_OP_COPY_PAGE 0x4
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#define ZL_REG_FLASH_INFO ZL_REG(2, 0x00, 1)
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#define ZL_FLASH_INFO_SECTOR_SIZE GENMASK(3, 0)
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#define ZL_FLASH_INFO_SECTOR_4K 0
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#define ZL_FLASH_INFO_SECTOR_64K 1
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#define ZL_REG_ERROR_COUNT ZL_REG(2, 0x04, 4)
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#define ZL_REG_ERROR_CAUSE ZL_REG(2, 0x08, 4)
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#define ZL_REG_OP_STATE ZL_REG(2, 0x14, 1)
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#define ZL_OP_STATE_NO_COMMAND 0
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#define ZL_OP_STATE_PENDING 1
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#define ZL_OP_STATE_DONE 2
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#endif /* _ZL3073X_REGS_H */
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