Conor Dooley 2f7ae8ab6a clk: microchip: mpfs-ccc: fix out of bounds access during output registration ... UBSAN reported an out of bounds access during registration of the last two outputs. This out of bounds access occurs because space is only allocated in the hws array for two PLLs and the four output dividers that each has, but the defined IDs contain two DLLS and their two outputs each, which are not supported by the driver. The ID order is PLLs -> DLLs -> PLL outputs -> DLL outputs. Decrement the PLL output IDs by two while adding them to the array to avoid the problem. Fixes: d39fb17276 ("clk: microchip: add PolarFire SoC fabric clock support") CC: stable@vger.kernel.org Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2026-03-02 17:12:45 +00:00
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clk-core.c	cleanups and fixes	2026-02-16 09:30:44 -08:00
clk-core.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445	2019-06-05 17:37:18 +02:00
clk-mpfs-ccc.c	clk: microchip: mpfs-ccc: fix out of bounds access during output registration	2026-03-02 17:12:45 +00:00
clk-mpfs.c	reset: mpfs: add non-auxiliary bus probing	2025-11-11 16:47:24 +00:00
clk-pic32mzda.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
Kconfig	Revert "clk: microchip: core: allow driver to be compiled with COMPILE_TEST"	2026-02-10 16:48:59 +01:00
Makefile	clk: microchip: add PolarFire SoC fabric clock support	2022-09-14 10:57:07 +03:00