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c3029c3817
Convert the repeated register save/restore sequences into macros, trading some level of implementation trickiness for conciseness (more than one register can be saved/restored with one invocation) and a smaller chance of cut and paste errors. This is particularly useful in preparation for extended GPR support; upcoming support for APX would need to add 32 lines to the VM entry/exit paths. No functional change intended. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Link: https://lore.kernel.org/6e67df0e-e5f0-43f5-aa86-22e8b01b75d2@redhat.com Link: https://patch.msgid.link/20260512011502.53072-2-chang.seok.bae@intel.com/ [Keep kvm_vcpu_regs.h and put the macros in there. -Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
112 lines
2.8 KiB
C
112 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMENTER_H
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#define __KVM_X86_VMENTER_H
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#include <asm/kvm_vcpu_regs.h>
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#define KVM_ENTER_VMRESUME BIT(0)
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#define KVM_ENTER_SAVE_SPEC_CTRL BIT(1)
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#define KVM_ENTER_CLEAR_CPU_BUFFERS_FOR_MMIO BIT(2)
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#ifdef __ASSEMBLER__
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.macro RESTORE_GUEST_SPEC_CTRL_BODY guest_spec_ctrl:req, label:req
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/*
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* SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
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* host's, write the MSR. This is kept out-of-line so that the common
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* case does not have to jump.
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*
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* IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
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* there must not be any returns or indirect branches between this code
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* and vmentry.
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*/
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#ifdef CONFIG_X86_64
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mov \guest_spec_ctrl, %rdx
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cmp PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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je \label
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movl %edx, %eax
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shr $32, %rdx
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#else
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mov \guest_spec_ctrl, %eax
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mov PER_CPU_VAR(x86_spec_ctrl_current), %ecx
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xor %eax, %ecx
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mov 4 + \guest_spec_ctrl, %edx
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mov PER_CPU_VAR(x86_spec_ctrl_current + 4), %esi
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xor %edx, %esi
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or %esi, %ecx
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je \label
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#endif
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mov $MSR_IA32_SPEC_CTRL, %ecx
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wrmsr
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.endm
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.macro RESTORE_HOST_SPEC_CTRL_BODY guest_spec_ctrl:req, enter_flags:req, label:req
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/* Same for after vmexit. */
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mov $MSR_IA32_SPEC_CTRL, %ecx
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/*
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* Load the value that the guest had written into MSR_IA32_SPEC_CTRL,
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* if it was not intercepted during guest execution.
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*/
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testl $KVM_ENTER_SAVE_SPEC_CTRL, \enter_flags
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jz 998f
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rdmsr
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movl %eax, \guest_spec_ctrl
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movl %edx, 4 + \guest_spec_ctrl
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998:
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/* Now restore the host value of the MSR if different from the guest's. */
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#ifdef CONFIG_X86_64
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mov PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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cmp \guest_spec_ctrl, %rdx
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/*
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* For legacy IBRS, the IBRS bit always needs to be written after
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* transitioning from a less privileged predictor mode, regardless of
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* whether the guest/host values differ.
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*/
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ALTERNATIVE __stringify(je \label), "", X86_FEATURE_KERNEL_IBRS
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movl %edx, %eax
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shr $32, %rdx
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#else
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mov PER_CPU_VAR(x86_spec_ctrl_current), %eax
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mov \guest_spec_ctrl, %esi
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xor %eax, %esi
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mov PER_CPU_VAR(x86_spec_ctrl_current + 4), %edx
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mov 4 + \guest_spec_ctrl, %edi
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xor %edx, %edi
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or %edi, %esi
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ALTERNATIVE __stringify(je \label), "", X86_FEATURE_KERNEL_IBRS
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#endif
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wrmsr
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.endm
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#define WORD_SIZE (BITS_PER_LONG / 8)
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.macro LOAD_REGS src:req, regs_ofs:req, regs:vararg
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.irp reg, \regs
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REG_NUM reg_num \reg
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mov (\regs_ofs + reg_num * WORD_SIZE)(\src), \reg
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.endr
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.endm
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.macro STORE_REGS dst:req, regs_ofs:req, regs:vararg
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.irp reg, \regs
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REG_NUM reg_num \reg
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mov \reg, (\regs_ofs + reg_num * WORD_SIZE)(\dst)
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.endr
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.endm
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.macro POP_REGS dst:req, regs_ofs:req, regs:vararg
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.irp reg, \regs
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REG_NUM reg_num \reg
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pop (\regs_ofs + reg_num * WORD_SIZE)(\dst)
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.endr
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.endm
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.macro CLEAR_REGS regs:vararg
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.irp reg, \regs
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xorl \reg, \reg
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.endr
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.endm
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#endif /* __ASSEMBLER__ */
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#endif /* __KVM_X86_VMENTER_H */
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