Yong-Xuan Wang 148ab873d8 RISC-V: errata: Add SiFive MAL-9092 workaround ... SiFive cores with MAL-9092 require fence.rw instructions around HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering when accessing guest memory. Note that HSTATUS.HU is cleared during KVM initialization, restricting hypervisor instructions to HS-mode only. If future changes enable HSTATUS.HU for U-mode access, additional errata considerations will be needed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com Signed-off-by: Paul Walmsley <pjw@kernel.org>		2026-10-05 19:02:38 -06:00
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errata_cip_453.S	riscv: errata: sifive: Use SYM_*() assembly macros	2024-09-15 00:03:22 -07:00
errata.c	RISC-V: errata: Add SiFive MAL-9092 workaround	2026-10-05 19:02:38 -06:00
Makefile	riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled	2021-06-01 21:16:41 -07:00