Michael Neuling 4d2b036994 riscv: errata: Fix bitwise vs logical AND in MIPS errata patching ... The condition checking whether a specific errata needs patching uses logical AND (&&) instead of bitwise AND (&). Since logical AND only checks that both operands are non-zero, this causes all errata patches to be applied whenever any single errata is detected, rather than only applying the matching one. The SiFive errata implementation correctly uses bitwise AND for the same check. Fixes: 0b0ca959d2 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700") Signed-off-by: Michael Neuling <mikey@neuling.org> Assisted-by: Cursor:claude-4.6-opus-high-thinking Link: https://patch.msgid.link/20260409091143.1348853-2-mikey@neuling.org [pjw@kernel.org: fixed checkpatch warning] Signed-off-by: Paul Walmsley <pjw@kernel.org>		2026-04-30 20:00:14 -06:00
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andes	asm-generic: introduce text-patching.h	2024-11-07 14:25:15 -08:00
mips	riscv: errata: Fix bitwise vs logical AND in MIPS errata patching	2026-04-30 20:00:14 -06:00
sifive	errata/sifive: remove unreliable warn_miss_errata	2026-01-25 21:09:04 -07:00
thead	riscv: fix various typos in comments and code	2026-04-04 18:42:39 -06:00
Makefile	riscv: errata: Fix the PAUSE Opcode for MIPS P8700	2025-09-19 10:33:56 -06:00