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18649ffbb6
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
102 lines
2.5 KiB
Plaintext
102 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Anlogic DR1V90";
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compatible = "anlogic,dr1v90";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <800000000>;
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cpu@0 {
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compatible = "nuclei,ux900", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <256>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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reg = <0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
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"zba", "zbb", "zbc", "zbkc", "zbs",
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"zicntr", "zicsr", "zifencei",
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"zihintpause", "zihpm";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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aclint_mswi: interrupt-controller@68031000 {
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compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
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reg = <0x0 0x68031000 0x0 0x4000>;
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interrupts-extended = <&cpu0_intc 3>;
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};
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aclint_mtimer: timer@68035000 {
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compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
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reg = <0x0 0x68035000 0x0 0x8000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu0_intc 7>;
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};
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aclint_sswi: interrupt-controller@6803d000 {
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compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
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reg = <0x0 0x6803d000 0x0 0x3000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 1>;
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};
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plic: interrupt-controller@6c000000 {
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compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
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reg = <0x0 0x6c000000 0x0 0x4000000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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riscv,ndev = <150>;
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};
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uart0: serial@f8400000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8400000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <71>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@f8401000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8401000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <72>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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